Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
GPR0 General Purpose Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAREQ_MUX_SEL0 : Selects between two possible sources for SDMA_EVENT[2]:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
sim2.ipd_sim_tx_dmareq
#1 : 1
uart6.ipd_uart_tx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL1 : Selects between two possible sources for SDMA_EVENT[7]:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
sim2.ipd_sim_rx_dmareq
#1 : 1
uart6.ipd_uart_rx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL2 : Selects between two possible sources for SDMA_EVENT[8]:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
sim1.ipd_sim_tx_dmareq
#1 : 1
uart5.ipd_uart_tx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL3 : Selects between two possible sources for SDMA_EVENT[9]:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
sim1.ipd_sim_rx_dmareq
#1 : 1
uart5.ipd_uart_rx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL4 : Selects between two possible sources for SDMA_EVENT[10]:
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
enet2.ipd_req_mac0_timer[1]
#1 : 1
uart8.ipd_uart_tx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL5 : Selects between two possible sources for SDMA_EVENT[16]:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
enet2.ipd_req_mac0_timer[0]
#1 : 1
uart8.ipd_uart_rx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL6 : Selects between two possible sources for SDMA_EVENT[24]:
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
enet1.ipd_req_mac0_timer[1]
#1 : 1
uart7.ipd_uart_tx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL7 : Selects between two possible sources for SDMA_EVENT[13]:
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
enet1.ipd_req_mac0_timer[0]
#1 : 1
uart7.ipd_uart_rx_dmareq
End of enumeration elements list.
DMAREQ_MUX_SEL8 : Selects between two possible sources for SDMA_EVENT[43]:
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
adc2.ipd_req
#1 : 1
tsc_dig.interrupt
End of enumeration elements list.
DMAREQ_MUX_SEL9 : Selects between two possible sources for SDMA_EVENT[44]:
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
gpt2.ipi_int_gpt
#1 : 1
lcdif.lcdif_irq
End of enumeration elements list.
DMAREQ_MUX_SEL10 : Selects between two possible sources for SDMA_EVENT[45]:
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
epit1.ipi_int_epit_oc
#1 : 1
csi.ipi_csi_int
End of enumeration elements list.
DMAREQ_MUX_SEL11 : Selects between two possible sources for SDMA_EVENT[46]:
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
ecspi4.ipd_req_cspi_tdma
#1 : 1
i2c4.ipi_int
End of enumeration elements list.
DMAREQ_MUX_SEL12 : Selects between two possible sources for SDMA_EVENT[33]:
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
ecspi4.ipd_req_cspi_rdma
#1 : 1
i2c3.ipi_int
End of enumeration elements list.
DMAREQ_MUX_SEL13 : Selects between two possible sources for SDMA_EVENT[34]:
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
ecspi3.ipd_req_cspi_tdma
#1 : 1
i2c2.ipi_int
End of enumeration elements list.
DMAREQ_MUX_SEL14 : Selects between two possible sources for SDMA_EVENT[0]:
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
ecspi3.ipd_req_cspi_rdma
#1 : 1
i2c1.ipi_int
End of enumeration elements list.
DMAREQ_MUX_SEL15 : Selects between two possible sources for SDMA_EVENT[47]:
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
epit2.ipi_int_epit_oc
#1 : 1
pxp.pxp_irq
End of enumeration elements list.
DMAREQ_MUX_SEL16 : Selects between two possible sources for SDMA_EVENT[32]:
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
uart4.ipd_uart_tx_dmareq_b (default)
#1 : 1
sai1.ipd_req_sai_tx
End of enumeration elements list.
DMAREQ_MUX_SEL17 : Selects between two possible sources for SDMA_EVENT[33]:
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
uart5.ipd_uart_rx_dmareq_b (default)
#1 : 1
sai2.ipd_req_sai_rx
End of enumeration elements list.
DMAREQ_MUX_SEL18 : Selects between two possible sources for SDMA_EVENT[34]:
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
uart5.ipd_uart_tx_dmareq_b (default)
#1 : 1
sai2.ipd_req_sai_tx
End of enumeration elements list.
DMAREQ_MUX_SEL19 : Selects between two possible sources for SDMA_EVENT[47]:
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
uart6.ipd_uart_tx_dmareq_b (default)
End of enumeration elements list.
DMAREQ_MUX_SEL20 : Selects between two possible sources for SDMA_EVENT[2]:
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
iomux_top.sdma_events[14] (default)
#1 : 1
csi2.ipi_csi_int_b
End of enumeration elements list.
DMAREQ_MUX_SEL21 : Selects between two possible sources for SDMA_EVENT[29]:
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
uart3.ipd_uart_rx_dmareq_b (default)
End of enumeration elements list.
DMAREQ_MUX_SEL22 : Selects between two possible sources for SDMA_EVENT[30]:
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
uart3.ipd_uart_tx_dmareq_b (default)
End of enumeration elements list.
GPR4 General Purpose Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDMA_STOP_REQ : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
CAN1_STOP_REQ : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
CAN2_STOP_REQ : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
ENET1_STOP_REQ : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
ENET2_STOP_REQ : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
SAI1_STOP_REQ : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
SAI2_STOP_REQ : no description available
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
SAI3_STOP_REQ : no description available
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
stop request off
#1 : 1
stop request on
End of enumeration elements list.
ENET_IPG_CLK_S_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ipg_clk_s is gated when there's no IPS access
#1 : 1
ipg_clk_s is always on
End of enumeration elements list.
SDMA_STOP_ACK : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
SDMA stop acknowledge is not asserted
#1 : 1
SDMA stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
CAN1_STOP_ACK : no description available
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
CAN1 stop acknowledge is not asserted
#1 : 1
CAN1 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
CAN2_STOP_ACK : no description available
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
CAN2 stop acknowledge is not asserted
#1 : 1
CAN2 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
ENET1_STOP_ACK : no description available
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
ENET1 stop acknowledge is not asserted
#1 : 1
ENET1 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
ENET2_STOP_ACK : no description available
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
ENET2 stop acknowledge is not asserted
#1 : 1
ENET2 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
SAI1_STOP_ACK : no description available
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
SAI1 stop acknowledge is not asserted
#1 : 1
SAI1 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
SAI2_STOP_ACK : no description available
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
SAI2 stop acknowledge is not asserted
#1 : 1
SAI2 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
SAI3_STOP_ACK : no description available
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
SAI3 stop acknowledge is not asserted
#1 : 1
SAI3 stop acknowledge is asserted, SDMA is in STOP mode
End of enumeration elements list.
ARM_WFI : no description available
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
ARM Core[GPR5-index] is not in WFI mode
#1 : 1
ARM Core[GPR5-index] is in WFI mode
End of enumeration elements list.
ARM_WFE : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
ARM Core[GPR5-index - 4] is not in WFE mode
#1 : 1
ARM Core[GPR5-index - 4] is in WFE mode
End of enumeration elements list.
GPR5 General Purpose Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDOG1_MASK : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDOG1 Timeout behaves normally
#1 : 1
WDOG1 Timeout is masked
End of enumeration elements list.
WDOG2_MASK : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDOG2 Timeout behaves normally
#1 : 1
WDOG2 Timeout is masked
End of enumeration elements list.
WDOG3_MASK : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDOG3 Timeout behaves normally
#1 : 1
WDOG3 Timeout is masked
End of enumeration elements list.
GPT2_CAPIN1_SEL : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
source from pad
#1 : 1
source from enet1.ipp_do_mac0_timer[3]
End of enumeration elements list.
GPT2_CAPIN2_SEL : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
source from pad
#1 : 1
source from enet2.ipp_do_mac0_timer[3]
End of enumeration elements list.
ENET1_EVENT3IN_SEL : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
event3 source input from pad
#1 : 1
event3 source input from gpt2.ipp_do_cmpout1
End of enumeration elements list.
ENET2_EVENT3IN_SEL : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
event3 source input from pad
#1 : 1
event3 source input from gpt2.ipp_do_cmpout2
End of enumeration elements list.
VREF_1M_CLK_GPT1 : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPT1 ipg_clk_highfreq driven by IPG_PERCLK
#1 : 1
GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock
End of enumeration elements list.
VREF_1M_CLK_GPT2 : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPT2 ipg_clk_highfreq driven by IPG_PERCLK
#1 : 1
GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock
End of enumeration elements list.
REF_1M_CLK_EPIT1 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPIT1 ipg_clk_highfreq driven by IPG_PERCLK
#1 : 1
EPIT1 ipg_clk highfreq driven by anatop 1 MHz clock
End of enumeration elements list.
REF_1M_CLK_EPIT2 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPIT2 ipg_clk_highfreq driven by IPG_PERCLK
#1 : 1
EPIT2 ipg_clk_highfreq driven by anatop 1 MHz clock
End of enumeration elements list.
GPR9 General Purpose Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TZASC1_BYP : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The TZASC-1 is bypassed and the transactions to DDR are not being checked.
#1 : 1
The TZASC-1 is not bypassed and the transactions to DDR are being monitored / checked.
End of enumeration elements list.
GPR10 General Purpose Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Debug turned off.
#1 : 1
Debug enabled (default).
End of enumeration elements list.
DBG_CLK_EN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Debug turned off.
#1 : 1
Debug enabled (default).
End of enumeration elements list.
SEC_ERR_RESP : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OKEY response
#1 : 1
SLVError (default)
End of enumeration elements list.
OCRAM_TZ_EN : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
#1 : 1
The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter.
End of enumeration elements list.
OCRAM_TZ_ADDR : no description available
bits : 11 - 15 (5 bit)
access : read-write
GPR14 General Purpose Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIM1_SIMV2_EMV_SEL : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
select simv2
#1 : 1
select emv
End of enumeration elements list.
SIM2_SIMV2_EMV_SEL : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
select simv2
#1 : 1
select emv
End of enumeration elements list.
GPR : General purpose bits
bits : 2 - 31 (30 bit)
access : read-write
GPR1 General Purpose Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT_CS0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
ADDRS0 : no description available
bits : 1 - 2 (2 bit)
access : read-write
ACT_CS1 : no description available
bits : 3 - 3 (1 bit)
access : read-write
ADDRS1 : no description available
bits : 4 - 5 (2 bit)
access : read-write
ACT_CS2 : no description available
bits : 6 - 6 (1 bit)
access : read-write
ADDRS2 : no description available
bits : 7 - 8 (2 bit)
access : read-write
ACT_CS3 : no description available
bits : 9 - 9 (1 bit)
access : read-write
ADDRS3 : no description available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
32 MByte
#01 : 01
64 MByte
#10 : 10
128 MByte
End of enumeration elements list.
GINT : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global interrupt request is not asserted
#1 : 1
Global interrupt request is asserted
End of enumeration elements list.
ENET1_CLK_SEL : ENET1 reference clock mode select.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
ENET1 TX reference clock driven by ref_enetpll1. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.
#1 : 1
Gets ENET1 TX reference clk from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller
End of enumeration elements list.
ENET2_CLK_SEL : ENET2 reference clock mode select.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
ENET2 TX reference clock driven by ref_enetpll0. This clock is also output to pins via the IOMUX. ENET_REF_CLK2 function.
#1 : 1
Gets ENET2 TX reference clk from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller
End of enumeration elements list.
USB_EXP_MODE : USB Exposure mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Exposure mode is disabled.
#1 : 1
Exposure mode is enabled.
End of enumeration elements list.
ADD_DS : Setting ADD_DS to 0 will make the output driver of the SD3 pins ~10% stronger at highest drive strength (DSE=111). This is for use if the I/O buffer operation at WCS and 200 MHz is marginal.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
output driver ~10% stronger
#1 : 1
output driver is normal
End of enumeration elements list.
ENET1_TX_CLK_DIR : ENET1_TX_CLK data direction control when anatop. ENET_REF_CLK1 is selected (ALT1)
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
ENET1_TX_CLK output driver is disabled when configured for ALT1
#1 : 1
ENET1_TX_CLK output driver is enabled when configured for ALT1
End of enumeration elements list.
ENET2_TX_CLK_DIR : ENET2_TX_CLK data direction control when anatop. ENET_REF_CLK2 is selected (ALT1)
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
ENET2_TX_CLK output driver is disabled when configured for ALT1
#1 : 1
ENET2_TX_CLK output driver is enabled when configured for ALT1
End of enumeration elements list.
SAI1_MCLK_DIR : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD_DATA00 output driver is disabled when configured for ALT8
#1 : 1
LCD_DATA00 output driver is enabled when configured for ALT8
End of enumeration elements list.
SAI2_MCLK_DIR : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD1_CLK output driver is disabled when configured for ALT2
#1 : 1
SD1_CLK output driver is enabled when configured for ALT2
End of enumeration elements list.
SAI3_MCLK_DIR : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD_CLK output driver is disabled when configured for ALT3
#1 : 1
LCD_CLK output driver is enabled when configured for ALT3
End of enumeration elements list.
EXC_MON : Exclusive monitor response select of illegal command
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
OKAY response
#1 : 1
SLVError response (default)
End of enumeration elements list.
TZASC1_BOOT_LOCK : TZASC-1 secure boot lock
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
secure boot lock is disabled
#1 : 1
secure boot lock is enabled
End of enumeration elements list.
ARMA7_CLK_APB_DBG_EN : ARM A7 platform APB clock enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
APB clock is not running (gated)
#1 : 1
APB clock is running (enabled)
End of enumeration elements list.
ARMA7_CLK_ATB_EN : ARM A7 platform ATB clock enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
ATB clock is not running (gated)
#1 : 1
ATB clock is running (enabled)
End of enumeration elements list.
ARMA7_CLK_AHB_EN : ARM A7 platform AHB clock enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
AHB clock is not running (gated)
#1 : 1
AHB clock is running (enabled)
End of enumeration elements list.
GPR2 General Purpose Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PXP_MEM_EN_POWERSAVING : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
#1 : 1
memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels
End of enumeration elements list.
PXP_MEM_SHUTDOWN : no description available
bits : 1 - 1 (1 bit)
access : read-write
PXP_MEM_DEEPSLEEP : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
#1 : 1
force memory into deep sleep mode
End of enumeration elements list.
PXP_MEM_LIGHTSLEEP : no description available
bits : 3 - 3 (1 bit)
access : read-write
LCDIF1_MEM_EN_POWERSAVING : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
#1 : 1
memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels
End of enumeration elements list.
LCDIF1_MEM_SHUTDOWN : no description available
bits : 5 - 5 (1 bit)
access : read-write
LCDIF1_MEM_DEEPSLEEP : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
#1 : 1
force memory into deep sleep mode
End of enumeration elements list.
LCDIF1_MEM_LIGHTSLEEP : no description available
bits : 7 - 7 (1 bit)
access : read-write
LCDIF2_MEM_EN_POWERSAVING : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
#1 : 1
memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels
End of enumeration elements list.
LCDIF2_MEM_SHUTDOWN : no description available
bits : 9 - 9 (1 bit)
access : read-write
LCDIF2_MEM_DEEPSLEEP : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
#1 : 1
force memory into deep sleep mode
End of enumeration elements list.
LCDIF2_MEM_LIGHTSLEEP : no description available
bits : 11 - 11 (1 bit)
access : read-write
L2_MEM_EN_POWERSAVING : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
#1 : 1
memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels
End of enumeration elements list.
L2_MEM_SHUTDOWN : no description available
bits : 13 - 13 (1 bit)
access : read-write
L2_MEM_DEEPSLEEP : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
#1 : 1
force memory into deep sleep mode
End of enumeration elements list.
L2_MEM_LIGHTSLEEP : no description available
bits : 15 - 15 (1 bit)
access : read-write
MQS_CLK_DIV : Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#00000000 : 00000000
mclk frequency = hmclk frequency
#00000001 : 00000001
mclk frequency = 1/2 * hmclk frequency
#00000010 : 00000010
mclk frequency = 1/3 * hmclk frequency
#11111111 : 11111111
mclk frequency = 1/256 * hmclk frequency
End of enumeration elements list.
MQS_SW_RST : MQS software reset.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Exit software reset for MQS
#1 : 1
Enable software reset for MQS
End of enumeration elements list.
MQS_EN : MQS enable.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable MQS
#1 : 1
Enable MQS
End of enumeration elements list.
MQS_OVERSAMPLE : Used to control the PWM oversampling rate compared with mclk.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
32
#1 : 1
64
End of enumeration elements list.
DRAM_RESET_BYPASS : DRAM Reset Bypass Select
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
DRAM reset driven by MMDC PHY Controller
#1 : 1
DRAM reset driven by GPR2 register bit [28]
End of enumeration elements list.
DRAM_RESET : DRAM Reset Value
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive DRAM reset with 0
#1 : 1
Drive DRAM reset with 1
End of enumeration elements list.
DRAM_CKE0 : CKE0 Bypass Value
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive CKE0 with 0
#1 : 1
Drive CKE0 with 1
End of enumeration elements list.
DRAM_CKE1 : CKE1 Bypass Value
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive CKE1 with 0
#1 : 1
Drive CKE1 with 1
End of enumeration elements list.
DRAM_CKE_BYPASS : DRAM CKE Bypass Select
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
DRAM CKE1, CKE0 driven by MMDC PHY Controller
#1 : 1
DRAM CKE1, CKE0 driven by GPR2 register bits [30:29]
End of enumeration elements list.
GPR3 General Purpose Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCRAM_CTL : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
read data pipeline is disabled
#1 : 1
read data pipeline is enabled
End of enumeration elements list.
CORE_DBG_ACK_EN : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Core debug acknowledge is part of global acknowledge.
#1 : 1
Core debug acknowledge is masked by this bit, and it is not part of global acknowledge.
End of enumeration elements list.
OCRAM_STATUS : no description available
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0 : 0
read data pipeline configuration valid
#1 : 1
read data pipeline control bit changed
End of enumeration elements list.
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