Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8C4 byte (0x0)
mem_usage : registers
protection : not protected
MMDC Core Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZ : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#0 : 0
16-bit data bus
End of enumeration elements list.
BL : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst Length 4 is used
#1 : 1
Burst Length 8 is used
End of enumeration elements list.
COL : no description available
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0 : 0
9 bits column
#1 : 1
10 bits column
#10 : 10
11 bits column
#11 : 11
8 bits column
#100 : 100
12 bits column
End of enumeration elements list.
ROW : no description available
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
11 bits Row
#001 : 001
12 bits Row
#010 : 010
13 bits Row
#011 : 011
14 bits Row
#100 : 100
15 bits Row
#101 : 101
16 bits Row
End of enumeration elements list.
SDE_1 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SDE_0 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
MMDC Core Timing Configuration Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tCWL : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : 0
2cycles ( DDR3) , 1 cycle (LPDDR2)
#1 : 1
3cycles ( DDR3) , 2 cycles (LPDDR2)
#10 : 10
4cycles ( DDR3) , 3 cycles (LPDDR2)
#11 : 11
5cycles ( DDR3) , 4 cycles (LPDDR2)
#100 : 100
6cycles ( DDR3) , 5 cycles (LPDDR2)
#101 : 101
7cycles ( DDR3) , 6 cycles (LPDDR2)
#110 : 110
8cycles ( DDR3) , 7 cycles (LPDDR2)
End of enumeration elements list.
tMRD : no description available
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
#1111 : 1111
16 clocks
End of enumeration elements list.
tWR : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#0 : 0
1cycle
#1 : 1
2cycles
#10 : 10
3cycles
#11 : 11
4cycles
#100 : 100
5cycles
#101 : 101
6cycles
#110 : 110
7cycles
#111 : 111
8 cycles
End of enumeration elements list.
tRPA : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Will be equal to: tRP.
#1 : 1
Will be equal to: tRP+1.
End of enumeration elements list.
tRAS : no description available
bits : 16 - 20 (5 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#11110 : 11110
31 clocks
End of enumeration elements list.
tRC : no description available
bits : 21 - 25 (5 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#11110 : 11110
31 clocks
#11111 : 11111
32 clocks
End of enumeration elements list.
tRP : no description available
bits : 26 - 28 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#11 : 11
4 clocks
#100 : 100
5 clocks
#101 : 101
6 clocks
#110 : 110
7 clocks
#111 : 111
8 clocks
End of enumeration elements list.
tRCD : no description available
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#11 : 11
4 clocks
#100 : 100
5 clocks
#101 : 101
6 clocks
#110 : 110
7 clocks
#111 : 111
8 clocks
End of enumeration elements list.
MMDC Core Timing Configuration Register 2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tRRD : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : 0
1cycle
#1 : 1
2cycles
#10 : 10
3cycles
#11 : 11
4cycles
#100 : 100
5cycles
#101 : 101
6cycles
#110 : 110
7cycles
End of enumeration elements list.
tWTR : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#0 : 0
1cycle
#1 : 1
2cycles
#10 : 10
3cycles
#11 : 11
4cycles
#100 : 100
5cycles
#101 : 101
6cycles
#110 : 110
7cycles
#111 : 111
8 cycles
End of enumeration elements list.
tRTP : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#0 : 0
1cycle
#1 : 1
2cycles
#10 : 10
3cycles
#11 : 11
4cycles
#100 : 100
5cycles
#101 : 101
6cycles
#110 : 110
7cycles
#111 : 111
8 cycles
End of enumeration elements list.
tDLLK : no description available
bits : 16 - 24 (9 bit)
access : read-write
Enumeration:
#0 : 0
1 cycle.
#1 : 1
2 cycles.
#10 : 10
3 cycles.
#11000111 : 11000111
200 cycles
#111111110 : 111111110
511 cycles.
#111111111 : 111111111
512 cycles (JEDEC value for DDR3).
End of enumeration elements list.
MMDC Core Miscellaneous Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do nothing.
#1 : 1
Assert reset to the MMDC.
End of enumeration elements list.
DDR_TYPE : no description available
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#0 : 0
DDR3 device is used. (Default)
#1 : 1
LPDDR2 device is used.
End of enumeration elements list.
DDR_4_BANK : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
8 banks device is being used. (Default)
#1 : 1
4 banks device is being used
End of enumeration elements list.
RALAT : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#0 : 0
no additional latency.
#1 : 1
1 cycle additional latency.
#10 : 10
2 cycles additional latency.
#11 : 11
3 cycles additional latency.
#100 : 100
4 cycles additional latency.
#101 : 101
5 cycles additional latency.
#110 : 110
6 cycles additional latency.
#111 : 111
7 cycles additional latency.
End of enumeration elements list.
MIF3_MODE : no description available
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disable prediction.
#01 : 01
Enable prediction based on : Valid access on first pipe line stage.
#10 : 10
Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus.
#11 : 11
Enable prediction based on: Valid access on first pipe line stage, Valid access on axi bus, Next miss access from access queue.
End of enumeration elements list.
LPDDR2_S2 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
LPDDR2-S4 device is used.
#1 : 1
LPDDR2-S2 device is used.
End of enumeration elements list.
BI_ON : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Banks are not interleaved, and address will be decoded as bank-row-column
#1 : 1
Banks are interleaved, and address will be decoded as row-bank-column
End of enumeration elements list.
WALAT : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#0 : 0
No additional latency required.
#1 : 1
1 cycle additional delay
#10 : 10
2 cycles additional delay
#11 : 11
3 cycles additional delay
End of enumeration elements list.
LHD : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Latency hiding on.
#1 : 1
Latency hiding disable.
End of enumeration elements list.
ADDR_MIRROR : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address mirroring disabled.
#1 : 1
Address mirroring enabled.
End of enumeration elements list.
CALIB_PER_CS : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Calibration is targetted to CS0
#1 : 1
Calibration is targetted to CS1
End of enumeration elements list.
CK1_GATING : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
MMDC drives two clocks toward the DDR memory
#1 : 1
MMDC drives only one clock toward the DDR memory (CK0)
End of enumeration elements list.
CS1_RDY : no description available
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
Device in wake-up period.
#1 : 1
Device is ready for initialization.
End of enumeration elements list.
CS0_RDY : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Device in wake-up period.
#1 : 1
Device is ready for initialization.
End of enumeration elements list.
MMDC Core Special Command Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_BA : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : 0
bank address 0
#1 : 1
bank address 1
#10 : 10
bank address 2
#111 : 111
bank address 7
End of enumeration elements list.
CMD_CS : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
to Chip-select 0
#1 : 1
to Chip-select 1
End of enumeration elements list.
CMD : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Precharge all, command is sent independently of bank status (set correct CMD_CS). Will be issued even if banks are closed. Mainly used for init sequence purpose.
#10 : 10
Auto-Refresh Command (set correct CMD_CS).
#11 : 11
Load Mode Register Command ( DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB), MRW Command (LPDDR2, set correct CMD_CS, MR_OP, MR_ADDR)
#100 : 100
ZQ calibration ( DDR3, set correct CMD_CS, {CMD_ADDR_MSB,CMD_ADDR_LSB} = 0x400 or 0x0 )
#101 : 101
Precharge all, only if banks open (set correct CMD_CS).
#110 : 110
MRR command (LPDDR2, set correct CMD_CS, MR_ADDR)
End of enumeration elements list.
WL_EN : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Exit write leveling mode or stay in normal mode.
#1 : 1
Write leveling entry command was sent.
End of enumeration elements list.
MRR_READ_DATA_VALID : no description available
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
Cleared upon the assertion of MRR command
#1 : 1
Set after MRR data is valid and stored at MDMRR register.
End of enumeration elements list.
CON_ACK : no description available
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
Configuration of MMDC registers is forbidden.
#1 : 1
Configuration of MMDC registers is permitted.
End of enumeration elements list.
CON_REQ : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request to configure MMDC.
#1 : 1
A request to configure MMDC is valid
End of enumeration elements list.
CMD_ADDR_LSB_MR_ADDR : no description available
bits : 16 - 23 (8 bit)
access : read-write
CMD_ADDR_MSB_MR_OP : no description available
bits : 24 - 31 (8 bit)
access : read-write
MMDC Core Refresh Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START_REF : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do nothing.
#1 : 1
Start a refresh cycle.
End of enumeration elements list.
REFR : no description available
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 refresh
#1 : 1
2 refreshes
#10 : 10
3 refreshes
#11 : 11
4 refreshes
#100 : 100
5 refreshes
#101 : 101
6 refreshes
#110 : 110
7 refreshes
#111 : 111
8 refreshes
End of enumeration elements list.
REF_SEL : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#0 : 0
Periodic refresh cycles will be triggered in frequency of 64KHz.
#1 : 1
Periodic refresh cycles will be triggered in frequency of 32KHz.
End of enumeration elements list.
REF_CNT : no description available
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#1 : 1
1 cycle.
#1111111111111110 : 1111111111111110
65534 cycles.
#1111111111111111 : 1111111111111111
65535 cycles.
End of enumeration elements list.
MMDC Core Read/Write Command Delay Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTR_DIFF : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycle
#10 : 10
2 cycles (Default)
#11 : 11
3 cycles
#100 : 100
4 cycles
#101 : 101
5 cycles
#110 : 110
6 cycles
#111 : 111
7 cycles
End of enumeration elements list.
RTW_DIFF : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycle
#10 : 10
2 cycles (Default)
#11 : 11
3 cycles
#100 : 100
4 cycles
#101 : 101
5 cycles
#110 : 110
6 cycles
#111 : 111
7 cycles
End of enumeration elements list.
WTW_DIFF : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycle
#10 : 10
2 cycles
#11 : 11
3 cycles (Default)
#100 : 100
4 cycles
#101 : 101
5 cycles
#110 : 110
6 cycles
#111 : 111
7 cycles
End of enumeration elements list.
WTR_DIFF : no description available
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycle
#10 : 10
2 cycles
#11 : 11
3 cycles (Default)
#100 : 100
4 cycles
#101 : 101
5 cycles
#110 : 110
6 cycles
#111 : 111
7 cycles
End of enumeration elements list.
RTW_SAME : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycle
#10 : 10
2 cycles (Default)
#11 : 11
3 cycles
#100 : 100
4 cycles
#101 : 101
5 cycles
#110 : 110
6 cycles
#111 : 111
7 cycles
End of enumeration elements list.
tDAI : no description available
bits : 16 - 28 (13 bit)
access : read-write
Enumeration:
#0 : 0
1 cycle
#111110011111 : 111110011111
4000 cycles (Default, JEDEC value for LPDDR2, gives 10us at 400MHz clock).
#1111111111111 : 1111111111111
8192 cycles
End of enumeration elements list.
MMDC Core Out of Reset Delays Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST_to_CKE : no description available
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#11 : 11
1 cycles
#10000 : 10000
14 cycles (JEDEC value for LPDDR2) - total of 200 us
#100011 : 100011
33 cycles (JEDEC value for DDR3) - total of 500 us
#111110 : 111110
60 cycles
#111111 : 111111
61 cycles
End of enumeration elements list.
SDE_to_RST : no description available
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#11 : 11
1 cycles
#100 : 100
2 cycles
#10000 : 10000
14 cycles (Jedec value for DDR3) - total of 200 us
#111110 : 111110
60 cycles
#111111 : 111111
61 cycles
End of enumeration elements list.
tXPR : no description available
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#1 : 1
2 cycles
#10 : 10
3 cycles
#11111110 : 11111110
255 cycles
#11111111 : 11111111
256 cycles
End of enumeration elements list.
MMDC Core MRR Data Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MRR_READ_DATA0 : no description available
bits : 0 - 7 (8 bit)
access : read-only
MRR_READ_DATA1 : no description available
bits : 8 - 15 (8 bit)
access : read-only
MMDC Core Timing Configuration Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tRPab_LP : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
End of enumeration elements list.
tRPpb_LP : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
End of enumeration elements list.
tRCD_LP : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
End of enumeration elements list.
RC_LP : no description available
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#111110 : 111110
63 clocks
End of enumeration elements list.
MMDC Core MR4 Derating Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDATE_DE_REQ : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do nothing.
#1 : 1
Request to update the following values: tRRD, tRCD, tRP, tRC, tRAS and refresh related fields(MDREF register): REF_CNT, REF_SEL, REFR
End of enumeration elements list.
UPDATE_DE_ACK : no description available
bits : 1 - 1 (1 bit)
access : read-only
tRCD_DE : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original tRCD is used.
#1 : 1
tRCD is derated in 1 cycle.
End of enumeration elements list.
tRC_DE : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original tRC is used.
#1 : 1
tRC is derated in 1 cycle.
End of enumeration elements list.
tRAS_DE : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original tRAS is used.
#1 : 1
tRAS is derated in 1 cycle.
End of enumeration elements list.
tRP_DE : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original tRP is used.
#1 : 1
tRP is derated in 1 cycle.
End of enumeration elements list.
tRRD_DE : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Original tRRD is used.
#1 : 1
tRRD is derated in 1 cycle.
End of enumeration elements list.
MMDC Core Power Down Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tCKSRE : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycles
#110 : 110
6cycles
#111 : 111
7cycles
End of enumeration elements list.
tCKSRX : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle
#1 : 1
1 cycles
#110 : 110
6 cycles
#111 : 111
7 cycles
End of enumeration elements list.
BOTH_CS_PD : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Each chip select can enter power down independently according to its configuration.
#1 : 1
Chip selects can enter power down only if the amount of idle cycles of both chip selects was obtained.
End of enumeration elements list.
SLOW_PD : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast mode.
#1 : 1
Slow mode.
End of enumeration elements list.
PWDT_0 : no description available
bits : 8 - 11 (4 bit)
access : read-write
PWDT_1 : no description available
bits : 12 - 15 (4 bit)
access : read-write
tCKE : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 cycle
#1 : 1
2 cycles
#110 : 110
7 cycles
#111 : 111
8 cycles
End of enumeration elements list.
PRCT_0 : no description available
bits : 24 - 26 (3 bit)
access : read-write
PRCT_1 : no description available
bits : 28 - 30 (3 bit)
access : read-write
MMDC Core Address Space Partition Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS0_END : no description available
bits : 0 - 6 (7 bit)
access : read-write
MMDC Core AXI Reordering Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCR_GUARD : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
15 (default)
#0001 : 0001
16
#1111 : 1111
30
End of enumeration elements list.
ARCR_DYN_MAX : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0
#0001 : 0001
1
#1111 : 1111
15 (default)
End of enumeration elements list.
ARCR_DYN_JMP : no description available
bits : 8 - 11 (4 bit)
access : read-write
ARCR_ACC_HIT : no description available
bits : 16 - 18 (3 bit)
access : read-write
ARCR_PAG_HIT : no description available
bits : 20 - 22 (3 bit)
access : read-write
ARCR_RCH_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal prioritization, no bypassing
#1 : 1
accesses with QoS=='F' bypass the arbitration
End of enumeration elements list.
ARCR_EXC_ERR_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
violation of AXI exclusive rules (6.2.4) result in OKAY response (rresp/bresp=2'b00)
#1 : 1
violation of AXI exclusive rules (6.2.4) result in SLAVE Error response (rresp/bresp=2'b10)
End of enumeration elements list.
ARCR_SEC_ERR_EN : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
security violation results in OKAY response (rresp/bresp=2'b00)
#1 : 1
security violation results in SLAVE Error response (rresp/bresp=2'b10)
End of enumeration elements list.
ARCR_SEC_ERR_LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ARCR_SEC_ERR_EN is unlocked, so can be updated any moment
#1 : 1
ARCR_SEC_ERR_EN is locked, so it can't be updated
End of enumeration elements list.
MMDC Core Power Saving Control and Status Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSD : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
power saving enabled
#1 : 1
power saving disabled (default)
End of enumeration elements list.
PSS : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
not in power saving
#1 : 1
power saving
End of enumeration elements list.
RIS : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
idle
#1 : 1
not idle
End of enumeration elements list.
WIS : no description available
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
idle
#1 : 1
not idle
End of enumeration elements list.
PST : no description available
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#00000000 : 00000000
Reserved - this value is forbidden.
#00000001 : 00000001
timer is configured to 64 clock cycles.
#00000010 : 00000010
timer is configured to 128 clock cycles.
#00010000 : 00010000
(Default)- 1024 clock cycles.
#11111111 : 11111111
timer clock is configured to 16320 clock cycles.
End of enumeration elements list.
LPMD : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
no lpmd request
#1 : 1
lpmd request
End of enumeration elements list.
DVFS : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
no dvfs request
#1 : 1
dvfs request
End of enumeration elements list.
LPACK : no description available
bits : 24 - 24 (1 bit)
access : read-only
DVACK : no description available
bits : 25 - 25 (1 bit)
access : read-only
MMDC Core Exclusive ID Monitor Register0
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXC_ID_MONITOR0 : no description available
bits : 0 - 15 (16 bit)
access : read-write
EXC_ID_MONITOR1 : no description available
bits : 16 - 31 (16 bit)
access : read-write
MMDC Core Exclusive ID Monitor Register1
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXC_ID_MONITOR2 : no description available
bits : 0 - 15 (16 bit)
access : read-write
EXC_ID_MONITOR3 : no description available
bits : 16 - 31 (16 bit)
access : read-write
MMDC Core Debug and Profiling Control Register 0
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
DBG_RST : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
no reset
#1 : 1
reset
End of enumeration elements list.
PRF_FRZ : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
profiling counters are not frozen
#1 : 1
profiling counters are frozen
End of enumeration elements list.
CYC_OVF : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
no overflow
#1 : 1
overflow
End of enumeration elements list.
SBS_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
SBS : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#1 : 1
Launch AXI pending access toward the DDR
#0 : 0
No access will be launched toward the DDR
End of enumeration elements list.
MMDC Core Debug and Profiling Control Register 1
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRF_AXI_ID : no description available
bits : 0 - 15 (16 bit)
access : read-write
PRF_AXI_IDMASK : no description available
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#1 : 1
AXI ID specific bit is chosen for profiling
#0 : 0
AXI ID specific bit is ignored (don't care)
End of enumeration elements list.
MMDC Core Debug and Profiling Status Register 0
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CYC_COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 1
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY_COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 2
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_ACC_COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 3
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_ACC_COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 4
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_BYTES_COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Debug and Profiling Status Register 5
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_BYTES_COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Step By Step Address Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SBS_ADDR : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC Core Step By Step Address Attributes Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SBS_VLD : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
not valid
#1 : 1
valid
End of enumeration elements list.
SBS_TYPE : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
write
#1 : 1
read
End of enumeration elements list.
SBS_LOCK : no description available
bits : 2 - 3 (2 bit)
access : read-only
SBS_PROT : no description available
bits : 4 - 6 (3 bit)
access : read-only
SBS_SIZE : no description available
bits : 7 - 9 (3 bit)
access : read-only
Enumeration:
#000 : 000
8 bits
#001 : 001
16 bits
#010 : 010
32 bits
#011 : 011
64 bits
#100 : 100
128bits
End of enumeration elements list.
SBS_BURST : no description available
bits : 10 - 11 (2 bit)
access : read-only
Enumeration:
#00 : 00
FIXED
#01 : 01
INCR burst
#10 : 10
WRAP burst
End of enumeration elements list.
SBS_BUFF : no description available
bits : 12 - 12 (1 bit)
access : read-only
SBS_LEN : no description available
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#000 : 000
burst of length 1
#001 : 001
burst of length 2
#111 : 111
burst of length 8
End of enumeration elements list.
SBS_AXI_ID : no description available
bits : 16 - 31 (16 bit)
access : read-only
MMDC Core General Purpose Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP31_GP0 : no description available
bits : 0 - 31 (32 bit)
access : read-write
MMDC Core ODT Timing Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tODT_idle_off : no description available
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
#0 : 0
0 cycle (turned off at the earliest possible time)
#1 : 1
1 cycle
#10 : 10
2 cycles
#11110 : 11110
30 cycles
#11111 : 11111
31 cycles
End of enumeration elements list.
tODTLon : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0 : 0
- 0x1 Reserved
#10 : 10
2 cycles
#11 : 11
3 cycles
#100 : 100
4 cycles
#101 : 101
5 cycles
#110 : 110
6 cycles
End of enumeration elements list.
tAXPD : no description available
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
#1111 : 1111
16 clocks
End of enumeration elements list.
tANPD : no description available
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
#1111 : 1111
16 clocks
End of enumeration elements list.
tAONPD : no description available
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 cycle
#1 : 1
2 cycles
#110 : 110
7 cycles
#111 : 111
8 cycles
End of enumeration elements list.
tAOFPD : no description available
bits : 27 - 29 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 cycle
#1 : 1
2 cycles
#110 : 110
7 cycles
#111 : 111
8 cycles
End of enumeration elements list.
MMDC PHY ZQ HW control register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_MODE : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#0 : 0
No ZQ calibration is issued. (Default)
#1 : 1
ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ long command to the external DDR device only when exiting self refresh.
#10 : 10
ZQ calibration command long/short is issued only to the external DDR device periodically and when exiting self refresh
#11 : 11
ZQ calibration is issued to i.MX ZQ calibration pad together with ZQ calibration command long/short to the external DDR device periodically and when exiting self refresh
End of enumeration elements list.
ZQ_HW_PER : no description available
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
ZQ calibration is performed every 1 ms.
#0001 : 0001
ZQ calibration is performed every 2 ms.
#0010 : 0010
ZQ calibration is performed every 4 ms.
#1010 : 1010
ZQ calibration is performed every 1 sec.
#1110 : 1110
ZQ calibration is performed every 16 sec.
#1111 : 1111
ZQ calibration is performed every 32 sec.
End of enumeration elements list.
ZQ_HW_PU_RES : no description available
bits : 6 - 10 (5 bit)
access : read-only
Enumeration:
#00000 : 00000
Min. resistance.
#11111 : 11111
Max. resistance.
End of enumeration elements list.
ZQ_HW_PD_RES : no description available
bits : 11 - 15 (5 bit)
access : read-only
Enumeration:
#00000 : 00000
Max. resistance.
#11111 : 11111
Min. resistance.
End of enumeration elements list.
ZQ_HW_FOR : no description available
bits : 16 - 16 (1 bit)
access : read-write
TZQ_INIT : no description available
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
#010 : 010
128 cycles
#011 : 011
256 cycles
#100 : 100
512 cycles - Default (JEDEC value for DDR3)
#101 : 101
1024 cycles
End of enumeration elements list.
TZQ_OPER : no description available
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#010 : 010
128 cycles
#011 : 011
256 cycles - Default (JEDEC value for DDR3)
#100 : 100
512 cycles
#101 : 101
1024 cycles
End of enumeration elements list.
TZQ_CS : no description available
bits : 23 - 25 (3 bit)
access : read-write
Enumeration:
#010 : 010
128 cycles (Default)
#011 : 011
256 cycles
#100 : 100
512 cycles
#101 : 101
1024 cycles
End of enumeration elements list.
ZQ_EARLY_COMPARATOR_EN_TIMER : no description available
bits : 27 - 31 (5 bit)
access : read-write
Enumeration:
#0 : 0
- 0x6 Reserved
#111 : 111
8 cycles
#10100 : 10100
21 cycles (Default)
#11110 : 11110
31 cycles
#11111 : 11111
32 cycles
End of enumeration elements list.
MMDC PHY ZQ SW control register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_SW_FOR : no description available
bits : 0 - 0 (1 bit)
access : read-write
ZQ_SW_RES : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current ZQ calibration voltage is less than VDD/2.
#1 : 1
Current ZQ calibration voltage is more than VDD/2
End of enumeration elements list.
ZQ_SW_PU_VAL : no description available
bits : 2 - 6 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Min. resistance.
#11111 : 11111
Max. resistance.
End of enumeration elements list.
ZQ_SW_PD_VAL : no description available
bits : 7 - 11 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Max. resistance.
#11111 : 11111
Min. resistance.
End of enumeration elements list.
ZQ_SW_PD : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PU resistor calibration
#1 : 1
PD resistor calibration
End of enumeration elements list.
USE_ZQ_SW_VAL : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fields ZQ_HW_PD_VAL & ZQ_HW_PU_VAL will be driven to I/O pads resistor controls.
#1 : 1
Fields ZQ_SW_PD_VAL & ZQ_SW_PU_VAL will be driven to I/O pads resistor controls.
End of enumeration elements list.
ZQ_CMP_OUT_SMP : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
7 cycles
#01 : 01
15 cycles
#10 : 10
23 cycles
#11 : 11
31 cycles
End of enumeration elements list.
MMDC PHY Write Leveling Configuration and Error Status Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_WL_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
SW_WL_EN : no description available
bits : 1 - 1 (1 bit)
access : read-write
SW_WL_CNT_EN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
MMDC doesn't count 25+15 cycles before issuing write-leveling DQS.
#1 : 1
MMDC counts 25+15 cycles before issuing write-leveling DQS.
End of enumeration elements list.
WL_SW_RES0 : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
DQS0 sampled low CK during SW write-leveling.
#1 : 1
DQS0 sampled high CK during SW write-leveling.
End of enumeration elements list.
WL_SW_RES1 : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
DQS1 sampled low CK during SW write-leveling.
#1 : 1
DQS1 sampled high CK during SW write-leveling.
End of enumeration elements list.
WL_HW_ERR0 : no description available
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found on byte0 during write-leveling HW calibration.
#1 : 1
An error was found on byte0 during write-leveling HW calibration.
End of enumeration elements list.
WL_HW_ERR1 : no description available
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found on byte1 during write-leveling HW calibration.
#1 : 1
An error was found on byte1 during write-leveling HW calibration.
End of enumeration elements list.
MMDC PHY Write Leveling Delay Control Register 0
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WL_DL_ABS_OFFSET0 : no description available
bits : 0 - 6 (7 bit)
access : read-write
WL_HC_DEL0 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No delay is added.
#1 : 1
Half cycle delay is added.
End of enumeration elements list.
WL_CYC_DEL0 : no description available
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#0 : 0
No delay is added.
#1 : 1
1 cycle delay is added.
End of enumeration elements list.
WL_DL_ABS_OFFSET1 : no description available
bits : 16 - 22 (7 bit)
access : read-write
WL_HC_DEL1 : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No delay is added.
#1 : 1
Half cycle delay is added.
End of enumeration elements list.
WL_CYC_DEL1 : no description available
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
#0 : 0
No delay is added.
#1 : 1
1 cycle delay is added.
End of enumeration elements list.
MMDC PHY Write Leveling delay-line Status Register
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WL_DL_UNIT_NUM0 : no description available
bits : 0 - 6 (7 bit)
access : read-only
WL_DL_UNIT_NUM1 : no description available
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY ODT control register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ODT_WR_PAS_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inactive CS ODT pin is disabled during write accesses to other CS.
#1 : 1
Inactive CS ODT pin is enabled during write accesses to other CS.
End of enumeration elements list.
ODT_WR_ACT_EN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active CS ODT pin is disabled during write access.
#1 : 1
Active CS ODT pin is enabled during write access.
End of enumeration elements list.
ODT_RD_PAS_EN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inactive CS ODT pin is disabled during read accesses to other CS.
#1 : 1
Inactive CS ODT pin is enabled during read accesses to other CS.
End of enumeration elements list.
ODT_RD_ACT_EN : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active CS ODT pin is disabled during read access.
#1 : 1
Active CS ODT pin is enabled during read access.
End of enumeration elements list.
ODT0_INT_RES : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
Rtt_Nom Disabled.
#001 : 001
Rtt_Nom 120 Ohm
#010 : 010
Rtt_Nom 60 Ohm
#011 : 011
Rtt_Nom 40 Ohm
#100 : 100
Rtt_Nom 30 Ohm
#101 : 101
Rtt_Nom 24 Ohm
#110 : 110
Rtt_Nom 20 Ohm
#111 : 111
Rtt_Nom 17 Ohm
End of enumeration elements list.
ODT1_INT_RES : no description available
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#0000 : 0000
Rtt_Nom Disabled.
#001 : 001
Rtt_Nom 120 Ohm
#010 : 010
Rtt_Nom 60 Ohm
#011 : 011
Rtt_Nom 40 Ohm
#100 : 100
Rtt_Nom 30 Ohm
#101 : 101
Rtt_Nom 24 Ohm
#110 : 110
Rtt_Nom 20 Ohm
#111 : 111
Rtt_Nom 17 Ohm
End of enumeration elements list.
MMDC PHY Read DQ Byte0 Delay Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_dq0_del : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq0 delay
#001 : 001
Add dq0 delay of 1 delay unit
#010 : 010
Add dq0 delay of 2 delay units.
#011 : 011
Add dq0 delay of 3 delay units.
#100 : 100
Add dq0 delay of 4 delay units.
#101 : 101
Add dq0 delay of 5 delay units.
#110 : 110
Add dq0 delay of 6 delay units.
#111 : 111
Add dq0 delay of 7 delay units.
End of enumeration elements list.
rd_dq1_del : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq1 delay
#001 : 001
Add dq1 delay of 1 delay unit
#010 : 010
Add dq1 delay of 2 delay units.
#011 : 011
Add dq1 delay of 3 delay units.
#100 : 100
Add dq1 delay of 4 delay units.
#101 : 101
Add dq1 delay of 5 delay units.
#110 : 110
Add dq1 delay of 6 delay units.
#111 : 111
Add dq1 delay of 7 delay units.
End of enumeration elements list.
rd_dq2_del : no description available
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq2 delay
#001 : 001
Add dq2 delay of 1 delay unit
#010 : 010
Add dq2 delay of 2 delay units.
#011 : 011
Add dq2 delay of 3 delay units.
#100 : 100
Add dq2 delay of 4 delay units.
#101 : 101
Add dq2 delay of 5 delay units.
#110 : 110
Add dq2 delay of 6 delay units.
#111 : 111
Add dq2 delay of 7 delay units.
End of enumeration elements list.
rd_dq3_del : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq3 delay
#001 : 001
Add dq3 delay of 1 delay unit
#010 : 010
Add dq3 delay of 2 delay units.
#011 : 011
Add dq3 delay of 3 delay units.
#100 : 100
Add dq3 delay of 4 delay units.
#101 : 101
Add dq3 delay of 5 delay units.
#110 : 110
Add dq3 delay of 6 delay units.
#111 : 111
Add dq3 delay of 7 delay units.
End of enumeration elements list.
rd_dq4_del : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq4 delay
#001 : 001
Add dq4 delay of 1 delay unit
#010 : 010
Add dq4 delay of 2 delay units.
#011 : 011
Add dq4 delay of 3 delay units.
#100 : 100
Add dq4 delay of 4 delay units.
#101 : 101
Add dq4 delay of 5 delay units.
#110 : 110
Add dq4 delay of 6 delay units.
#111 : 111
Add dq4 delay of 7 delay units.
End of enumeration elements list.
rd_dq5_del : no description available
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq5 delay
#001 : 001
Add dq5 delay of 1 delay unit
#010 : 010
Add dq5 delay of 2 delay units.
#011 : 011
Add dq5 delay of 3 delay units.
#100 : 100
Add dq5 delay of 4 delay units.
#101 : 101
Add dq5 delay of 5 delay units.
#110 : 110
Add dq5 delay of 6 delay units.
#111 : 111
Add dq5 delay of 7 delay units.
End of enumeration elements list.
rd_dq6_del : no description available
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq6 delay
#001 : 001
Add dq6 delay of 1 delay unit
#010 : 010
Add dq6 delay of 2 delay units.
#011 : 011
Add dq6 delay of 3 delay units.
#100 : 100
Add dq6 delay of 4 delay units.
#101 : 101
Add dq6 delay of 5 delay units.
#110 : 110
Add dq6 delay of 6 delay units.
#111 : 111
Add dq6 delay of 7 delay units.
End of enumeration elements list.
rd_dq7_del : no description available
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq7 delay
#001 : 001
Add dq7 delay of 1 delay unit
#010 : 010
Add dq7 delay of 2 delay units.
#011 : 011
Add dq7 delay of 3 delay units.
#100 : 100
Add dq7 delay of 4 delay units.
#101 : 101
Add dq7 delay of 5 delay units.
#110 : 110
Add dq7 delay of 6 delay units.
#111 : 111
Add dq7 delay of 7 delay units.
End of enumeration elements list.
MMDC PHY Read DQ Byte1 Delay Register
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rd_dq8_del : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq8 delay
#001 : 001
Add dq8 delay of 1 delay unit
#010 : 010
Add dq8 delay of 2 delay units.
#011 : 011
Add dq8 delay of 3 delay units.
#100 : 100
Add dq8 delay of 4 delay units.
#101 : 101
Add dq8 delay of 5 delay units.
#110 : 110
Add dq8 delay of 6 delay units.
#111 : 111
Add dq8 delay of 7 delay units.
End of enumeration elements list.
rd_dq9_del : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq9 delay
#001 : 001
Add dq9 delay of 1 delay unit
#010 : 010
Add dq9 delay of 2 delay units.
#011 : 011
Add dq9 delay of 3 delay units.
#100 : 100
Add dq9 delay of 4 delay units.
#101 : 101
Add dq9 delay of 5 delay units.
#110 : 110
Add dq9 delay of 6 delay units.
#111 : 111
Add dq9 delay of 7 delay units.
End of enumeration elements list.
rd_dq10_del : no description available
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq10 delay
#001 : 001
Add dq10 delay of 1 delay unit
#010 : 010
Add dq10 delay of 2 delay units.
#011 : 011
Add dq10 delay of 3 delay units.
#100 : 100
Add dq10 delay of 4 delay units.
#101 : 101
Add dq10 delay of 5 delay unit
#110 : 110
Add dq10 delay of 6 delay units.
#111 : 111
Add dq10 delay of 7 delay units.
End of enumeration elements list.
rd_dq11_del : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq11 delay
#001 : 001
Add dq11 delay of 1 delay unit
#010 : 010
Add dq11 delay of 2 delay units.
#011 : 011
Add dq11 delay of 3 delay units.
#100 : 100
Add dq11 delay of 4 delay units.
#101 : 101
Add dq11 delay of 5 delay units.
#110 : 110
Add dq11 delay of 6 delay units.
#111 : 111
Add dq11 delay of 7 delay units.
End of enumeration elements list.
rd_dq12_del : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq12 delay
#001 : 001
Add dq12 delay of 1 delay unit
#010 : 010
Add dq12 delay of 2 delay units.
#011 : 011
Add dq12 delay of 3 delay units.
#100 : 100
Add dq12 delay of 4 delay units.
#101 : 101
Add dq12 delay of 5 delay units.
#110 : 110
Add dq12 delay of 6 delay units.
#111 : 111
Add dq12 delay of 7 delay units.
End of enumeration elements list.
rd_dq13_del : no description available
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq13 delay
#001 : 001
Add dq13 delay of 1 delay unit
#010 : 010
Add dq13 delay of 2 delay units.
#011 : 011
Add dq13 delay of 3 delay units.
#100 : 100
Add dq13 delay of 4 delay units.
#101 : 101
Add dq13 delay of 5 delay units.
#110 : 110
Add dq13 delay of 6 delay units.
#111 : 111
Add dq13 delay of 7 delay units.
End of enumeration elements list.
rd_dq14_del : no description available
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq14 delay
#001 : 001
Add dq14 delay of 1 delay unit
#010 : 010
Add dq14 delay of 2 delay units.
#011 : 011
Add dq14 delay of 3 delay units.
#100 : 100
Add dq14 delay of 4 delay units.
#101 : 101
Add dq14 delay of 5 delay units.
#110 : 110
Add dq14 delay of 6 delay units.
#111 : 111
Add dq14 delay of 7 delay units.
End of enumeration elements list.
rd_dq15_del : no description available
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 000
No change in dq15 delay
#001 : 001
Add dq15 delay of 1 delay unit
#010 : 010
Add dq15 delay of 2 delay units.
#011 : 011
Add dq15 delay of 3 delay units.
#100 : 100
Add dq15 delay of 4 delay units.
#101 : 101
Add dq15 delay of 5 delay units.
#110 : 110
Add dq15 delay of 6 delay units.
#111 : 111
Add dq15 delay of 7 delay units.
End of enumeration elements list.
MMDC PHY Write DQ Byte0 Delay Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_dq0_del : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq0 delay
#01 : 01
Add dq0 delay of 1 delay unit.
#10 : 10
Add dq0 delay of 2 delay units.
#11 : 11
Add dq0 delay of 3 delay units.
End of enumeration elements list.
wr_dq1_del : no description available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq1 delay
#01 : 01
Add dq1 delay of 1 delay unit.
#10 : 10
Add dq1 delay of 2 delay units.
#11 : 11
Add dq1 delay of 3 delay units.
End of enumeration elements list.
wr_dq2_del : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq2 delay
#01 : 01
Add dq2 delay of 1 delay unit.
#10 : 10
Add dq2 delay of 2 delay units.
#11 : 11
Add dq2 delay of 3 delay units.
End of enumeration elements list.
wr_dq3_del : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq3 delay
#01 : 01
Add dq3 delay of 1 delay unit.
#10 : 10
Add dq3 delay of 2 delay units.
#11 : 11
Add dq3 delay of 3 delay units.
End of enumeration elements list.
wr_dq4_del : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq4 delay
#01 : 01
Add dq4 delay of 1 delay unit..
#10 : 10
Add dq4 delay of 2 delay units.
#11 : 11
Add dq4 delay of 3 delay units.
End of enumeration elements list.
wr_dq5_del : no description available
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq5 delay
#01 : 01
Add dq5 delay of 1 delay unit.
#10 : 10
Add dq5 delay of 2 delay units.
#11 : 11
Add dq5 delay of 3 delay units.
End of enumeration elements list.
wr_dq6_del : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq6 delay
#01 : 01
Add dq6 delay of 1 delay unit.
#10 : 10
Add dq6 delay of 2 delay units.
#11 : 11
Add dq6 delay of 3 delay units.
End of enumeration elements list.
wr_dq7_del : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq7 delay
#01 : 01
Add dq7 delay of 1 delay unit.
#10 : 10
Add dq7 delay of 2 delay units.
#11 : 11
Add dq7 delay of 3 delay units.
End of enumeration elements list.
wr_dm0_del : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dm0 delay
#01 : 01
Add dm0 delay of 1 delay unit.
#10 : 10
Add dm0 delay of 2 delay units.
#11 : 11
Add dm0 delay of 3 delay units.
End of enumeration elements list.
MMDC PHY Write DQ Byte1 Delay Register
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wr_dq8_del : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq8 delay
#01 : 01
Add dq8 delay of 1 delay unit.
#10 : 10
Add dq8 delay of 2 delay units.
#11 : 11
Add dq8 delay of 3 delay units.
End of enumeration elements list.
wr_dq9_del : no description available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq9 delay
#01 : 01
Add dq9 delay of 1 delay unit.
#10 : 10
Add dq9 delay of 2 delay units.
#11 : 11
Add dq9 delay of 3 delay units.
End of enumeration elements list.
wr_dq10_del : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq10 delay
#01 : 01
Add dq10 delay of 1 delay unit.
#10 : 10
Add dq10 delay of 2 delay units.
#11 : 11
Add dq10 delay of 3 delay units.
End of enumeration elements list.
wr_dq11_del : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq11 delay
#01 : 01
Add dq11 delay of 1 delay unit.
#10 : 10
Add dq11 delay of 2 delay units.
#11 : 11
Add dq11 delay of 3 delay units.
End of enumeration elements list.
wr_dq12_del : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq12 delay
#01 : 01
Add dq12 delay of 1 delay unit.
#10 : 10
Add dq12 delay of 2 delay units.
#11 : 11
Add dq12 delay of 3 delay units.
End of enumeration elements list.
wr_dq13_del : no description available
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq13 delay
#01 : 01
Add dq13 delay of 1 delay unit.
#10 : 10
Add dq13 delay of 2 delay units.
#11 : 11
Add dq13 delay of 3 delay units.
End of enumeration elements list.
wr_dq14_del : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq14 delay
#01 : 01
Add dq14 delay of 1 delay unit.
#10 : 10
Add dq14 delay of 2 delay units.
#11 : 11
Add dq14 delay of 3 delay units.
End of enumeration elements list.
wr_dq15_del : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dq15 delay
#01 : 01
Add dq15 delay of 1 delay unit.
#10 : 10
Add dq15 delay of 2 delay units.
#11 : 11
Add dq15 delay of 3 delay units.
End of enumeration elements list.
wr_dm1_del : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in dm1 delay
#01 : 01
Add dm1 delay of 1 delay unit.
#10 : 10
Add dm1 delay of 2 delay units.
#11 : 11
Add dm1 delay of 3 delay units.
End of enumeration elements list.
MMDC PHY Read DQS Gating Control Register 0
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DG_DL_ABS_OFFSET0 : no description available
bits : 0 - 6 (7 bit)
access : read-write
DG_HC_DEL0 : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 cycles delay.
#0001 : 0001
Half cycle delay.
#0010 : 0010
1 cycle delay
#1101 : 1101
6.5 cycles delay
End of enumeration elements list.
HW_DG_ERR : no description available
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found during the DQS gating HW calibration process.
#1 : 1
An error was found during the DQS gating HW calibration process.
End of enumeration elements list.
DG_DL_ABS_OFFSET1 : no description available
bits : 16 - 22 (7 bit)
access : read-write
DG_EXT_UP : no description available
bits : 23 - 23 (1 bit)
access : read-write
DG_HC_DEL1 : no description available
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 cycles delay.
#0001 : 0001
Half cycle delay.
#0010 : 0010
1 cycle delay
#1101 : 1101
6.5 cycles delay
End of enumeration elements list.
HW_DG_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable automatic read DQS gating calibration
#1 : 1
Start automatic read DQS gating calibration
End of enumeration elements list.
DG_DIS : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read DQS gating mechanism is enabled
#1 : 1
Read DQS gating mechanism is disabled
End of enumeration elements list.
DG_CMP_CYC : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
MMDC waits 16 DDR cycles
#1 : 1
MMDC waits 32 DDR cycles
End of enumeration elements list.
RST_RD_FIFO : no description available
bits : 31 - 31 (1 bit)
access : read-write
MMDC PHY Read DQS Gating delay-line Status Register
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DG_DL_UNIT_NUM0 : no description available
bits : 0 - 6 (7 bit)
access : read-only
DG_DL_UNIT_NUM1 : no description available
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY Read delay-lines Configuration Register
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_DL_ABS_OFFSET0 : no description available
bits : 0 - 6 (7 bit)
access : read-write
RD_DL_ABS_OFFSET1 : no description available
bits : 8 - 14 (7 bit)
access : read-write
MMDC PHY Read delay-lines Status Register
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD_DL_UNIT_NUM0 : no description available
bits : 0 - 6 (7 bit)
access : read-only
RD_DL_UNIT_NUM1 : no description available
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY Write delay-lines Configuration Register
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_DL_ABS_OFFSET0 : no description available
bits : 0 - 6 (7 bit)
access : read-write
WR_DL_ABS_OFFSET1 : no description available
bits : 8 - 14 (7 bit)
access : read-write
MMDC PHY Write delay-lines Status Register
address_offset : 0x854 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WR_DL_UNIT_NUM0 : no description available
bits : 0 - 6 (7 bit)
access : read-only
WR_DL_UNIT_NUM1 : no description available
bits : 8 - 14 (7 bit)
access : read-only
MMDC PHY CK Control Register
address_offset : 0x858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDclk0_del : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in DDR clock0 delay
#01 : 01
Add DDR clock0 delay of 1 delay unit.
#10 : 10
Add DDR clock0 delay of 2 delay units.
#11 : 11
Add DDR clock0 delay of 3 delay units.
End of enumeration elements list.
SDCLK1_del : no description available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in DDR clock delay
#01 : 01
Add DDR clock delay of 1 delay unit.
#10 : 10
Add DDR clock delay of 2 delay units.
#11 : 11
Add DDR clock delay of 3 delay units.
End of enumeration elements list.
MMDC ZQ LPDDR2 HW Control Register
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZQ_LP2_HW_ZQINIT : no description available
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
#110111 : 110111
112 cycles
#111000 : 111000
114 cycles
#100001001 : 100001001
532 cycles (Default, JEDEC value, tZQINIT, for LPDDR2, 1us @ clock frequency 533MHz)
#111111110 : 111111110
1022 cycles
#111111111 : 111111111
1024 cycles
End of enumeration elements list.
ZQ_LP2_HW_ZQCL : no description available
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#110111 : 110111
112 cycles
#111000 : 111000
114 cycles
#1011111 : 1011111
192 cycles (Default, JEDEC value, tZQCL, for LPDDR2, 360ns @ clock frequency 533MHz)
#11111110 : 11111110
510 cycles
#11111111 : 11111111
512 cycles
End of enumeration elements list.
ZQ_LP2_HW_ZQCS : no description available
bits : 24 - 30 (7 bit)
access : read-write
Enumeration:
#11011 : 11011
112 cycles (default)
#11100 : 11100
116 cycles
#1111110 : 1111110
508 cycles
#1111111 : 1111111
512 cycles
End of enumeration elements list.
MMDC PHY Read Delay HW Calibration Control Register
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_RD_DL_ERR0 : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0.
#1 : 1
An error was found in read delay-line 0 during the automatic (HW) read calibration process of read delay-line 0.
End of enumeration elements list.
HW_RD_DL_ERR1 : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1.
#1 : 1
An error was found in read delay-line 1 during the automatic (HW) read calibration process of read delay-line 1.
End of enumeration elements list.
HW_RD_DL_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
HW_RD_DL_CMP_CYC : no description available
bits : 5 - 5 (1 bit)
access : read-write
MMDC PHY Write Delay HW Calibration Control Register
address_offset : 0x864 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HW_WR_DL_ERR0 : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found during the automatic (HW) write calibration process of write delay-line 0.
#1 : 1
An error was found during the automatic (HW) write calibration process of write delay-line 0.
End of enumeration elements list.
HW_WR_DL_ERR1 : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error was found during the automatic (HW) write calibration process of write delay-line 1.
#1 : 1
An error was found during the automatic (HW) write calibration process of write delay-line 1.
End of enumeration elements list.
HW_WR_DL_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
HW_WR_DL_CMP_CYC : no description available
bits : 5 - 5 (1 bit)
access : read-write
MMDC PHY Read Delay HW Calibration Status Register 0
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_RD_DL_LOW0 : no description available
bits : 0 - 6 (7 bit)
access : read-only
HW_RD_DL_UP0 : no description available
bits : 8 - 14 (7 bit)
access : read-only
HW_RD_DL_LOW1 : no description available
bits : 16 - 22 (7 bit)
access : read-only
HW_RD_DL_UP1 : no description available
bits : 24 - 30 (7 bit)
access : read-only
MMDC PHY Write Delay HW Calibration Status Register 0
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_WR_DL_LOW0 : no description available
bits : 0 - 6 (7 bit)
access : read-only
HW_WR_DL_UP0 : no description available
bits : 8 - 14 (7 bit)
access : read-only
HW_WR_DL_LOW1 : no description available
bits : 16 - 22 (7 bit)
access : read-only
HW_WR_DL_UP1 : no description available
bits : 24 - 30 (7 bit)
access : read-only
MMDC PHY Write Leveling HW Error Register
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_WL0_DQ : no description available
bits : 0 - 7 (8 bit)
access : read-only
HW_WL1_DQ : no description available
bits : 8 - 15 (8 bit)
access : read-only
MMDC PHY Read DQS Gating HW Status Register 0
address_offset : 0x87C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_DG_LOW0 : no description available
bits : 0 - 10 (11 bit)
access : read-only
HW_DG_UP0 : no description available
bits : 16 - 26 (11 bit)
access : read-only
MMDC PHY Read DQS Gating HW Status Register 1
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HW_DG_LOW1 : no description available
bits : 0 - 10 (11 bit)
access : read-only
HW_DG_UP1 : no description available
bits : 16 - 26 (11 bit)
access : read-only
MMDC PHY Pre-defined Compare Register 1
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDV1 : no description available
bits : 0 - 15 (16 bit)
access : read-write
PDV2 : no description available
bits : 16 - 31 (16 bit)
access : read-write
MMDC PHY Pre-defined Compare and CA delay-line Configuration Register
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPR_CMP : no description available
bits : 0 - 0 (1 bit)
access : read-write
MPR_FULL_CMP : no description available
bits : 1 - 1 (1 bit)
access : read-write
READ_LEVEL_PATTERN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare with read pattern 1010
#1 : 1
Compare with read pattern 0011 (Used only in LPDDR2 mode)
End of enumeration elements list.
CA_DL_ABS_OFFSET : no description available
bits : 16 - 22 (7 bit)
access : read-write
PHY_CA_DL_UNIT : no description available
bits : 24 - 30 (7 bit)
access : read-only
MMDC PHY SW Dummy Access Register
address_offset : 0x894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW_DUMMY_WR : no description available
bits : 0 - 0 (1 bit)
access : read-write
SW_DUMMY_RD : no description available
bits : 1 - 1 (1 bit)
access : read-write
SW_DUM_CMP0 : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Dummy read fail
#1 : 1
Dummy read pass
End of enumeration elements list.
SW_DUM_CMP1 : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Dummy read fail
#1 : 1
Dummy read pass
End of enumeration elements list.
MMDC PHY SW Dummy Read Data Register 0
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD0 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 1
address_offset : 0x89C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD1 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 2
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD2 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 3
address_offset : 0x8A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD3 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 4
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD4 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 5
address_offset : 0x8AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD5 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 6
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD6 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY SW Dummy Read Data Register 7
address_offset : 0x8B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DUM_RD7 : no description available
bits : 0 - 31 (32 bit)
access : read-only
MMDC PHY Measure Unit Register
address_offset : 0x8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MU_BYP_VAL : no description available
bits : 0 - 9 (10 bit)
access : read-write
MU_BYP_EN : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The delay-lines use delay units as indicated at MU_UNIT_DEL_NUM.
#1 : 1
The delay-lines use delay units as indicated at MU_BYPASS_VAL.
End of enumeration elements list.
FRC_MSR : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No measurement is performed
#1 : 1
Perform measurement process
End of enumeration elements list.
MU_UNIT_DEL_NUM : no description available
bits : 16 - 25 (10 bit)
access : read-only
MMDC Write CA delay-line controller
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_CA0_DEL : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA0 delay
#01 : 01
Add CA0 delay of 1 delay unit
#10 : 10
Add CA0 delay of 2 delay units.
#11 : 11
Add CA0 delay of 3 delay units.
End of enumeration elements list.
WR_CA1_DEL : no description available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA1 delay
#01 : 01
Add CA1 delay of 1 delay unit
#10 : 10
Add CA1 delay of 2 delay units.
#11 : 11
Add CA1 delay of 3 delay units.
End of enumeration elements list.
WR_CA2_DEL : no description available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA2 delay
#01 : 01
Add CA2 delay of 1 delay unit
#10 : 10
Add CA2 delay of 2 delay units.
#11 : 11
Add CA2 delay of 3 delay units.
End of enumeration elements list.
WR_CA3_DEL : no description available
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA3 delay
#01 : 01
Add CA3 delay of 1 delay unit
#10 : 10
Add CA3 delay of 2 delay units.
#11 : 11
Add CA3 delay of 3 delay units.
End of enumeration elements list.
WR_CA4_DEL : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA4 delay
#01 : 01
Add CA4 delay of 1 delay unit
#10 : 10
Add CA4 delay of 2 delay units.
#11 : 11
Add CA4 delay of 3 delay units.
End of enumeration elements list.
WR_CA5_DEL : no description available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA5 delay
#01 : 01
Add CA5 delay of 1 delay unit
#10 : 10
Add CA5 delay of 2 delay units.
#11 : 11
Add CA5 delay of 3 delay units.
End of enumeration elements list.
WR_CA6_DEL : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA6 delay
#01 : 01
Add CA6 delay of 1 delay unit
#10 : 10
Add CA6 delay of 2 delay units.
#11 : 11
Add CA6 delay of 3 delay units.
End of enumeration elements list.
WR_CA7_DEL : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA7 delay
#01 : 01
Add CA7 delay of 1 delay unit
#10 : 10
Add CA7 delay of 2 delay units.
#11 : 11
Add CA7 delay of 3 delay units.
End of enumeration elements list.
WR_CA8_DEL : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA8 delay
#01 : 01
Add CA8 delay of 1 delay unit
#10 : 10
Add CA8 delay of 2 delay units.
#11 : 11
Add CA8 delay of 3 delay units.
End of enumeration elements list.
WR_CA9_DEL : no description available
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
No change in CA9 delay
#01 : 01
Add CA9 delay of 1 delay unit
#10 : 10
Add CA9 delay of 2 delay units.
#11 : 11
Add CA9 delay of 3 delay units.
End of enumeration elements list.
MMDC Duty Cycle Control Register
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_DQS0_FT_DCC : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#001 : 001
51.5% low 48.5% high
#010 : 010
50% duty cycle (default)
#100 : 100
48.5% low 51.5% high
End of enumeration elements list.
WR_DQS1_FT_DCC : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#001 : 001
51.5% low 48.5% high
#010 : 010
50% duty cycle (default)
#100 : 100
48.5% low 51.5% high
End of enumeration elements list.
CK_FT0_DCC : no description available
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#001 : 001
51.5% low 48.5% high
#010 : 010
50% duty cycle (default)
#100 : 100
48.5% low 51.5% high
End of enumeration elements list.
CK_FT1_DCC : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#001 : 001
51.5% low 48.5% high
#010 : 010
50% duty cycle (default)
#100 : 100
48.5% low 51.5% high
End of enumeration elements list.
RD_DQS0_FT_DCC : no description available
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
#001 : 001
51.5% low 48.5% high
#010 : 010
50% duty cycle (default)
#100 : 100
48.5% low 51.5% high
End of enumeration elements list.
RD_DQS1_FT_DCC : no description available
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
#001 : 001
51.5% low 48.5% high
#010 : 010
50% duty cycle (default)
#100 : 100
48.5% low 51.5% high
End of enumeration elements list.
MMDC Core Timing Configuration Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tCL : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0 : 0
3 cycles
#1 : 1
4 cycles
#10 : 10
5 cycles
#11 : 11
6 cycles
#100 : 100
7 cycles
#101 : 101
8 cycles
#110 : 110
9 cycles
#111 : 111
10 cycles
#1000 : 1000
11 cycles
#1001 : 1001
- 0xF Reserved
End of enumeration elements list.
tFAW : no description available
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#11110 : 11110
31 clocks
#11111 : 11111
32 clocks
End of enumeration elements list.
tXPDLL : no description available
bits : 9 - 12 (4 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#1110 : 1110
15 clocks
#1111 : 1111
16 clocks
End of enumeration elements list.
tXP : no description available
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
#0 : 0
1 cycle
#1 : 1
2 cycles
#110 : 110
7 cycles
#111 : 111
8 cycles
End of enumeration elements list.
tXS : no description available
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#0 : 0
- 0x15 reserved
#10110 : 10110
23 clocks
#10111 : 10111
24 clocks
#11111110 : 11111110
255 clocks
#11111111 : 11111111
256 clocks
End of enumeration elements list.
tRFC : no description available
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
#0 : 0
1 clock
#1 : 1
2 clocks
#10 : 10
3 clocks
#11111110 : 11111110
255 clocks
#11111111 : 11111111
256 clocks
End of enumeration elements list.
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