Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
CSI Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL_BIT : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
8-bit data for each pixel
#1 : 1
10-bit data for each pixel
End of enumeration elements list.
REDGE : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pixel data is latched at the falling edge of CSI_PIXCLK
#1 : 1
Pixel data is latched at the rising edge of CSI_PIXCLK
End of enumeration elements list.
INV_PCLK : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CSI_PIXCLK is directly applied to internal circuitry
#1 : 1
CSI_PIXCLK is inverted before applied to internal circuitry
End of enumeration elements list.
INV_DATA : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
CSI_D[7:0] data lines are directly applied to internal circuitry
#1 : 1
CSI_D[7:0] data lines are inverted before applied to internal circuitry
End of enumeration elements list.
GCLK_MODE : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
#1 : 1
Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
End of enumeration elements list.
CLR_RXFIFO : no description available
bits : 5 - 5 (1 bit)
access : read-write
CLR_STATFIFO : no description available
bits : 6 - 6 (1 bit)
access : read-write
PACK_DIR : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
#1 : 1
Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
End of enumeration elements list.
FCC : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Asynchronous FIFO clear is selected.
#1 : 1
Synchronous FIFO clear is selected.
End of enumeration elements list.
CCIR_EN : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Traditional interface is selected. Timing interface logic is used to latch data.
#1 : 1
CCIR656 interface is selected.
End of enumeration elements list.
HSYNC_POL : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSYNC is active low
#1 : 1
HSYNC is active high
End of enumeration elements list.
SOF_INTEN : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOF interrupt disable
#1 : 1
SOF interrupt enable
End of enumeration elements list.
SOF_POL : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOF interrupt is generated on SOF falling edge
#1 : 1
SOF interrupt is generated on SOF rising edge
End of enumeration elements list.
RXFF_INTEN : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
RxFIFO full interrupt disable
#1 : 1
RxFIFO full interrupt enable
End of enumeration elements list.
FB1_DMA_DONE_INTEN : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Buffer1 DMA Transfer Done interrupt disable
#1 : 1
Frame Buffer1 DMA Transfer Done interrupt enable
End of enumeration elements list.
FB2_DMA_DONE_INTEN : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Buffer2 DMA Transfer Done interrupt disable
#1 : 1
Frame Buffer2 DMA Transfer Done interrupt enable
End of enumeration elements list.
STATFF_INTEN : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
STATFIFO full interrupt disable
#1 : 1
STATFIFO full interrupt enable
End of enumeration elements list.
SFF_DMA_DONE_INTEN : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
STATFIFO DMA Transfer Done interrupt disable
#1 : 1
STATFIFO DMA Transfer Done interrupt enable
End of enumeration elements list.
RF_OR_INTEN : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
RxFIFO overrun interrupt is disabled
#1 : 1
RxFIFO overrun interrupt is enabled
End of enumeration elements list.
SF_OR_INTEN : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
STATFIFO overrun interrupt is disabled
#1 : 1
STATFIFO overrun interrupt is enabled
End of enumeration elements list.
COF_INT_EN : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
COF interrupt is disabled
#1 : 1
COF interrupt is enabled
End of enumeration elements list.
VIDEO_MODE : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Progressive mode is selected
#1 : 1
Interlace mode is selected
End of enumeration elements list.
PrP_IF_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
CSI to PrP bus is disabled
#1 : 1
CSI to PrP bus is enabled
End of enumeration elements list.
EOF_INT_EN : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EOF interrupt is disabled.
#1 : 1
EOF interrupt is generated when RX count value is reached.
End of enumeration elements list.
EXT_VSYNC : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal VSYNC mode
#1 : 1
External VSYNC mode
End of enumeration elements list.
SWAP16_EN : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable swapping
#1 : 1
Enable swapping
End of enumeration elements list.
CSI RX FIFO Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMAGE : no description available
bits : 0 - 31 (32 bit)
access : read-only
CSI RX Count Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCNT : no description available
bits : 0 - 21 (22 bit)
access : read-write
CSI Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRDY : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No data (word) is ready
#1 : 1
At least 1 datum (word) is ready in RXFIFO.
End of enumeration elements list.
ECC_INT : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No error detected
#1 : 1
Error is detected in CCIR coding
End of enumeration elements list.
HRESP_ERR_INT : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No hresponse error.
#1 : 1
Hresponse error is detected.
End of enumeration elements list.
COF_INT : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Video field has no change.
#1 : 1
Change of video field is detected.
End of enumeration elements list.
F1_INT : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Field 1 of video is not detected.
#1 : 1
Field 1 of video is about to start.
End of enumeration elements list.
F2_INT : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Field 2 of video is not detected
#1 : 1
Field 2 of video is about to start
End of enumeration elements list.
SOF_INT : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOF is not detected.
#1 : 1
SOF is detected.
End of enumeration elements list.
EOF_INT : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EOF is not detected.
#1 : 1
EOF is detected.
End of enumeration elements list.
RxFF_INT : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
RxFIFO is not full.
#1 : 1
RxFIFO is full.
End of enumeration elements list.
DMA_TSF_DONE_FB1 : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not completed.
#1 : 1
DMA transfer is completed.
End of enumeration elements list.
DMA_TSF_DONE_FB2 : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not completed.
#1 : 1
DMA transfer is completed.
End of enumeration elements list.
STATFF_INT : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
STATFIFO is not full.
#1 : 1
STATFIFO is full.
End of enumeration elements list.
DMA_TSF_DONE_SFF : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not completed.
#1 : 1
DMA transfer is completed.
End of enumeration elements list.
RF_OR_INT : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXFIFO has not overflowed.
#1 : 1
RXFIFO has overflowed.
End of enumeration elements list.
SF_OR_INT : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
STATFIFO has not overflowed.
#1 : 1
STATFIFO has overflowed.
End of enumeration elements list.
DMA_FIELD1_DONE : no description available
bits : 26 - 26 (1 bit)
access : read-write
DMA_FIELD0_DONE : no description available
bits : 27 - 27 (1 bit)
access : read-write
BASEADDR_CHHANGE_ERROR : no description available
bits : 28 - 28 (1 bit)
access : read-write
CSI DMA Start Address Register - for STATFIFO
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START_ADDR_SFF : no description available
bits : 2 - 31 (30 bit)
access : read-write
CSI DMA Transfer Size Register - for STATFIFO
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_TSF_SIZE_SFF : no description available
bits : 0 - 31 (32 bit)
access : read-write
CSI DMA Start Address Register - for Frame Buffer1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START_ADDR_FB1 : no description available
bits : 2 - 31 (30 bit)
access : read-write
CSI DMA Transfer Size Register - for Frame Buffer2
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_START_ADDR_FB2 : no description available
bits : 2 - 31 (30 bit)
access : read-write
CSI Frame Buffer Parameter Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBUF_STRIDE : no description available
bits : 0 - 15 (16 bit)
access : read-write
DEINTERLACE_STRIDE : no description available
bits : 16 - 31 (16 bit)
access : read-write
CSI Image Parameter Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMAGE_HEIGHT : no description available
bits : 0 - 15 (16 bit)
access : read-write
IMAGE_WIDTH : no description available
bits : 16 - 31 (16 bit)
access : read-write
CSI Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSC : no description available
bits : 0 - 7 (8 bit)
access : read-write
VSC : no description available
bits : 8 - 15 (8 bit)
access : read-write
LVRM : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#0 : 0
512 x 384
#1 : 1
448 x 336
End of enumeration elements list.
BTS : no description available
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 00
GR
#01 : 01
RG
#10 : 10
BG
#11 : 11
GB
End of enumeration elements list.
SCE : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Skip count disable
#1 : 1
Skip count enable
End of enumeration elements list.
AFS : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Abs Diff on consecutive green pixels
#01 : 01
Abs Diff on every third green pixels
#1x : 1x
Abs Diff on every four green pixels
End of enumeration elements list.
DRM : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stats grid of 8 x 6
#1 : 1
Stats grid of 8 x 12
End of enumeration elements list.
DMA_BURST_TYPE_SFF : no description available
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#01 : 01
INCR4
#11 : 11
INCR16
End of enumeration elements list.
DMA_BURST_TYPE_RFF : no description available
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#01 : 01
INCR4
#11 : 11
INCR16
End of enumeration elements list.
CSI Control Register 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTSC_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PAL
#1 : 1
NTSC
End of enumeration elements list.
DEINTERLACE_EN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Deinterlace disabled
#1 : 1
Deinterlace enabled
End of enumeration elements list.
PARALLEL24_EN : no description available
bits : 3 - 3 (1 bit)
access : read-write
BASEADDR_SWITCH_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
BASEADDR_SWITCH_SEL : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Switching base address at the edge of the vsync
#1 : 1
Switching base address at the edge of the first data of each frame
End of enumeration elements list.
FIELD0_DONE_IE : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
DMA_FIELD1_DONE_IE : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
LAST_DMA_REQ_SEL : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
fifo_full_level
#1 : 1
hburst_length
End of enumeration elements list.
BASEADDR_CHANGE_ERROR_IE : no description available
bits : 9 - 9 (1 bit)
access : read-write
RGB888A_FORMAT_SEL : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
{8'h0, data[23:0]}
#1 : 1
{data[23:0], 8'h0}
End of enumeration elements list.
AHB_HPROT : no description available
bits : 12 - 15 (4 bit)
access : read-write
CSI_LCDIF_BUFFER_LINES : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
4 lines
#01 : 01
8 lines
End of enumeration elements list.
MASK_OPTION : no description available
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
#01 : 01
Writing to memory when CSI_ENABLE is 1.
End of enumeration elements list.
CSI_ENABLE : no description available
bits : 31 - 31 (1 bit)
access : read-write
CSI Control Register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC_AUTO_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto Error correction is disabled.
#1 : 1
Auto Error correction is enabled.
End of enumeration elements list.
ECC_INT_EN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
#1 : 1
Interrupt is generated when error is detected.
End of enumeration elements list.
ZERO_PACK_EN : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero packing disabled
#1 : 1
Zero packing enabled
End of enumeration elements list.
TWO_8BIT_SENSOR : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only one sensor is connected.
#1 : 1
Two 8-bit sensors are connected or one 16-bit sensor is connected.
End of enumeration elements list.
RxFF_LEVEL : no description available
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
4 Double words
#001 : 001
8 Double words
#010 : 010
16 Double words
#011 : 011
24 Double words
#100 : 100
32 Double words
#101 : 101
48 Double words
#110 : 110
64 Double words
#111 : 111
96 Double words
End of enumeration elements list.
HRESP_ERR_EN : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable hresponse error interrupt
#1 : 1
Enable hresponse error interrupt
End of enumeration elements list.
STATFF_LEVEL : no description available
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
4 Double words
#001 : 001
8 Double words
#010 : 010
12 Double words
#011 : 011
16 Double words
#100 : 100
24 Double words
#101 : 101
32 Double words
#110 : 110
48 Double words
#111 : 111
64 Double words
End of enumeration elements list.
DMA_REQ_EN_SFF : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the dma request
#1 : 1
Enable the dma request
End of enumeration elements list.
DMA_REQ_EN_RFF : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the dma request
#1 : 1
Enable the dma request
End of enumeration elements list.
DMA_REFLASH_SFF : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reflashing
#1 : 1
Reflash the embedded DMA controller
End of enumeration elements list.
DMA_REFLASH_RFF : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reflashing
#1 : 1
Reflash the embedded DMA controller
End of enumeration elements list.
FRMCNT_RST : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not reset
#1 : 1
Reset frame counter immediately
End of enumeration elements list.
FRMCNT : no description available
bits : 16 - 31 (16 bit)
access : read-write
CSI Statistic FIFO Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STAT : no description available
bits : 0 - 31 (32 bit)
access : read-only
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