\n

DMAMUX0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CHCFG0

CHCFG1

CHCFG2

CHCFG3


CHCFG0

Channel Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG0 CHCFG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Software_DMA_Request

#10 : 2

UART0_Receive_DMA_Request

#11 : 3

UART0_Transmit_DMA_Request

#100 : 4

UART1_Receive_DMA_Request

#101 : 5

UART1_Transmit_DMA_Request

#110 : 6

UART2_Receive_DMA_Request

#111 : 7

UART2_Transmit_DMA_Request

#1110 : 14

I2S0_Receive_DMA_Request

#1111 : 15

I2S0_Transmit_DMA_Request

#10000 : 16

SPI0_Receive_DMA_Request

#10001 : 17

SPI0_Transmit_DMA_Request

#10110 : 22

I2C0_DMA_Request

#11000 : 24

FTM0_C0_DMA_Request

#11001 : 25

FTM0_C1_DMA_Request

#11010 : 26

FTM0_C2_DMA_Request

#11011 : 27

FTM0_C3_DMA_Request

#11100 : 28

FTM0_C4_DMA_Request

#11101 : 29

FTM0_C5_DMA_Request

#11110 : 30

FTM0_C6_DMA_Request

#11111 : 31

FTM0_C7_DMA_Request

#100000 : 32

FTM1_C0_DMA_Request

#100001 : 33

FTM1_C1_DMA_Request

#101000 : 40

ADC0_DMA_Request

#101010 : 42

CMP0_DMA_Request

#101011 : 43

CMP1_DMA_Request

#101111 : 47

CMT_DMA_Request

#110000 : 48

PDB_DMA_Request

#110001 : 49

GPIO_Port_A_DMA_Request

#110010 : 50

GPIO_Port_B_DMA_Request

#110011 : 51

GPIO_Port_C_DMA_Request

#110100 : 52

GPIO_Port_D_DMA_Request

#110101 : 53

GPIO_Port_E_DMA_Request

#110110 : 54

Always_Enabled_slot_54_DMA_Request

#110111 : 55

Always_Enabled_slot_55_DMA_Request

#111000 : 56

Always_Enabled_slot_56_DMA_Request

#111001 : 57

Always_Enabled_slot_57_DMA_Request

#111010 : 58

Always_Enabled_slot_58_DMA_Request

#111011 : 59

Always_Enabled_slot_59_DMA_Request

#111100 : 60

Always_Enabled_slot_60_DMA_Request

#111101 : 61

Always_Enabled_slot_61_DMA_Request

#111110 : 62

Always_Enabled_slot_62_DMA_Request

#111111 : 63

Always_Enabled_slot_63_DMA_Request

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG1

Channel Configuration Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG1 CHCFG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Software_DMA_Request

#10 : 2

UART0_Receive_DMA_Request

#11 : 3

UART0_Transmit_DMA_Request

#100 : 4

UART1_Receive_DMA_Request

#101 : 5

UART1_Transmit_DMA_Request

#110 : 6

UART2_Receive_DMA_Request

#111 : 7

UART2_Transmit_DMA_Request

#1110 : 14

I2S0_Receive_DMA_Request

#1111 : 15

I2S0_Transmit_DMA_Request

#10000 : 16

SPI0_Receive_DMA_Request

#10001 : 17

SPI0_Transmit_DMA_Request

#10110 : 22

I2C0_DMA_Request

#11000 : 24

FTM0_C0_DMA_Request

#11001 : 25

FTM0_C1_DMA_Request

#11010 : 26

FTM0_C2_DMA_Request

#11011 : 27

FTM0_C3_DMA_Request

#11100 : 28

FTM0_C4_DMA_Request

#11101 : 29

FTM0_C5_DMA_Request

#11110 : 30

FTM0_C6_DMA_Request

#11111 : 31

FTM0_C7_DMA_Request

#100000 : 32

FTM1_C0_DMA_Request

#100001 : 33

FTM1_C1_DMA_Request

#101000 : 40

ADC0_DMA_Request

#101010 : 42

CMP0_DMA_Request

#101011 : 43

CMP1_DMA_Request

#101111 : 47

CMT_DMA_Request

#110000 : 48

PDB_DMA_Request

#110001 : 49

GPIO_Port_A_DMA_Request

#110010 : 50

GPIO_Port_B_DMA_Request

#110011 : 51

GPIO_Port_C_DMA_Request

#110100 : 52

GPIO_Port_D_DMA_Request

#110101 : 53

GPIO_Port_E_DMA_Request

#110110 : 54

Always_Enabled_slot_54_DMA_Request

#110111 : 55

Always_Enabled_slot_55_DMA_Request

#111000 : 56

Always_Enabled_slot_56_DMA_Request

#111001 : 57

Always_Enabled_slot_57_DMA_Request

#111010 : 58

Always_Enabled_slot_58_DMA_Request

#111011 : 59

Always_Enabled_slot_59_DMA_Request

#111100 : 60

Always_Enabled_slot_60_DMA_Request

#111101 : 61

Always_Enabled_slot_61_DMA_Request

#111110 : 62

Always_Enabled_slot_62_DMA_Request

#111111 : 63

Always_Enabled_slot_63_DMA_Request

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG2

Channel Configuration Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG2 CHCFG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Software_DMA_Request

#10 : 2

UART0_Receive_DMA_Request

#11 : 3

UART0_Transmit_DMA_Request

#100 : 4

UART1_Receive_DMA_Request

#101 : 5

UART1_Transmit_DMA_Request

#110 : 6

UART2_Receive_DMA_Request

#111 : 7

UART2_Transmit_DMA_Request

#1110 : 14

I2S0_Receive_DMA_Request

#1111 : 15

I2S0_Transmit_DMA_Request

#10000 : 16

SPI0_Receive_DMA_Request

#10001 : 17

SPI0_Transmit_DMA_Request

#10110 : 22

I2C0_DMA_Request

#11000 : 24

FTM0_C0_DMA_Request

#11001 : 25

FTM0_C1_DMA_Request

#11010 : 26

FTM0_C2_DMA_Request

#11011 : 27

FTM0_C3_DMA_Request

#11100 : 28

FTM0_C4_DMA_Request

#11101 : 29

FTM0_C5_DMA_Request

#11110 : 30

FTM0_C6_DMA_Request

#11111 : 31

FTM0_C7_DMA_Request

#100000 : 32

FTM1_C0_DMA_Request

#100001 : 33

FTM1_C1_DMA_Request

#101000 : 40

ADC0_DMA_Request

#101010 : 42

CMP0_DMA_Request

#101011 : 43

CMP1_DMA_Request

#101111 : 47

CMT_DMA_Request

#110000 : 48

PDB_DMA_Request

#110001 : 49

GPIO_Port_A_DMA_Request

#110010 : 50

GPIO_Port_B_DMA_Request

#110011 : 51

GPIO_Port_C_DMA_Request

#110100 : 52

GPIO_Port_D_DMA_Request

#110101 : 53

GPIO_Port_E_DMA_Request

#110110 : 54

Always_Enabled_slot_54_DMA_Request

#110111 : 55

Always_Enabled_slot_55_DMA_Request

#111000 : 56

Always_Enabled_slot_56_DMA_Request

#111001 : 57

Always_Enabled_slot_57_DMA_Request

#111010 : 58

Always_Enabled_slot_58_DMA_Request

#111011 : 59

Always_Enabled_slot_59_DMA_Request

#111100 : 60

Always_Enabled_slot_60_DMA_Request

#111101 : 61

Always_Enabled_slot_61_DMA_Request

#111110 : 62

Always_Enabled_slot_62_DMA_Request

#111111 : 63

Always_Enabled_slot_63_DMA_Request

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.


CHCFG3

Channel Configuration Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCFG3 CHCFG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SOURCE TRIG ENBL

SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

#0 : 0

Software_DMA_Request

#10 : 2

UART0_Receive_DMA_Request

#11 : 3

UART0_Transmit_DMA_Request

#100 : 4

UART1_Receive_DMA_Request

#101 : 5

UART1_Transmit_DMA_Request

#110 : 6

UART2_Receive_DMA_Request

#111 : 7

UART2_Transmit_DMA_Request

#1110 : 14

I2S0_Receive_DMA_Request

#1111 : 15

I2S0_Transmit_DMA_Request

#10000 : 16

SPI0_Receive_DMA_Request

#10001 : 17

SPI0_Transmit_DMA_Request

#10110 : 22

I2C0_DMA_Request

#11000 : 24

FTM0_C0_DMA_Request

#11001 : 25

FTM0_C1_DMA_Request

#11010 : 26

FTM0_C2_DMA_Request

#11011 : 27

FTM0_C3_DMA_Request

#11100 : 28

FTM0_C4_DMA_Request

#11101 : 29

FTM0_C5_DMA_Request

#11110 : 30

FTM0_C6_DMA_Request

#11111 : 31

FTM0_C7_DMA_Request

#100000 : 32

FTM1_C0_DMA_Request

#100001 : 33

FTM1_C1_DMA_Request

#101000 : 40

ADC0_DMA_Request

#101010 : 42

CMP0_DMA_Request

#101011 : 43

CMP1_DMA_Request

#101111 : 47

CMT_DMA_Request

#110000 : 48

PDB_DMA_Request

#110001 : 49

GPIO_Port_A_DMA_Request

#110010 : 50

GPIO_Port_B_DMA_Request

#110011 : 51

GPIO_Port_C_DMA_Request

#110100 : 52

GPIO_Port_D_DMA_Request

#110101 : 53

GPIO_Port_E_DMA_Request

#110110 : 54

Always_Enabled_slot_54_DMA_Request

#110111 : 55

Always_Enabled_slot_55_DMA_Request

#111000 : 56

Always_Enabled_slot_56_DMA_Request

#111001 : 57

Always_Enabled_slot_57_DMA_Request

#111010 : 58

Always_Enabled_slot_58_DMA_Request

#111011 : 59

Always_Enabled_slot_59_DMA_Request

#111100 : 60

Always_Enabled_slot_60_DMA_Request

#111101 : 61

Always_Enabled_slot_61_DMA_Request

#111110 : 62

Always_Enabled_slot_62_DMA_Request

#111111 : 63

Always_Enabled_slot_63_DMA_Request

End of enumeration elements list.

TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)

#1 : 1

Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.

End of enumeration elements list.

ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.

#1 : 1

DMA channel is enabled

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.