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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCR

TXFR3

RXFR1

CTAR0

RXFR2

CTAR1

RXFR3

SR

RSER

PUSHR

PUSHR_SLAVE

POPR

TXFR0

TCR

TXFR1

CTAR_SLAVE

RXFR0

TXFR2


MCR

Module Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT RESERVED RESERVED RESERVED SMPL_PT CLR_RXF CLR_TXF DIS_RXF DIS_TXF MDIS DOZE PCSIS RESERVED ROOE RESERVED MTFE FRZ DCONF CONT_SCKE MSTR

HALT : Halt
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Start transfers.

#1 : 1

Stop transfers.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

SMPL_PT : Sample Point
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

0 system clocks between SCK edge and SIN sample

#01 : 01

1 system clock between SCK edge and SIN sample

#10 : 10

2 system clocks between SCK edge and SIN sample

#11 : 11

Reserved

End of enumeration elements list.

CLR_RXF : no description available
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

#0 : 0

Do not clear the RX FIFO counter.

#1 : 1

Clear the RX FIFO counter.

End of enumeration elements list.

CLR_TXF : Clear TX FIFO
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

#0 : 0

Do not clear the TX FIFO counter.

#1 : 1

Clear the TX FIFO counter.

End of enumeration elements list.

DIS_RXF : Disable Receive FIFO
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

RX FIFO is enabled.

#1 : 1

RX FIFO is disabled.

End of enumeration elements list.

DIS_TXF : Disable Transmit FIFO
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

TX FIFO is enabled.

#1 : 1

TX FIFO is disabled.

End of enumeration elements list.

MDIS : Module Disable
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enables the module clocks.

#1 : 1

Allows external logic to disable the module clocks.

End of enumeration elements list.

DOZE : Doze Enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Doze mode has no effect on the module.

#1 : 1

Doze mode disables the module.

End of enumeration elements list.

PCSIS : Peripheral Chip Select x Inactive State
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

#0 : 0

The inactive state of PCSx is low.

#1 : 1

The inactive state of PCSx is high.

End of enumeration elements list.

RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only

ROOE : Receive FIFO Overflow Overwrite Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Incoming data is ignored.

#1 : 1

Incoming data is shifted into the shift register.

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-only

MTFE : Modified Timing Format Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Modified SPI transfer format disabled.

#1 : 1

Modified SPI transfer format enabled.

End of enumeration elements list.

FRZ : Freeze
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not halt serial transfers in Debug mode.

#1 : 1

Halt serial transfers in Debug mode.

End of enumeration elements list.

DCONF : DSPI Configuration.
bits : 28 - 29 (2 bit)
access : read-only

Enumeration:

#00 : 00

SPI

#01 : 01

Reserved

#10 : 10

Reserved

#11 : 11

Reserved

End of enumeration elements list.

CONT_SCKE : Continuous SCK Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Continuous SCK disabled.

#1 : 1

Continuous SCK enabled.

End of enumeration elements list.

MSTR : Master/Slave Mode Select
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

The module is in Slave mode.

#1 : 1

The module is in Master mode.

End of enumeration elements list.


TXFR3

DSPI Transmit FIFO Registers
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFR3 TXFR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA TXCMD_TXDATA

TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only

TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only


RXFR1

DSPI Receive FIFO Registers
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFR1 RXFR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only


CTAR0

Clock and Transfer Attributes Register (In Master Mode)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI2
reset_Mask : 0x0

CTAR0 CTAR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR DT ASC CSSCK PBR PDT PASC PCSSCK LSBFE CPHA CPOL FMSZ DBR

BR : Baud Rate Scaler
bits : 0 - 3 (4 bit)
access : read-write

DT : Delay After Transfer Scaler
bits : 4 - 7 (4 bit)
access : read-write

ASC : After SCK Delay Scaler
bits : 8 - 11 (4 bit)
access : read-write

CSSCK : PCS to SCK Delay Scaler
bits : 12 - 15 (4 bit)
access : read-write

PBR : Baud Rate Prescaler
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Baud Rate Prescaler value is 2.

#01 : 01

Baud Rate Prescaler value is 3.

#10 : 10

Baud Rate Prescaler value is 5.

#11 : 11

Baud Rate Prescaler value is 7.

End of enumeration elements list.

PDT : Delay after Transfer Prescaler
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 00

Delay after Transfer Prescaler value is 1.

#01 : 01

Delay after Transfer Prescaler value is 3.

#10 : 10

Delay after Transfer Prescaler value is 5.

#11 : 11

Delay after Transfer Prescaler value is 7.

End of enumeration elements list.

PASC : After SCK Delay Prescaler
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

Delay after Transfer Prescaler value is 1.

#01 : 01

Delay after Transfer Prescaler value is 3.

#10 : 10

Delay after Transfer Prescaler value is 5.

#11 : 11

Delay after Transfer Prescaler value is 7.

End of enumeration elements list.

PCSSCK : PCS to SCK Delay Prescaler
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 00

PCS to SCK Prescaler value is 1.

#01 : 01

PCS to SCK Prescaler value is 3.

#10 : 10

PCS to SCK Prescaler value is 5.

#11 : 11

PCS to SCK Prescaler value is 7.

End of enumeration elements list.

LSBFE : LSB First
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data is transferred MSB first.

#1 : 1

Data is transferred LSB first.

End of enumeration elements list.

CPHA : Clock Phase
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data is captured on the leading edge of SCK and changed on the following edge.

#1 : 1

Data is changed on the leading edge of SCK and captured on the following edge.

End of enumeration elements list.

CPOL : Clock Polarity
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

The inactive state value of SCK is low.

#1 : 1

The inactive state value of SCK is high.

End of enumeration elements list.

FMSZ : Frame Size
bits : 27 - 30 (4 bit)
access : read-write

DBR : Double Baud Rate
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

The baud rate is computed normally with a 50/50 duty cycle.

#1 : 1

The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

End of enumeration elements list.


RXFR2

DSPI Receive FIFO Registers
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFR2 RXFR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only


CTAR1

Clock and Transfer Attributes Register (In Master Mode)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI2
reset_Mask : 0x0

CTAR1 CTAR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR DT ASC CSSCK PBR PDT PASC PCSSCK LSBFE CPHA CPOL FMSZ DBR

BR : Baud Rate Scaler
bits : 0 - 3 (4 bit)
access : read-write

DT : Delay After Transfer Scaler
bits : 4 - 7 (4 bit)
access : read-write

ASC : After SCK Delay Scaler
bits : 8 - 11 (4 bit)
access : read-write

CSSCK : PCS to SCK Delay Scaler
bits : 12 - 15 (4 bit)
access : read-write

PBR : Baud Rate Prescaler
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Baud Rate Prescaler value is 2.

#01 : 01

Baud Rate Prescaler value is 3.

#10 : 10

Baud Rate Prescaler value is 5.

#11 : 11

Baud Rate Prescaler value is 7.

End of enumeration elements list.

PDT : Delay after Transfer Prescaler
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 00

Delay after Transfer Prescaler value is 1.

#01 : 01

Delay after Transfer Prescaler value is 3.

#10 : 10

Delay after Transfer Prescaler value is 5.

#11 : 11

Delay after Transfer Prescaler value is 7.

End of enumeration elements list.

PASC : After SCK Delay Prescaler
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

Delay after Transfer Prescaler value is 1.

#01 : 01

Delay after Transfer Prescaler value is 3.

#10 : 10

Delay after Transfer Prescaler value is 5.

#11 : 11

Delay after Transfer Prescaler value is 7.

End of enumeration elements list.

PCSSCK : PCS to SCK Delay Prescaler
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 00

PCS to SCK Prescaler value is 1.

#01 : 01

PCS to SCK Prescaler value is 3.

#10 : 10

PCS to SCK Prescaler value is 5.

#11 : 11

PCS to SCK Prescaler value is 7.

End of enumeration elements list.

LSBFE : LSB First
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data is transferred MSB first.

#1 : 1

Data is transferred LSB first.

End of enumeration elements list.

CPHA : Clock Phase
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data is captured on the leading edge of SCK and changed on the following edge.

#1 : 1

Data is changed on the leading edge of SCK and captured on the following edge.

End of enumeration elements list.

CPOL : Clock Polarity
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

The inactive state value of SCK is low.

#1 : 1

The inactive state value of SCK is high.

End of enumeration elements list.

FMSZ : Frame Size
bits : 27 - 30 (4 bit)
access : read-write

DBR : Double Baud Rate
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

The baud rate is computed normally with a 50/50 duty cycle.

#1 : 1

The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

End of enumeration elements list.


RXFR3

DSPI Receive FIFO Registers
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFR3 RXFR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only


SR

DSPI Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POPNXTPTR RXCTR TXNXTPTR TXCTR RESERVED RFDF RESERVED RFOF RESERVED RESERVED RESERVED RESERVED RESERVED TFFF RESERVED TFUF EOQF RESERVED TXRXS TCF

POPNXTPTR : Pop Next Pointer
bits : 0 - 3 (4 bit)
access : read-only

RXCTR : RX FIFO Counter
bits : 4 - 7 (4 bit)
access : read-only

TXNXTPTR : Transmit Next Pointer
bits : 8 - 11 (4 bit)
access : read-only

TXCTR : TX FIFO Counter
bits : 12 - 15 (4 bit)
access : read-only

RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only

RFDF : Receive FIFO Drain Flag
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

RX FIFO is empty.

#1 : 1

RX FIFO is not empty.

End of enumeration elements list.

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-only

RFOF : Receive FIFO Overflow Flag
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

No Rx FIFO overflow.

#1 : 1

Rx FIFO overflow has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

RESERVED : no description available
bits : 21 - 21 (1 bit)
access : read-only

RESERVED : no description available
bits : 22 - 22 (1 bit)
access : read-only

RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : no description available
bits : 24 - 24 (1 bit)
access : read-only

TFFF : Transmit FIFO Fill Flag
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

TX FIFO is full.

#1 : 1

TX FIFO is not full.

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only

TFUF : Transmit FIFO Underflow Flag
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

No TX FIFO underflow.

#1 : 1

TX FIFO underflow has occurred.

End of enumeration elements list.

EOQF : End of Queue Flag
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

EOQ is not set in the executing command.

#1 : 1

EOQ is set in the executing SPI command.

End of enumeration elements list.

RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only

TXRXS : TX and RX Status
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transmit and receive operations are disabled (The module is in Stopped state).

#1 : 1

Transmit and receive operations are enabled (The module is in Running state).

End of enumeration elements list.

TCF : Transfer Complete Flag
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transfer not complete.

#1 : 1

Transfer complete.

End of enumeration elements list.


RSER

DMA/Interrupt Request Select and Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSER RSER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED RFDF_DIRS RFDF_RE RESERVED RFOF_RE RESERVED RESERVED RESERVED RESERVED TFFF_DIRS TFFF_RE RESERVED TFUF_RE EOQF_RE RESERVED RESERVED TCF_RE

RESERVED : no description available
bits : 0 - 13 (14 bit)
access : read-only

RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only

RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only

RFDF_DIRS : Receive FIFO Drain DMA or Interrupt Request Select
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt request.

#1 : 1

DMA request.

End of enumeration elements list.

RFDF_RE : Receive FIFO Drain Request Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

RFDF interrupt or DMA requests are disabled.

#1 : 1

RFDF interrupt or DMA requests are enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-only

RFOF_RE : Receive FIFO Overflow Request Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

RFOF interrupt requests are disabled.

#1 : 1

RFOF interrupt requests are enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

RESERVED : no description available
bits : 21 - 21 (1 bit)
access : read-only

RESERVED : no description available
bits : 22 - 22 (1 bit)
access : read-only

RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only

TFFF_DIRS : Transmit FIFO Fill DMA or Interrupt Request Select
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

TFFF flag generates interrupt requests.

#1 : 1

TFFF flag generates DMA requests.

End of enumeration elements list.

TFFF_RE : Transmit FIFO Fill Request Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

TFFF interrupts or DMA requests are disabled.

#1 : 1

TFFF interrupts or DMA requests are enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only

TFUF_RE : Transmit FIFO Underflow Request Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

TFUF interrupt requests are disabled.

#1 : 1

TFUF interrupt requests are enabled.

End of enumeration elements list.

EOQF_RE : Finished Request Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

EOQF interrupt requests are disabled.

#1 : 1

EOQF interrupt requests are enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only

RESERVED : no description available
bits : 30 - 30 (1 bit)
access : read-only

TCF_RE : Transmission Complete Request Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

TCF interrupt requests are disabled.

#1 : 1

TCF interrupt requests are enabled.

End of enumeration elements list.


PUSHR

PUSH TX FIFO Register In Master Mode
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI2
reset_Mask : 0x0

PUSHR PUSHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA PCS RESERVED RESERVED CTCNT EOQ CTAS CONT

TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-write

PCS : no description available
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

#0 : 0

Negate the PCS[x] signal.

#1 : 1

Assert the PCS[x] signal.

End of enumeration elements list.

RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only

RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only

CTCNT : Clear Transfer Counter
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not clear the TCR[TCNT] field.

#1 : 1

Clear the TCR[TCNT] field.

End of enumeration elements list.

EOQ : End Of Queue
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

The SPI data is not the last data to transfer.

#1 : 1

The SPI data is the last data to transfer.

End of enumeration elements list.

CTAS : Clock and Transfer Attributes Select
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#000 : 000

CTAR0

#001 : 001

CTAR1

#010 : 010

Reserved

#011 : 011

Reserved

#100 : 100

Reserved

#101 : 101

Reserved

#110 : 110

Reserved

#111 : 111

Reserved

End of enumeration elements list.

CONT : Continuous Peripheral Chip Select Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Return PCSn signals to their inactive state between transfers.

#1 : 1

Keep PCSn signals asserted between transfers.

End of enumeration elements list.


PUSHR_SLAVE

PUSH TX FIFO Register In Slave Mode
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI2
reset_Mask : 0x0

PUSHR_SLAVE PUSHR_SLAVE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Transmit Data
bits : 0 - 31 (32 bit)
access : read-write


POPR

POP RX FIFO Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

POPR POPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Received Data
bits : 0 - 31 (32 bit)
access : read-only


TXFR0

DSPI Transmit FIFO Registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFR0 TXFR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA TXCMD_TXDATA

TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only

TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only


TCR

Transfer Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SPI_TCNT

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

SPI_TCNT : SPI Transfer Counter
bits : 16 - 31 (16 bit)
access : read-write


TXFR1

DSPI Transmit FIFO Registers
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFR1 TXFR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA TXCMD_TXDATA

TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only

TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only


CTAR_SLAVE

Clock and Transfer Attributes Register (In Slave Mode)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPI2
reset_Mask : 0x0

CTAR_SLAVE CTAR_SLAVE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED CPHA CPOL FMSZ

RESERVED : no description available
bits : 0 - 21 (22 bit)
access : read-only

RESERVED : no description available
bits : 22 - 22 (1 bit)
access : read-only

RESERVED : no description available
bits : 23 - 24 (2 bit)
access : read-only

CPHA : Clock Phase
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data is captured on the leading edge of SCK and changed on the following edge.

#1 : 1

Data is changed on the leading edge of SCK and captured on the following edge.

End of enumeration elements list.

CPOL : Clock Polarity
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

The inactive state value of SCK is low.

#1 : 1

The inactive state value of SCK is high.

End of enumeration elements list.

FMSZ : Frame Size
bits : 27 - 31 (5 bit)
access : read-write


RXFR0

DSPI Receive FIFO Registers
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXFR0 RXFR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Receive Data
bits : 0 - 31 (32 bit)
access : read-only


TXFR2

DSPI Transmit FIFO Registers
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TXFR2 TXFR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA TXCMD_TXDATA

TXDATA : Transmit Data
bits : 0 - 15 (16 bit)
access : read-only

TXCMD_TXDATA : Transmit Command or Transmit Data
bits : 16 - 31 (16 bit)
access : read-only



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