\n

CMT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

CGH1

CGL1

CGH2

CGL2

OC

MSC

CMD1

CMD2

CMD3

CMD4

PPS

DMA


CGH1

CMT Carrier Generator High Data Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGH1 CGH1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PH

PH : Primary Carrier High Time Data Value
bits : 0 - 7 (8 bit)
access : read-write


CGL1

CMT Carrier Generator Low Data Register 1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGL1 CGL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PL

PL : Primary Carrier Low Time Data Value
bits : 0 - 7 (8 bit)
access : read-write


CGH2

CMT Carrier Generator High Data Register 2
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGH2 CGH2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SH

SH : Secondary Carrier High Time Data Value
bits : 0 - 7 (8 bit)
access : read-write


CGL2

CMT Carrier Generator Low Data Register 2
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGL2 CGL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SL

SL : Secondary Carrier Low Time Data Value
bits : 0 - 7 (8 bit)
access : read-write


OC

CMT Output Control Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OC OC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESERVED IROPEN CMTPOL IROL

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

IROPEN : IRO Pin Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The IRO signal is disabled.

#1 : 1

The IRO signal is enabled as output.

End of enumeration elements list.

CMTPOL : CMT Output Polarity
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The IRO signal is active-low.

#1 : 1

The IRO signal is active-high.

End of enumeration elements list.

IROL : IRO Latch Control
bits : 7 - 7 (1 bit)
access : read-write


MSC

CMT Modulator Status and Control Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSC MSC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MCGEN EOCIE FSK BASE EXSPC CMTDIV EOCF

MCGEN : Modulator and Carrier Generator Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Modulator and carrier generator disabled

#1 : 1

Modulator and carrier generator enabled

End of enumeration elements list.

EOCIE : End of Cycle Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

CPU interrupt is disabled.

#1 : 1

CPU interrupt is enabled.

End of enumeration elements list.

FSK : FSK Mode Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The CMT operates in Time or Baseband mode.

#1 : 1

The CMT operates in FSK mode.

End of enumeration elements list.

BASE : Baseband Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Baseband mode is disabled.

#1 : 1

Baseband mode is enabled.

End of enumeration elements list.

EXSPC : Extended Space Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Extended space is disabled.

#1 : 1

Extended space is enabled.

End of enumeration elements list.

CMTDIV : CMT Clock Divide Prescaler
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

IF * 1

#01 : 01

IF * 2

#10 : 10

IF * 4

#11 : 11

IF * 8

End of enumeration elements list.

EOCF : End Of Cycle Status Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

End of modulation cycle has not occured since the flag last cleared.

#1 : 1

End of modulator cycle has occurred.

End of enumeration elements list.


CMD1

CMT Modulator Data Register Mark High
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD1 CMD1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MB

MB : no description available
bits : 0 - 7 (8 bit)
access : read-write


CMD2

CMT Modulator Data Register Mark Low
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD2 CMD2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MB

MB : no description available
bits : 0 - 7 (8 bit)
access : read-write


CMD3

CMT Modulator Data Register Space High
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD3 CMD3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SB

SB : no description available
bits : 0 - 7 (8 bit)
access : read-write


CMD4

CMT Modulator Data Register Space Low
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD4 CMD4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SB

SB : no description available
bits : 0 - 7 (8 bit)
access : read-write


PPS

CMT Primary Prescaler Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PPS PPS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PPSDIV RESERVED

PPSDIV : Primary Prescaler Divider
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Bus clock * 1

#0001 : 0001

Bus clock * 2

#0010 : 0010

Bus clock * 3

#0011 : 0011

Bus clock * 4

#0100 : 0100

Bus clock * 5

#0101 : 0101

Bus clock * 6

#0110 : 0110

Bus clock * 7

#0111 : 0111

Bus clock * 8

#1000 : 1000

Bus clock * 9

#1001 : 1001

Bus clock * 10

#1010 : 1010

Bus clock * 11

#1011 : 1011

Bus clock * 12

#1100 : 1100

Bus clock * 13

#1101 : 1101

Bus clock * 14

#1110 : 1110

Bus clock * 15

#1111 : 1111

Bus clock * 16

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only


DMA

CMT Direct Memory Access Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DMA RESERVED

DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA transfer request and done are disabled.

#1 : 1

DMA transfer request and done are enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.