\n
address_offset : 0x0 Bytes (0x0)
size : 0x1070 byte (0x0)
mem_usage : registers
protection : not protected
System Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only
RESERVED : no description available
bits : 8 - 9 (2 bit)
access : read-only
RESERVED : no description available
bits : 10 - 18 (9 bit)
access : read-only
OSC32KSEL : 32 kHz oscillator clock select
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
System oscillator (OSC32KCLK)
#1 : 1
RTC oscillator
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 28 (9 bit)
access : read-only
USBSTBY : USB voltage regulator in standby mode during VLP
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB voltage regulator not in standby during VLP mode.
#1 : 1
USB voltage regulator in standby during VLP mode.
End of enumeration elements list.
USBSSTBY : USB voltage regulator in standby mode dring stop
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB voltage regulator not in standby
#1 : 1
USB voltage regulator in standby,
End of enumeration elements list.
USBREGEN : USB voltage regulator enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB voltage regulator is disabled.
#1 : 1
USB voltage regulator is enabled
End of enumeration elements list.
System Options Register 2
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 1 (2 bit)
access : read-only
USBHSRC : USB HS clock source select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus clock
#01 : 01
MCGPLL1CLK
#10 : 10
MCGPLL2CLK
#11 : 11
EXTAL clock
End of enumeration elements list.
RTCCLKOUTSEL : RTC clock out select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC 1 Hz clock drives RTC CLKOUT.
#1 : 1
RTC 32 kHz oscillator drives RTC CLKOUT.
End of enumeration elements list.
CLKOUTSEL : Clock out select
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#001 : 001
Reserved
#010 : 010
Flash ungated clock
#011 : 011
LPO clock (1 kHz)
#100 : 100
MCGIRCLK
#101 : 101
RTC 32 kHz clock (OSC32KCLK)
#110 : 110
OSC0ERCLK
#111 : 111
OSC1ERCLK
End of enumeration elements list.
FBSL : Flexbus security level
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
All off-chip accesses (op code and data) via the FlexBus are disallowed.
#10 : 10
Off-chip op code accesses are disallowed. Data accesses are allowed.
#11 : 11
Off-chip op code accesses and data accesses are allowed.
End of enumeration elements list.
USBH_CLKSEL : USB HS controller clock select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock divider 60 MHz ULPI clock.
#1 : 1
External 60 MHz ULPI clock.
End of enumeration elements list.
CMTUARTPAD : CMT/UART pad drive strength
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-pad drive strength for CMT IRO or UART0_TXD.
#1 : 1
Dual-pad drive strength for CMT IRO or UART0_TXD.
End of enumeration elements list.
TRACECLKSEL : Debug trace clock select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGPLL1CLK
#1 : 1
Core/system clock
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 13 (1 bit)
access : read-only
RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only
NFC_CLKSEL : NFC Flash clock select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock divider NFC clock
#1 : 1
EXTAL clock.
End of enumeration elements list.
PLLFLLSEL : PLL/FLL clock select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCGFLLCLK
#01 : 01
MCGPLL1CLK
#10 : 10
MCGPLL2CLK
#11 : 11
Systerm platfrom clock
End of enumeration elements list.
USBF_CLKSEL : USB FS clock select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock divider USB FS clock
#1 : 1
External bypass clock (PTE26)
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 19 (1 bit)
access : read-only
TIMESRC : Ethernet timestamp clock source select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
System platform clock
#01 : 01
MCGPLLCLK/MCGFLLCLK
#10 : 10
EXTAL clock
#11 : 11
External bypass clock (PTE26)
End of enumeration elements list.
USBFSRC : USB FS clock source select
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
PLL/FLL selected by PLLFLLSEL[1:0]
#01 : 01
MCGPLL1CLK
#10 : 10
MCGPLL2CLK
#11 : 11
EXTAL clock
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
RESERVED : no description available
bits : 26 - 27 (2 bit)
access : read-only
ESDHCSRC : ESDHC perclk source select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Core/system clock
#01 : 01
MCGPLLCLK/MCGFLLCLK
#10 : 10
EXTAL clock
#11 : 11
External bypass clock (PTD11)
End of enumeration elements list.
NFCSRC : NFC Flash clock source select
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus clock.
#01 : 01
MCGPLL1CLK
#10 : 10
MCGPLL2CLK
#11 : 11
EXTAL clock
End of enumeration elements list.
System Options Register 4
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTM0FLT0 : FlexTimer 0 Fault 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT0 drives FTM 0 fault 0.
#1 : 1
CMP0 OUT drives FTM 0 fault 0.
End of enumeration elements list.
FTM0FLT1 : FlexTimer 0 Fault 1 Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT1 drives FTM 0 fault 1.
#1 : 1
CMP1 OUT drives FTM 0 fault 1.
End of enumeration elements list.
FTM0FLT2 : FlexTimer 0 Fault 2 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT2 drives FTM 0 fault 2.
#1 : 1
CMP2 OUT drives FTM 0 fault 2.
End of enumeration elements list.
FTM0FLT3 : FlexTimer 0 Fault 3 Select.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT3 drives FTM 0 fault 3.
#1 : 1
CMP0 OUT drives FTM 0 fault 3.
End of enumeration elements list.
FTM1FLT0 : FlexTimer 1 Fault 0 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1_FLT0 drives FTM 1 fault 0.
#1 : 1
CMP0 OUT drives FTM 1 fault 0.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
FTM2FLT0 : FlexTimer 2 Fault 0 Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_FLT0 drives FTM 2 fault 0.
#1 : 1
CMP0 OUT drives FTM 2 fault 0.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 11 (3 bit)
access : read-only
FTM3FLT0 : FlexTimer 3 Fault 0 Select.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_FLT0 drives FTM 2 fault 0.
#1 : 1
CMP0 OUT drives FTM 2 fault 0.
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 17 (5 bit)
access : read-only
FTM1CH0SRC : FlexTimer 1 channel 0 input capture source select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
FTM1_CH0 pin
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
FTM2CH0SRC : FlexTimer 2 channel 0 input capture source select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
FTM2_CH0 pin
#01 : 01
CMP0 output
#10 : 10
CMP1 output
#11 : 11
Reserved
End of enumeration elements list.
RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only
FTM0CLKSEL : FlexTimer 0 external clock pin select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0 external clock driven by FTM CLKIN0 pin
#1 : 1
FTM0 external clock driven by FTM CLKIN1 pin.
End of enumeration elements list.
FTM1CLKSEL : FlexTimer 1 external clock pin select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1 external clock driven by FTM CLKIN0 pin.
#1 : 1
FTM1 external clock driven by FTM CLKIN1 pin.
End of enumeration elements list.
FTM2CLKSEL : FlexTimer 2 external clock pin select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2 external clock driven by FTM CLKIN0 pin.
#1 : 1
FTM2 external clock driven by FTM CLKIN1 pin.
End of enumeration elements list.
FTM3CLKSEL : FlexTimer 3 external clock pin select
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3 external clock driven by FTM CLKIN0 pin.
#1 : 1
FTM3 external clock driven by FTM CLKIN1 pin .
End of enumeration elements list.
FTM0TRG0SRC : FlexTimer 0 hardware trigger 0 source select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP0 OUT drives FTM0 hardware trigger 0.
#1 : 1
FTM1 channel match trigger drives FTM0 hardware trigger 0.
End of enumeration elements list.
FTM0TRG1SRC : FlexTimer 0 hardware trigger 1 source select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB output trigger 1 drives FTM0 hardware trigger 1.
#1 : 1
FTM2 channel match trigger drives FTM0 hardware trigger 1.
End of enumeration elements list.
FTM3TRG0SRC : FlexTimer 3 hardware trigger 0 source select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP3 OUT drives FTM3 hardware trigger 0.
#1 : 1
FTM1 channel match trigger drives FTM3 hardware trigger 0.
End of enumeration elements list.
FTM3TRG1SRC : FlexTimer 3 hardware trigger 1 source select
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB output trigger 3 drives FTM3 hardware trigger 1.
#1 : 1
FTM2 channel match trigger drives FTM3 hardware trigger 1.
End of enumeration elements list.
System Options Register 5
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0TXSRC : UART0 transmit data source select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART0_TX pin
#01 : 01
UART0_TX pin modulated with FTM1 channel 0 output
#10 : 10
UART0_TX pin modulated with FTM2 channel 0 output
#11 : 11
Reserved
End of enumeration elements list.
UART0RXSRC : UART0 receive data source select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART0_RX pin
#01 : 01
CMP0
#10 : 10
CMP1
#11 : 11
Reserved
End of enumeration elements list.
UART1TXSRC : UART1 transmit data source select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART1_TX pin
#01 : 01
UART1_TX pin modulated with FTM1 channel 0 Output
#10 : 10
UART1_TX pin modulated with FTM2 channel 0 Output
#11 : 11
Reserved
End of enumeration elements list.
UART1RXSRC : UART1 receive data source select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
UART1_RX pin
#01 : 01
CMP0
#10 : 10
CMP1
#11 : 11
Reserved
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
System Options Register 6
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCC : MCC
bits : 0 - 15 (16 bit)
access : read-write
PCR : PCR
bits : 16 - 19 (4 bit)
access : read-write
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RSTFLTSEL : Reset pin filter select
bits : 24 - 28 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Bus clock filter count is 1
#00001 : 00001
Bus clock filter count is 2
#00010 : 00010
Bus clock filter count is 3
#00011 : 00011
Bus clock filter count is 4
#11100 : 11100
Bus clock filter count is 29
#11101 : 11101
Bus clock filter count is 30
#11110 : 11110
Bus clock filter count is 31
#11111 : 11111
Bus clock filter count is 32
End of enumeration elements list.
RSTFLTEN : Reset pin filter enable
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 000
All filtering disabled
#001 : 001
Bus clock filter enabled in normal operation. LPO clock filter enabled in stop mode.
#010 : 010
LPO clock filter enabled
#011 : 011
Bus clock filter enabled in normal operation. All filtering disabled in stop mode.
#100 : 100
LPO clock filter enabled in normal operation. All filtering disabled in stop mode.
#101 : 101
Reserved (all filtering disabled)
#110 : 110
Reserved (all filtering disabled)
#111 : 111
Reserved (all filtering disabled)
End of enumeration elements list.
System Options Register 7
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0TRGSEL : ADC0 trigger select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
External trigger
#0001 : 0001
High speed comparator 0 asynchronous interrupt
#0010 : 0010
High speed comparator 1 asynchronous interrupt
#0011 : 0011
High speed comparator 2 asynchronous interrupt
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1011 : 1011
FTM3 trigger
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer trigger
#1111 : 1111
High speed comparator 3 asynchronous interrupt
End of enumeration elements list.
ADC0PRETRGSEL : ADC0 pre-trigger select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A selected for ADC0.
#1 : 1
Pre-trigger B selected for ADC0.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 6 (2 bit)
access : read-only
ADC0ALTTRGEN : ADC0 alternate trigger enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC0.
#1 : 1
Alternate trigger selected for ADC0.
End of enumeration elements list.
ADC1TRGSEL : ADC1 trigger select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
External trigger
#0001 : 0001
High speed comparator 0 asynchronous interrupt
#0010 : 0010
High speed comparator 1 asynchronous interrupt
#0011 : 0011
High speed comparator 2 asynchronous interrupt
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1011 : 1011
FTM3 trigger
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer trigger
#1111 : 1111
High speed comparator 3 asynchronous interrupt
End of enumeration elements list.
ADC1PRETRGSEL : ADC1 pre-trigger select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A selected for ADC1.
#1 : 1
Pre-trigger B selected for ADC1.
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 14 (2 bit)
access : read-only
ADC1ALTTRGEN : ADC1 alternate trigger enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC1.
#1 : 1
Alternate trigger selected for ADC1.
End of enumeration elements list.
ADC2TRGSEL : ADC2 trigger select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
External trigger
#0001 : 0001
High speed comparator 0 asynchronous interrupt
#0010 : 0010
High speed comparator 1 asynchronous interrupt
#0011 : 0011
High speed comparator 2 asynchronous interrupt
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer trigger
#1111 : 1111
High speed comparator 3 asynchronous interrupt
End of enumeration elements list.
ADC2PRETRGSEL : ADC2 pre-trigger select
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A selected for ADC2.
#1 : 1
Pre-trigger B selected for ADC2.
End of enumeration elements list.
RESERVED : no description available
bits : 21 - 22 (2 bit)
access : read-only
ADC2ALTTRGEN : ADC2 alternate trigger enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC2.
#1 : 1
Alternate trigger selected for ADC2.
End of enumeration elements list.
ADC3TRGSEL : ADC3 trigger select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
External trigger
#0001 : 0001
High speed comparator 0 asynchronous interrupt
#0010 : 0010
High speed comparator 1 asynchronous interrupt
#0011 : 0011
High speed comparator 2 asynchronous interrupt
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1010 : 1010
FTM2 trigger
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer trigger
#1111 : 1111
High speed comparator 3 asynchronous interrupt
End of enumeration elements list.
ADC3PRETRGSEL : ADC3 pre-trigger select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A selected for ADC3.
#1 : 1
Pre-trigger B selected for ADC3.
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 30 (2 bit)
access : read-only
ADC3ALTTRGEN : ADC3 alternate trigger enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC3.
#1 : 1
Alternate trigger selected for ADC3.
End of enumeration elements list.
System Device Identification Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOID : Bondout identification number
bits : 0 - 6 (7 bit)
access : read-only
DIEID : Die identification number
bits : 7 - 9 (3 bit)
access : read-only
RESERVED : no description available
bits : 10 - 11 (2 bit)
access : read-only
REVID : Device revision number
bits : 12 - 15 (4 bit)
access : read-only
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
System Clock Gating Control Register 1
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 9 (10 bit)
access : read-only
UART4 : UART4 clock gate control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
UART5 : UART5 clock gate control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only
System Clock Gating Control Register 2
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENET1 : ENET clock gate control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 11 (11 bit)
access : read-only
DAC0 : 12BDAC0 clock gate control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DAC1 : 12BDAC1 clock gate control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 14 - 31 (18 bit)
access : read-only
System Clock Gating Control Register 3
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RNGA : RNGA clock gate control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
FLEXCAN1 : FlexCAN1 clock gate control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
NFC : NFC clock gate control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 11 (3 bit)
access : read-only
DSPI2 : DSPI2 clock gate control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 13 (1 bit)
access : read-only
DDR : DDR clock gate control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
SAI1 : SAI1 clock gate control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only
ESDHC : ESDHC clock gate control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 21 (4 bit)
access : read-only
RESERVED : no description available
bits : 22 - 22 (1 bit)
access : read-only
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only
FTM2 : FTM2 clock gate control
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
FTM3 : FTM3 clock gate control
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only
ADC1 : ADC1 clock gate control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
ADC3 : ADC3 clock gate control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only
System Clock Gating Control Register 4
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only
EWM : EWM clock gate control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
CMT : CMT clock gate control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
MCG : MCG clock gate control
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
OSC : OSC clock gate control
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
IIC2 : IIC2 clock gate control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
IIC1 : IIC1 clock gate control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 9 (2 bit)
access : read-only
UART0 : UART0 clock gate control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
UART1 : UART1 clock gate control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
UART2 : UART2 clock gate control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
UART3 : UART3 clock gate control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 14 - 17 (4 bit)
access : read-only
USBFS : USB FS clock gate control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
ANL : ANL clock gate control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
VREF : VREF clock gate control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 21 - 27 (7 bit)
access : read-only
LLWU : LLWU clock gate control
bits : 28 - 28 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PMC : PMC clock gate control
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
SMC : SMC clock gate control
bits : 30 - 30 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RCM : RCM clock gate control
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
System Clock Gating Control Register 5
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTIMER : LPTMR clock gate control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
REGFILE : REGFILE clock gate control
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DRYICE : Dryice clock gate control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DRYICESECREG : Dryice SECREG clock gate control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only
TSI : TSI clock gate control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
ATX : ATX clock gate control
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
SIMDGO : SIM DGO clock gate control
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
SIM : SIM clock gate control
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PORTA : PORTA clock gate control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PORTB : PORTB clock gate control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PORTC : PORTC clock gate control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PORTD : PORTD clock gate control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PORTE : PORTE clock gate control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PORTF : PORTF clock gate control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 17 (3 bit)
access : read-only
WDT : WDT clock gate control
bits : 18 - 18 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-only
System Clock Gating Control Register 6
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTF : FTF clock gate control
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DMAMUX0 : DMAMUX0 clock gate control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DMAMUX1 : DMAMUX1 clock gate control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
FLEXCAN0 : FlexCAN0 clock gate control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 11 (7 bit)
access : read-only
DSPI0 : DSPI0 clock gate control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DSPI1 : DSPI1 clock gate control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only
SAI0 : SAI0 clock gate control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 17 (2 bit)
access : read-only
CRC : CRC clock gate control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 19 (1 bit)
access : read-only
USB2OTG : USB2 OTG clock gate control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
USBDCD : USB DCD clock gate control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PDB : PDB clock gate control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PIT : PIT clock gate control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
FTM0 : FTM0 clock gate control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
FTM1 : FTM1 clock gate control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only
ADC0 : ADC0 clock gate control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
ADC2 : ADC2 clock gate control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RTC : RTC clock gate control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 30 - 30 (1 bit)
access : read-only
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
System Clock Gating Control Register 7
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXBUS : FlexBus controller clock gate control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
DMA : DMA controller clock gate control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
PFLEXNVM : Flash controller clock gate control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
MPU : MPU clock gate control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is disabled.
#1 : 1
Clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only
System Clock Divider Register 1
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
OUTDIV4 : Clock 4 output divider value
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV3 : Clock 3 output divider value
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV2 : Clock 2 output divider value
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV1 : Clock 1 output divider value
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
System Clock Divider Register 2
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBFSFRAC : USB FS clock divider fraction
bits : 0 - 0 (1 bit)
access : read-write
USBFSDIV : USB FS clock divider divisor
bits : 1 - 3 (3 bit)
access : read-write
RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only
USBHSFRAC : USB HS clock divider fraction
bits : 8 - 8 (1 bit)
access : read-write
USBHSDIV : USB HS clock divider divisor
bits : 9 - 11 (3 bit)
access : read-write
RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only
Flash Configuration Register 1
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTFDIS : Disable FTFE
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only
DEPART : FlexNVM partition
bits : 8 - 11 (4 bit)
access : read-only
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
EESIZE : EEPROM size
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0011 : 0011
2 KB
#0100 : 0100
1 KB
#0101 : 0101
512 Bytes
#0110 : 0110
256 Bytes
#0111 : 0111
128 Bytes
#1000 : 1000
64 Bytes
#1001 : 1001
32 Bytes
#1111 : 1111
0 Bytes
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
FSIZE : Flash size
bits : 24 - 31 (8 bit)
access : read-only
Enumeration:
#1100 : 1100
512 KB of program flash memory, 16 KB protection region
#1110 : 1110
1 MB of program flash memory, 32 KB protection region
End of enumeration elements list.
Flash Configuration Register 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
MAXADDR1 : Max address block 1
bits : 16 - 21 (6 bit)
access : read-only
RESERVED : no description available
bits : 22 - 22 (1 bit)
access : read-only
PFLSH : Program flash
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
For devices with FlexNVM: Physical flash block 1 is used as FlexNVM For devices without FlexNVM: Reserved
#1 : 1
Physical flash block 1 is used as program flash
End of enumeration elements list.
MAXADDR0 : Max address block 0
bits : 24 - 29 (6 bit)
access : read-only
RESERVED : no description available
bits : 30 - 30 (1 bit)
access : read-only
SWAPPFLSH : Swap program flash
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Swap is not active.
#1 : 1
Swap is active.
End of enumeration elements list.
Unique Identification Register High
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid-High
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid Low
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Low
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
System Clock Divider Register 4
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACEFRAC : Trace clock divider fraction
bits : 0 - 0 (1 bit)
access : read-write
TRACEDIV : Trace clock divider divisor
bits : 1 - 3 (3 bit)
access : read-write
RESERVED : no description available
bits : 4 - 23 (20 bit)
access : read-only
NFCFRAC : NFC clock divider fraction
bits : 24 - 26 (3 bit)
access : read-write
NFCDIV : NFC clock divider divisor
bits : 27 - 31 (5 bit)
access : read-write
Misc Control Register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DDRSREN : DDR self refresh enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DDR is not set to self refresh mode.
#1 : 1
DDR is set in self refresh mode. Check DDRSR to make sure DDR is in self refresh mode.
End of enumeration elements list.
DDRS : DDR Self Refresh Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
DDR is not set to self refresh mode.
#1 : 1
Sets DDR in self refresh mode.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 7 (6 bit)
access : read-only
RCRRSTEN : DDR RCR Special Reset Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No soft reset to DDR RCR
#1 : 1
Soft reset to DDR RCR
End of enumeration elements list.
RCRRST : DDR RCR Reset Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
DDR RCR is not in reset status
#1 : 1
DDR RCR is in reset status
End of enumeration elements list.
RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only
RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only
RESERVED : no description available
bits : 17 - 28 (12 bit)
access : read-only
PDBLOOP : PDB Loop Mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Provides two seperated minor loop, loop for ADC0/1 and loop for ADC2/3D
#1 : 1
Provides a loop to involve ADC0, ADC1, ADC2 and ADC3.
End of enumeration elements list.
ULPICLKOBE : 60 MHz ULPI clock output enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal generated 60MHz ULPI clock is not output to pad.
#1 : 1
Interanl generated 60MHz ULPI clock provide clock for external ULPI phy.
End of enumeration elements list.
TRACECLKDIS : Trace clock disable.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enables trace clock.
#1 : 1
Disable trace clock.
End of enumeration elements list.
SOPT1 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only
URWE : USB voltage regulator enable write enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOPT1 USBREGEN cannot be written.
#1 : 1
SOPT1 USBREGEN can be written.
End of enumeration elements list.
UVSWE : USB voltage regulator VLP standby write enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOPT1 USBVSTB cannot be written.
#1 : 1
SOPT1 USBVSTB can be written.
End of enumeration elements list.
USSWE : USB voltage regulator stop standby write enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOPT1 USBSSTB cannot be written.
#1 : 1
SOPT1 USBSSTB can be written.
End of enumeration elements list.
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
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