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DDR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x184 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR00

CR04

CR05

CR06

RCR

CR07

CR08

CR09

CR10

CR11

CR12

CR13

CR14

CR15

CR01

CR16

CR17

CR18

CR19

CR20

CR21

CR22

CR23

CR24

CR25

CR26

CR27

CR28

CR29

CR30

CR31

CR02

CR32

CR33

CR34

CR35

CR36

CR37

CR38

CR39

CR40

CR41

CR42

CR43

CR44

CR45

CR46

CR47

CR03

CR48

CR49

CR50

CR51

CR52

CR53

CR54

CR55

CR56

CR57

CR58

CR59

CR60

CR61

CR62

CR63


CR00

DDR Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR00 CR00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RESERVED DDRCLS RESERVED VERSION

START : Start
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

DDRCLS : DRAM Class
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

DDR1

#0001 : 0001

LPDDR

#0010 : 0010

DDR2

#0011 : 0011

Reserved

#1111 : 1111

Reserved

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

VERSION : Version
bits : 16 - 31 (16 bit)
access : read-only


CR04

DDR Control Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR04 CR04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBINT RESERVED TRRD RESERVED TRC RESERVED TRASMIN

TBINT : Time Burst Interrupt Interval
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : Reserved
bits : 3 - 7 (5 bit)
access : read-only

TRRD : no description available
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

TRC : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : Reserved
bits : 22 - 23 (2 bit)
access : read-only

TRASMIN : Time RAS Minimum
bits : 24 - 31 (8 bit)
access : read-write


CR05

DDR Control Register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR05 CR05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TWTR RESERVED TRP RESERVED TRTP RESERVED TMRD RESERVED

TWTR : Time Write-To-Read
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

TRP : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

TRTP : Time Read-To-Precharge
bits : 16 - 18 (3 bit)
access : read-write

RESERVED : Reserved
bits : 19 - 23 (5 bit)
access : read-only

TMRD : no description available
bits : 24 - 28 (5 bit)
access : read-write

RESERVED : Reserved
bits : 29 - 31 (3 bit)
access : read-only


CR06

DDR Control Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR06 CR06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMOD TRASMAX INTWBR RESERVED

TMOD : Time Mode
bits : 0 - 7 (8 bit)
access : read-write

TRASMAX : Time Row Access Maximum
bits : 8 - 23 (16 bit)
access : read-write

INTWBR : Interrupt Write Burst
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Read commands cannot interrupt write commands

#1 : 1

Read commands can interrupt write commands

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


RCR

RCR Control Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RST RESERVED

RESERVED : no description available
bits : 0 - 29 (30 bit)
access : read-only

RST : Reset
bits : 30 - 30 (1 bit)
access : write-only

Enumeration:

#0 : 0

No software reset

#1 : 1

Force software reset

End of enumeration elements list.

RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only


CR07

DDR Control Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR07 CR07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKPW RESERVED TCKESR RESERVED AP RESERVED CCAPEN RESERVED

CLKPW : Clock Pulse Width
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : Reserved
bits : 3 - 7 (5 bit)
access : read-only

TCKESR : Time Clock low Self Refresh
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : Reserved
bits : 13 - 15 (3 bit)
access : read-only

AP : Auto Precharge
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

CCAPEN : Concurrent Auto-Precharge Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-write


CR08

DDR Control Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR08 CR08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRAS RESERVED TRASDI TWR RESERVED TDAL RESERVED

TRAS : Time RAS lockout
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

TRASDI : Time RAS-to-CAS Delay Interval
bits : 8 - 15 (8 bit)
access : read-write

TWR : Time Write Recovery
bits : 16 - 20 (5 bit)
access : read-write

RESERVED : Reserved
bits : 21 - 23 (3 bit)
access : read-only

TDAL : no description available
bits : 24 - 28 (5 bit)
access : read-write

RESERVED : Reserved
bits : 29 - 31 (3 bit)
access : read-only


CR09

DDR Control Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR09 CR09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDLL NOCMD RESERVED BSTLEN RESERVED

TDLL : Time DLL
bits : 0 - 15 (16 bit)
access : read-write

NOCMD : No Command
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Issue only REF and PRE commands during DLL initialization of the DRAM devices. If PRE commands are issued before DLL initialization is complete, the command is executed immediately and the DLL initialization continues.

#1 : 1

Do not issue any type of command during DLL initialization of the DRAM devices. If any other commands are issued, they are held until DLL initialization completes.

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

BSTLEN : Burst Length
bits : 24 - 26 (3 bit)
access : read-write

RESERVED : Reserved
bits : 27 - 31 (5 bit)
access : read-only


CR10

DDR Control Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR10 CR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFAW RESERVED TCPD TRPAB RESERVED

TFAW : Time FAW
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : Reserved
bits : 6 - 7 (2 bit)
access : read-only

TCPD : Time Clock Enable to Precharge Delay
bits : 8 - 23 (16 bit)
access : read-write

TRPAB : TRP All Bank
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR11

DDR Control Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR11 CR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGDIMM RESERVED AREF RESERVED AREFMODE RESERVED TREFEN RESERVED

REGDIMM : Registered DIMM
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

AREF : Auto Refresh
bits : 8 - 8 (1 bit)
access : write-only

RESERVED : Reserved
bits : 9 - 15 (7 bit)
access : read-only

AREFMODE : Auto Refresh Mode
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

TREFEN : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR12

DDR Control Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR12 CR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRFC RESERVED TREF RESERVED

TRFC : Time Refresh Command
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : Reserved
bits : 10 - 15 (6 bit)
access : read-only

TREF : Time Refresh
bits : 16 - 29 (14 bit)
access : read-write

RESERVED : Reserved
bits : 30 - 31 (2 bit)
access : read-only


CR13

DDR Control Register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR13 CR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TREFINT RESERVED PD RESERVED

TREFINT : Reserved
bits : 0 - 13 (14 bit)
access : read-write

RESERVED : Reserved
bits : 14 - 15 (2 bit)
access : read-only

PD : Power Down
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable full power state

#1 : 1

The memory controller completes processing of the current burst for the current transaction (if any), issues a precharge all command, and disables the clock enable signal to the DRAM devices. Any subsequent commands in the command queue are suspended until this bit is cleared.

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 31 (15 bit)
access : read-only


CR14

DDR Control Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR14 CR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPDEX TXSR

TPDEX : Time Power Down Exit
bits : 0 - 15 (16 bit)
access : read-only

TXSR : Time Exit Self Refresh
bits : 16 - 31 (16 bit)
access : read-only


CR15

DDR Control Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR15 CR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSNR SREF RESERVED PUREF RESERVED

TXSNR : TXSNR parameter
bits : 0 - 15 (16 bit)
access : read-write

SREF : Self Refresh
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

PUREF : Power Up Refresh
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR01

DDR Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR01 CR01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXROW RESERVED MAXCOL RESERVED CSMAX RESERVED

MAXROW : Maxmum Row
bits : 0 - 4 (5 bit)
access : read-only

RESERVED : Reserved
bits : 5 - 7 (3 bit)
access : read-only

MAXCOL : Maximum Column
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

0

#0001 : 0001

1

#1011 : 1011

11

#1100 : 1100

Reserved

#1101 : 1101

Reserved

#1110 : 1110

Reserved

#1111 : 1111

Reserved

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

CSMAX : Chip Select Maximum
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

#00 : 00

Zero

#01 : 01

One

#10 : 10

Two

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : Reserved
bits : 18 - 31 (14 bit)
access : read-only


CR16

DDR Control Register 16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR16 CR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QKREF RESERVED CLKDLY RESERVED LPCTRL RESERVED

QKREF : Quick Refresh
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Continue memory initialization

#1 : 1

Interrupt memory initialization and enter self-refresh mode

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

CLKDLY : Clock Delay
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

LPCTRL : Low Power Control
bits : 16 - 20 (5 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 21 - 31 (11 bit)
access : read-only


CR17

DDR Control Register 17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR17 CR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPPDCNT LPRFCNT

LPPDCNT : Low Power Power Down Count
bits : 0 - 15 (16 bit)
access : read-write

LPRFCNT : Low Power Refresh Count
bits : 16 - 31 (16 bit)
access : read-write


CR18

DDR Control Register 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR18 CR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPEXTCNT LPAUTO RESERVED

LPEXTCNT : Low Power External Count
bits : 0 - 15 (16 bit)
access : read-write

LPAUTO : Low Power Auto
bits : 16 - 20 (5 bit)
access : read-write

RESERVED : Reserved
bits : 21 - 31 (11 bit)
access : read-only


CR19

DDR Control Register 19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR19 CR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPINTCNT LPRFHOLD

LPINTCNT : Low Power Interval Count
bits : 0 - 15 (16 bit)
access : read-write

LPRFHOLD : Low Power Refresh Hold
bits : 16 - 31 (16 bit)
access : read-write


CR20

DDR Control Register 20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR20 CR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPRE RESERVED CKSRE RESERVED CKSRX RESERVED WRMD RESERVED

LPRE : Low Power Refresh enable
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Refreshes occur

#01 : 01

Refreshes do not occur

#10 : 10

Reserved

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 7 (6 bit)
access : read-only

CKSRE : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

CKSRX : Clock Self Refresh Exit
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

WRMD : Write Mode Register
bits : 24 - 24 (1 bit)
access : write-only

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR21

DDR Control Register 21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR21 CR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0DAT0 MR1DAT0

MR0DAT0 : no description available
bits : 0 - 15 (16 bit)
access : read-write

MR1DAT0 : no description available
bits : 16 - 31 (16 bit)
access : read-write


CR22

DDR Control Register 22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR22 CR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR2DATA0 MR3DAT0

MR2DATA0 : no description available
bits : 0 - 15 (16 bit)
access : read-write

MR3DAT0 : no description available
bits : 16 - 31 (16 bit)
access : read-write


CR23

DDR Control Register 23
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR23 CR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR24

DDR Control Register 24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR24 CR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


CR25

DDR Control Register 25
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR25 CR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BNK8 RESERVED ADDPINS RESERVED COLSIZ RESERVED APREBIT RESERVED

BNK8 : Eight Bank Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 banks

#1 : 1

8 banks

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

ADDPINS : Address Pins
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

COLSIZ : Column Size
bits : 16 - 18 (3 bit)
access : read-write

RESERVED : Reserved
bits : 19 - 23 (5 bit)
access : read-only

APREBIT : Auto Precharge Bit
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR26

DDR Control Register 26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR26 CR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGECNT CMDAGE ADDCOL RESERVED BNKSPT RESERVED

AGECNT : Age Count
bits : 0 - 7 (8 bit)
access : read-write

CMDAGE : Command Age count
bits : 8 - 15 (8 bit)
access : read-write

ADDCOL : Address Collision enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

BNKSPT : Bank Split enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR27

DDR Control Register 27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR27 CR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLEN RESERVED PRIEN RESERVED RWEN RESERVED SWPEN RESERVED

PLEN : Placement Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled. The command queue is a straight FIFO.

#1 : 1

Enabled. The command queue is filled according to the placement logic factors.

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

PRIEN : Priority Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 15 (7 bit)
access : read-only

RWEN : Read Write same Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

SWPEN : Swap Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR28

DDR Control Register 28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR28 CR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSMAP RESERVED REDUC RESERVED BIGEND RESERVED CMDLATR RESERVED

CSMAP : Chip Select Map
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

REDUC : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

16-bit - standard operation using full memory bus

#1 : 1

8-bit - Memory datapath width is half of the maximum size. The upper half of the memory busses (DQ, DQS, and DM) are unused and relevant data only exists in the lower half of the busses.

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 15 (7 bit)
access : read-only

BIGEND : Big Endian Enable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Little endian

#1 : 1

Big endian

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

CMDLATR : Command Latency Reduction Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR29

DDR Control Register 29
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR29 CR29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRLATR RESERVED FSTWR RESERVED QFULL RESERVED RESYNC RESERVED

WRLATR : Write Latency Reduction enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

FSTWR : Fast Write
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The memory controller issues a write command to the DRAM devices when it has received enough data for one DRAM burst. Write data can be sent in any cycle relative to the write command. This mode also allows for multi-word write command data to arrive in non-sequential cycles.

#1 : 1

The memory controller issues a write command to the DRAM devices after the first word of the write data is received by the memory controller. The first word can be sent at any time relative to the write command. In this mode, multi-word write command data must be available to the memory controller in sequential cycles.

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 15 (7 bit)
access : read-only

QFULL : Queue Fullness
bits : 16 - 17 (2 bit)
access : read-write

RESERVED : Reserved
bits : 18 - 23 (6 bit)
access : read-only

RESYNC : Resyncronize
bits : 24 - 24 (1 bit)
access : write-only

Enumeration:

#0 : 0

No effect

#1 : 1

Initiate

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR30

DDR Control Register 30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR30 CR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSYNCRF RESERVED INTSTAT RESERVED INTACK

RSYNCRF : Resynchroize after Refresh
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

INTSTAT : Interrupt Status
bits : 8 - 16 (9 bit)
access : read-only

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

INTACK : Interupt Acknowlege
bits : 24 - 31 (8 bit)
access : write-only

Enumeration:

#0 : 0

No effect

#1 : 1

Clear the corresponding bit in INTSTATUS

End of enumeration elements list.


CR31

DDR Control Register 31
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR31 CR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTMASK RESERVED

INTMASK : Interrupt Mask
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

#0 : 0

No mask

#1 : 1

Mask corresponding interrupt signal

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 31 (23 bit)
access : read-only


CR02

DDR Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR02 CR02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TINIT INITAREF RESERVED

TINIT : Time Initialization
bits : 0 - 23 (24 bit)
access : read-write

INITAREF : Initialization Auto-Refresh
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR32

DDR Control Register 32
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR32 CR32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OORAD

OORAD : Out Of Range Address
bits : 0 - 31 (32 bit)
access : read-only


CR33

DDR Control Register 33
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR33 CR33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OORLEN RESERVED OORTYP RESERVED OORID RESERVED

OORLEN : Out Of Range Length
bits : 0 - 9 (10 bit)
access : read-only

RESERVED : Reserved
bits : 10 - 15 (6 bit)
access : read-only

OORTYP : Out Of Range Type
bits : 16 - 21 (6 bit)
access : read-only

RESERVED : Reserved
bits : 22 - 23 (2 bit)
access : read-only

OORID : Out Of Range source ID
bits : 24 - 25 (2 bit)
access : read-only

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


CR34

DDR Control Register 34
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR34 CR34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODTRDC RESERVED ODTWRCS RESERVED RESERVED RESERVED RESERVED RESERVED

ODTRDC : ODT Read map CS
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : Reserved
bits : 1 - 7 (7 bit)
access : read-only

ODTWRCS : ODT Write map CS
bits : 8 - 8 (1 bit)
access : read-write

RESERVED : Reserved
bits : 9 - 15 (7 bit)
access : read-only

RESERVED : Reserved
bits : 16 - 17 (2 bit)
access : read-only

RESERVED : Reserved
bits : 18 - 23 (6 bit)
access : read-only

RESERVED : Reserved
bits : 24 - 25 (2 bit)
access : read-only

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


CR35

DDR Control Register 35
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR35 CR35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2WSMCS RESERVED W2RSMCS RESERVED

R2WSMCS : Read To Write Same Chip Select
bits : 0 - 3 (4 bit)
access : read-only

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

W2RSMCS : Write To Read Same Chip Select
bits : 8 - 11 (4 bit)
access : read-only

RESERVED : Reserved
bits : 12 - 31 (20 bit)
access : read-only


CR36

DDR Control Register 36
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR36 CR36 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR37

DDR Control Register 37
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR37 CR37 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2RSAME RESERVED R2WSAME RESERVED W2RSAME RESERVED W2WSAME RESERVED

R2RSAME : R2R Same chip select delay
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : Reserved
bits : 3 - 7 (5 bit)
access : read-only

R2WSAME : R2W Same chip select delay
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

W2RSAME : W2R Same chip select delay
bits : 16 - 18 (3 bit)
access : read-write

RESERVED : Reserved
bits : 19 - 23 (5 bit)
access : read-only

W2WSAME : W2W Same chip select delay
bits : 24 - 26 (3 bit)
access : read-write

RESERVED : Reserved
bits : 27 - 31 (5 bit)
access : read-only


CR38

DDR Control Register 38
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR38 CR38 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDNCS RESERVED PUPCS RESERVED PWRCNT RESERVED

PDNCS : OCD Pull Down adjustment Chip Select
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : Reserved
bits : 5 - 7 (3 bit)
access : read-only

PUPCS : OCD Pull Up adjustment Chip Select
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : Reserved
bits : 13 - 15 (3 bit)
access : read-only

PWRCNT : Port 0 Write Count
bits : 16 - 26 (11 bit)
access : read-write

RESERVED : Reserved
bits : 27 - 31 (5 bit)
access : read-only


CR39

DDR Control Register 39
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR39 CR39 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0RDCNT RESERVED RP0 RESERVED WP0 RESERVED

P0RDCNT : Port 0 Read command Count
bits : 0 - 10 (11 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

RP0 : Port 0 Read command Priority
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest

End of enumeration elements list.

RESERVED : Reserved
bits : 18 - 23 (6 bit)
access : read-only

WP0 : Port 0 Write command Priority
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


CR40

DDR Control Register 40
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR40 CR40 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0TYP RESERVED P1WRCNT RESERVED

P0TYP : Port 0 Type
bits : 0 - 1 (2 bit)
access : read-write

RESERVED : Reserved
bits : 2 - 7 (6 bit)
access : read-only

P1WRCNT : Port 1 Write command Count
bits : 8 - 18 (11 bit)
access : read-write

RESERVED : Reserved
bits : 19 - 31 (13 bit)
access : read-only


CR41

DDR Control Register 41
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR41 CR41 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1RDCNT RESERVED RP1 RESERVED WP1 RESERVED

P1RDCNT : Port 1 Read command Count
bits : 0 - 10 (11 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

RP1 : Read command priority Port 1
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest

End of enumeration elements list.

RESERVED : Reserved
bits : 18 - 23 (6 bit)
access : read-only

WP1 : Write command priority Port 1
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


CR42

DDR Control Register 42
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR42 CR42 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1TYP RESERVED P2WRCNT RESERVED

P1TYP : Port 1 Type
bits : 0 - 1 (2 bit)
access : read-write

RESERVED : Reserved
bits : 2 - 7 (6 bit)
access : read-only

P2WRCNT : Port 2 Write command Count
bits : 8 - 18 (11 bit)
access : read-write

RESERVED : Reserved
bits : 19 - 31 (13 bit)
access : read-only


CR43

DDR Control Register 43
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR43 CR43 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2RDCNT RESERVED RP2 RESERVED WP2 RESERVED

P2RDCNT : Port 2 Read command Count
bits : 0 - 10 (11 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

RP2 : Read command priority Port 2
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest

End of enumeration elements list.

RESERVED : Reserved
bits : 18 - 23 (6 bit)
access : read-only

WP2 : Write command priority Port 2
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


CR44

DDR Control Register 44
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR44 CR44 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2TYP RESERVED WRRLAT RESERVED WRRSHARE RESERVED WRRERR RESERVED

P2TYP : Port 2 Type
bits : 0 - 1 (2 bit)
access : read-write

RESERVED : Reserved
bits : 2 - 7 (6 bit)
access : read-only

WRRLAT : WRR Latency
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Free-running

#1 : 1

Limited

End of enumeration elements list.

RESERVED : Reserved
bits : 9 - 15 (7 bit)
access : read-only

WRRSHARE : WRR Shared arbitration
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port 0 and port 1 are treated independently for arbitration

#1 : 1

Port 0 and port 1 are grouped together for arbitration

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 23 (7 bit)
access : read-only

WRRERR : WRR parameters Error
bits : 24 - 27 (4 bit)
access : read-only

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR45

DDR Control Register 45
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR45 CR45 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0PRI0 RESERVED P0PRI1 RESERVED P0PRI2 RESERVED P0PRI3 RESERVED

P0PRI0 : Port 0 Priority 0 commands
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

P0PRI1 : Port 0 Priority 1 commands
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

P0PRI2 : Port 0 Priority 2 commands
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

P0PRI3 : Port 0 Priority 3 commands
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR46

DDR Control Register 46
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR46 CR46 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0ORD RESERVED P0PRIRLX RESERVED P1PRI0 RESERVED

P0ORD : Port 0 Order
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest listing in the scan order

#01 : 01

------

#10 : 10

------

#11 : 11

Lowest listing in the scan order

End of enumeration elements list.

RESERVED : Reserved
bits : 2 - 7 (6 bit)
access : read-only

P0PRIRLX : Port 0 Priority Relax
bits : 8 - 17 (10 bit)
access : read-write

RESERVED : Reserved
bits : 18 - 23 (6 bit)
access : read-only

P1PRI0 : Port 1 Priority 0 commands
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR47

DDR Control Register 47
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR47 CR47 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1PRI1 RESERVED P1PRI2 RESERVED P1PRI3 RESERVED P1ORD RESERVED

P1PRI1 : Port 1 Priority 1 commands
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

P1PRI2 : Port 1 Priority 2 commands
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

P1PRI3 : Port 1 Priority 3 commands
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

P1ORD : Port 1 Order
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest listing in the scan order

#11 : 11

Lowest listing in the scan order

End of enumeration elements list.

RESERVED : Reserved
bits : 26 - 31 (6 bit)
access : read-only


CR03

DDR Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR03 CR03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATLIN RESERVED LATGATE RESERVED WRLAT RESERVED TCCD RESERVED

LATLIN : Latency Linear
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Reserved

#0001 : 0001

Reserved

#0010 : 0010

1 cycle

#0011 : 0011

1.5 cycles

#1111 : 1111

7.5 cycles

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

LATGATE : Latency Gate
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

WRLAT : Write Latency
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

TCCD : Time CAS-to-CAS Delay
bits : 24 - 28 (5 bit)
access : read-write

RESERVED : Reserved
bits : 29 - 31 (3 bit)
access : read-only


CR48

DDR Control Register 48
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR48 CR48 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P1PRIRLX RESERVED P2PRI0 RESERVED P2PRI1 RESERVED

P1PRIRLX : Port 1 Priority Relax
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : Reserved
bits : 10 - 15 (6 bit)
access : read-only

P2PRI0 : Port 2 Priority 0 commands
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

P2PRI1 : Port 2 Priority 1 commands
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR49

DDR Control Register 49
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR49 CR49 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2PRI2 RESERVED P2PRI3 RESERVED P2ORD RESERVED

P2PRI2 : Port 2 Priority 2 commands
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

P2PRI3 : Port 2 Priority 3 commands
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Lowest

#0001 : 0001

-----

#1110 : 1110

-----

#1111 : 1111

Highest

End of enumeration elements list.

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

P2ORD : Port 2 Order
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Highest listing in the scan order

#01 : 01

-----

#10 : 10

-----

#11 : 11

Lowest listing in the scan order

End of enumeration elements list.

RESERVED : Reserved
bits : 18 - 31 (14 bit)
access : read-only


CR50

DDR Control Register 50
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR50 CR50 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P2PRIRLX RESERVED CLKSTATUS RESERVED

P2PRIRLX : Port 2 Priority Relax
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : Reserved
bits : 10 - 15 (6 bit)
access : read-only

CLKSTATUS : Clock Status
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

RESERVED : Reserved
bits : 17 - 31 (15 bit)
access : read-only


CR51

DDR Control Register 51
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR51 CR51 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLLRSTDLY DLLRADLY PHYWRLAT RESERVED

DLLRSTDLY : DLL Reset Delay
bits : 0 - 15 (16 bit)
access : read-write

DLLRADLY : DLL Reset Adjust Delay
bits : 16 - 23 (8 bit)
access : read-write

PHYWRLAT : PHY Write Latency
bits : 24 - 27 (4 bit)
access : read-only

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR52

DDR Control Register 52
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR52 CR52 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PYWRLTBS RESERVED PHYRDLAT RESERVED RDDATAEN RESERVED RDDTENBAS RESERVED

PYWRLTBS : PHY Write Latency Base
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

PHYRDLAT : PHY Read Latency
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

RDDATAEN : Read Data Enable
bits : 16 - 19 (4 bit)
access : read-only

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

RDDTENBAS : Read Data Enable Base
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR53

DDR Control Register 53
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR53 CR53 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKDISCS RESERVED RESERVED CRTLUPDMN RESERVED CTRLUPDMX RESERVED

CLKDISCS : DRAM Clock Disable for chip select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Memory clock active

#1 : 1

Memory clock disabled

End of enumeration elements list.

RESERVED : Reserved
bits : 1 - 1 (1 bit)
access : read-only

RESERVED : Reserved
bits : 2 - 7 (6 bit)
access : read-only

CRTLUPDMN : DFI CRTLUPD Minimum
bits : 8 - 11 (4 bit)
access : read-only

RESERVED : Reserved
bits : 12 - 15 (4 bit)
access : read-only

CTRLUPDMX : DFI CRTLUPD Minimum
bits : 16 - 29 (14 bit)
access : read-write

RESERVED : Reserved
bits : 30 - 31 (2 bit)
access : read-only


CR54

DDR Control Register 54
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR54 CR54 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYUPDTY0 RESERVED PHYUPDTY1 RESERVED

PHYUPDTY0 : DFI PHYUPD Type 0
bits : 0 - 13 (14 bit)
access : read-write

RESERVED : Reserved
bits : 14 - 15 (2 bit)
access : read-only

PHYUPDTY1 : DFI PHYUPD Type 1
bits : 16 - 29 (14 bit)
access : read-write

RESERVED : Reserved
bits : 30 - 31 (2 bit)
access : read-only


CR55

DDR Control Register 55
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR55 CR55 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYUPDTY2 RESERVED PHYUPDTY3 RESERVED

PHYUPDTY2 : DFI PHYUPD TYPE2
bits : 0 - 13 (14 bit)
access : read-write

RESERVED : Reserved
bits : 14 - 15 (2 bit)
access : read-only

PHYUPDTY3 : DFI PHYUPD TYPE3
bits : 16 - 29 (14 bit)
access : read-write

RESERVED : Reserved
bits : 30 - 31 (2 bit)
access : read-only


CR56

DDR Control Register 56
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR56 CR56 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYUPDRESP RESERVED RDLATADJ RESERVED WRLATADJ RESERVED

PHYUPDRESP : TDFI PHYUPDRESP parameter
bits : 0 - 13 (14 bit)
access : read-write

RESERVED : Reserved
bits : 14 - 15 (2 bit)
access : read-only

RDLATADJ : Read Latency Adjust
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

WRLATADJ : Write Latency Adjust
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : Reserved
bits : 28 - 31 (4 bit)
access : read-only


CR57

DDR Control Register 57
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR57 CR57 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMDDLY RESERVED CLKDISDLY RESERVED CLKENDLY RESERVED ODTALTEN RESERVED

CMDDLY : Command Delay
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : Reserved
bits : 4 - 7 (4 bit)
access : read-only

CLKDISDLY : DFI Clock Disable Delay
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : Reserved
bits : 11 - 15 (5 bit)
access : read-only

CLKENDLY : DFI Clock Enable Delay
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : Reserved
bits : 20 - 23 (4 bit)
access : read-only

ODTALTEN : ODT Alternate Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : Reserved
bits : 25 - 31 (7 bit)
access : read-only


CR58

DDR Control Register 58
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR58 CR58 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR59

DDR Control Register 59
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR59 CR59 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR60

DDR Control Register 60
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR60 CR60 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR61

DDR Control Register 61
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR61 CR61 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR62

DDR Control Register 62
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR62 CR62 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only


CR63

DDR Control Register 63
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR63 CR63 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Not_Used NOT_USED

Not_Used : Reserved
bits : 0 - 15 (16 bit)
access : read-only

NOT_USED : Reserved
bits : 16 - 31 (16 bit)
access : read-only



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