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RNG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

SR

ER

OR


CR

RNGA Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GO HA INTM CLRI SLP RESERVED

GO : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RNGA Output Register is not loaded with random data.

#1 : 1

RNGA Output Register is loaded with random data.

End of enumeration elements list.

HA : High Assurance
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Notification of security violations is masked.

#1 : 1

Notification of security violations is enabled.

End of enumeration elements list.

INTM : Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is enabled.

#1 : 1

Interrupt is masked.

End of enumeration elements list.

CLRI : Clear Interrupt
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

#0 : 0

Do not clear the interrupt.

#1 : 1

Clear the interrupt.

End of enumeration elements list.

SLP : Sleep
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

RNGA is not in Sleep mode.

#1 : 1

RNGA is in Sleep mode.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only


SR

RNGA Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECV LRS ORU ERRI SLP RESERVED OREG_LVL OREG_SIZE RESERVED

SECV : Security Violation
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No security violations have occured or CR[HA] is not set.

#1 : 1

A security violation has occurred.

End of enumeration elements list.

LRS : Last Read Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Last read was performed while the RNGA Output Register was not empty.

#1 : 1

Last read was performed while the RNGA Output Register was empty (underflow condition).

End of enumeration elements list.

ORU : Output Register Underflow
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

The RNGA Output Register has not been read while empty since last read of the RNGA Status Register.

#1 : 1

The RNGA Output Register has been read while empty since last read of the RNGA Status Register.

End of enumeration elements list.

ERRI : Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

The RNGA Output Register has not been read while empty.

#1 : 1

The RNGA Output Register has been read while empty.

End of enumeration elements list.

SLP : Sleep
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

The RNGA is not in Sleep mode.

#1 : 1

The RNGA is in Sleep mode.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

OREG_LVL : Output Register Level
bits : 8 - 15 (8 bit)
access : read-only

OREG_SIZE : Output Register Size
bits : 16 - 23 (8 bit)
access : read-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


ER

RNGA Entropy Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ER ER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXT_ENT

EXT_ENT : External Entropy
bits : 0 - 31 (32 bit)
access : write-only


OR

RNGA Output Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OR OR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RANDOUT

RANDOUT : Random Output
bits : 0 - 31 (32 bit)
access : read-only



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