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MPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x820 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CESR

RGDAAC0

RGD2_WORD0

RGD2_WORD1

RGD2_WORD2

RGD2_WORD3

RGD3_WORD0

RGD3_WORD1

RGD3_WORD2

RGD3_WORD3

RGDAAC1

RGD4_WORD0

RGD4_WORD1

RGD4_WORD2

RGD4_WORD3

RGD5_WORD0

RGD5_WORD1

RGD5_WORD2

RGD5_WORD3

EAR0

RGDAAC2

RGD6_WORD0

RGD6_WORD1

RGD6_WORD2

RGD6_WORD3

RGD7_WORD0

RGD7_WORD1

RGD7_WORD2

RGD7_WORD3

EDR0

RGDAAC3

RGDAAC4

EAR1

RGDAAC5

RGDAAC6

EDR1

RGDAAC7

RGD0_WORD0

RGD0_WORD1

RGD0_WORD2

RGD0_WORD3

RGD1_WORD0

RGD1_WORD1

RGD1_WORD2

RGD1_WORD3


CESR

Control/Error Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CESR CESR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED NRGD NSP HRL RESERVED RESERVED RESERVED SPERR

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

MPU is disabled. All accesses from all bus masters are allowed.

#1 : 1

MPU is enabled

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

NRGD : Number Of Region Descriptors
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

8 region descriptors

#0001 : 0001

12 region descriptors

#0010 : 0010

16 region descriptors

End of enumeration elements list.

NSP : Number Of Slave Ports
bits : 12 - 15 (4 bit)
access : read-only

HRL : Hardware Revision Level
bits : 16 - 19 (4 bit)
access : read-only

RESERVED : no description available
bits : 20 - 22 (3 bit)
access : read-only

RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : no description available
bits : 24 - 29 (6 bit)
access : read-only

SPERR : Slave Port n Error
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#0 : 0

No error has occurred for slave port n.

#1 : 1

An error has occurred for slave port n.

End of enumeration elements list.


RGDAAC0

Region Descriptor Alternate Access Control n
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC0 RGDAAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD2_WORD0

Region Descriptor n, Word 0
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD2_WORD0 RGD2_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD2_WORD1

Region Descriptor n, Word 1
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD2_WORD1 RGD2_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD2_WORD2

Region Descriptor n, Word 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD2_WORD2 RGD2_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD2_WORD3

Region Descriptor n, Word 3
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD2_WORD3 RGD2_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


RGD3_WORD0

Region Descriptor n, Word 0
address_offset : 0x1460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD3_WORD0 RGD3_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD3_WORD1

Region Descriptor n, Word 1
address_offset : 0x1474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD3_WORD1 RGD3_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD3_WORD2

Region Descriptor n, Word 2
address_offset : 0x1488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD3_WORD2 RGD3_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD3_WORD3

Region Descriptor n, Word 3
address_offset : 0x149C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD3_WORD3 RGD3_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


RGDAAC1

Region Descriptor Alternate Access Control n
address_offset : 0x1804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC1 RGDAAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD4_WORD0

Region Descriptor n, Word 0
address_offset : 0x18A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD4_WORD0 RGD4_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD4_WORD1

Region Descriptor n, Word 1
address_offset : 0x18B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD4_WORD1 RGD4_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD4_WORD2

Region Descriptor n, Word 2
address_offset : 0x18D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD4_WORD2 RGD4_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD4_WORD3

Region Descriptor n, Word 3
address_offset : 0x18E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD4_WORD3 RGD4_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


RGD5_WORD0

Region Descriptor n, Word 0
address_offset : 0x1CF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD5_WORD0 RGD5_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD5_WORD1

Region Descriptor n, Word 1
address_offset : 0x1D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD5_WORD1 RGD5_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD5_WORD2

Region Descriptor n, Word 2
address_offset : 0x1D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD5_WORD2 RGD5_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD5_WORD3

Region Descriptor n, Word 3
address_offset : 0x1D44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD5_WORD3 RGD5_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


EAR0

Error Address Register, slave port n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EAR0 EAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EADDR

EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only


RGDAAC2

Region Descriptor Alternate Access Control n
address_offset : 0x200C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC2 RGDAAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD6_WORD0

Region Descriptor n, Word 0
address_offset : 0x2150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD6_WORD0 RGD6_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD6_WORD1

Region Descriptor n, Word 1
address_offset : 0x2170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD6_WORD1 RGD6_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD6_WORD2

Region Descriptor n, Word 2
address_offset : 0x2190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD6_WORD2 RGD6_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD6_WORD3

Region Descriptor n, Word 3
address_offset : 0x21B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD6_WORD3 RGD6_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


RGD7_WORD0

Region Descriptor n, Word 0
address_offset : 0x25C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD7_WORD0 RGD7_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD7_WORD1

Region Descriptor n, Word 1
address_offset : 0x25E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD7_WORD1 RGD7_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD7_WORD2

Region Descriptor n, Word 2
address_offset : 0x2608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD7_WORD2 RGD7_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD7_WORD3

Region Descriptor n, Word 3
address_offset : 0x262C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD7_WORD3 RGD7_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


EDR0

Error Detail Register, slave port n
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EDR0 EDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERW EATTR EMN EPID EACD

ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Read

#1 : 1

Write

End of enumeration elements list.

EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only

Enumeration:

#000 : 000

User mode, instruction access

#001 : 001

User mode, data access

#010 : 010

Supervisor mode, instruction access

#011 : 011

Supervisor mode, data access

End of enumeration elements list.

EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only

EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only

EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only


RGDAAC3

Region Descriptor Alternate Access Control n
address_offset : 0x2818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC3 RGDAAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGDAAC4

Region Descriptor Alternate Access Control n
address_offset : 0x3028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC4 RGDAAC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


EAR1

Error Address Register, slave port n
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EAR1 EAR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EADDR

EADDR : Error Address
bits : 0 - 31 (32 bit)
access : read-only


RGDAAC5

Region Descriptor Alternate Access Control n
address_offset : 0x383C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC5 RGDAAC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGDAAC6

Region Descriptor Alternate Access Control n
address_offset : 0x4054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC6 RGDAAC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


EDR1

Error Detail Register, slave port n
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EDR1 EDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERW EATTR EMN EPID EACD

ERW : Error Read/Write
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Read

#1 : 1

Write

End of enumeration elements list.

EATTR : Error Attributes
bits : 1 - 3 (3 bit)
access : read-only

Enumeration:

#000 : 000

User mode, instruction access

#001 : 001

User mode, data access

#010 : 010

Supervisor mode, instruction access

#011 : 011

Supervisor mode, data access

End of enumeration elements list.

EMN : Error Master Number
bits : 4 - 7 (4 bit)
access : read-only

EPID : Error Process Identification
bits : 8 - 15 (8 bit)
access : read-only

EACD : Error Access Control Detail
bits : 16 - 31 (16 bit)
access : read-only


RGDAAC7

Region Descriptor Alternate Access Control n
address_offset : 0x4870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGDAAC7 RGDAAC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier Enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier Enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access Control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD0_WORD0

Region Descriptor n, Word 0
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD0_WORD0 RGD0_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD0_WORD1

Region Descriptor n, Word 1
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD0_WORD1 RGD0_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD0_WORD2

Region Descriptor n, Word 2
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD0_WORD2 RGD0_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD0_WORD3

Region Descriptor n, Word 3
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD0_WORD3 RGD0_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write


RGD1_WORD0

Region Descriptor n, Word 0
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD1_WORD0 RGD1_WORD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SRTADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

SRTADDR : Start Address
bits : 5 - 31 (27 bit)
access : read-write


RGD1_WORD1

Region Descriptor n, Word 1
address_offset : 0xC1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD1_WORD1 RGD1_WORD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ENDADDR

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ENDADDR : End Address
bits : 5 - 31 (27 bit)
access : read-write


RGD1_WORD2

Region Descriptor n, Word 2
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD1_WORD2 RGD1_WORD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0UM M0SM M0PE M1UM M1SM M1PE M2UM M2SM M2PE M3UM M3SM M3PE M4WE M4RE M5WE M5RE M6WE M6RE M7WE M7RE

M0UM : Bus Master 0 User Mode Access Control
bits : 0 - 2 (3 bit)
access : read-write

M0SM : Bus Master 0 Supervisor Mode Access Control
bits : 3 - 4 (2 bit)
access : read-write

M0PE : Bus Master 0 Process Identifier enable
bits : 5 - 5 (1 bit)
access : read-write

M1UM : Bus Master 1 User Mode Access Control
bits : 6 - 8 (3 bit)
access : read-write

M1SM : Bus Master 1 Supervisor Mode Access Control
bits : 9 - 10 (2 bit)
access : read-write

M1PE : Bus Master 1 Process Identifier enable
bits : 11 - 11 (1 bit)
access : read-write

M2UM : Bus Master 2 User Mode Access control
bits : 12 - 14 (3 bit)
access : read-write

M2SM : Bus Master 2 Supervisor Mode Access Control
bits : 15 - 16 (2 bit)
access : read-write

M2PE : Bus Master 2 Process Identifier Enable
bits : 17 - 17 (1 bit)
access : read-write

M3UM : Bus Master 3 User Mode Access Control
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0 : 0

An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.

#1 : 1

Allows the given access type to occur

End of enumeration elements list.

M3SM : Bus Master 3 Supervisor Mode Access Control
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#00 : 00

r/w/x; read, write and execute allowed

#01 : 01

r/x; read and execute allowed, but no write

#10 : 10

r/w; read and write allowed, but no execute

#11 : 11

Same as User mode defined in M3UM

End of enumeration elements list.

M3PE : Bus Master 3 Process Identifier Enable
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not include the process identifier in the evaluation

#1 : 1

Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation

End of enumeration elements list.

M4WE : Bus Master 4 Write Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 4 writes allowed

End of enumeration elements list.

M4RE : Bus Master 4 Read Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 4 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 4 reads allowed

End of enumeration elements list.

M5WE : Bus Master 5 Write Enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 5 writes allowed

End of enumeration elements list.

M5RE : Bus Master 5 Read Enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 5 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 5 reads allowed

End of enumeration elements list.

M6WE : Bus Master 6 Write Enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 6 writes allowed

End of enumeration elements list.

M6RE : Bus Master 6 Read Enable
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 6 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 6 reads allowed

End of enumeration elements list.

M7WE : Bus Master 7 Write Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 writes terminate with an access error and the write is not performed

#1 : 1

Bus master 7 writes allowed

End of enumeration elements list.

M7RE : Bus Master 7 Read Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus master 7 reads terminate with an access error and the read is not performed

#1 : 1

Bus master 7 reads allowed

End of enumeration elements list.


RGD1_WORD3

Region Descriptor n, Word 3
address_offset : 0xC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RGD1_WORD3 RGD1_WORD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLD RESERVED PIDMASK PID

VLD : Valid
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Region descriptor is invalid

#1 : 1

Region descriptor is valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only

PIDMASK : Process Identifier Mask
bits : 16 - 23 (8 bit)
access : read-write

PID : Process Identifier
bits : 24 - 31 (8 bit)
access : read-write



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