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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected

Registers

YEARMON

CTRL

STATUS

ISR

IER

DAYS

GP_DATA_REG

DST_HOUR

DST_MONTH

DST_DAY

COMPEN

TAMPER_DIRECTION

TAMPER_QSCR

TAMPER_SCR

FILTER01_CFG

FILTER2_CFG

HOURMIN

TAMPER_QUEUE

CTRL2

SECONDS

ALM_YEARMON

ALM_DAYS

ALM_HOURMIN

ALM_SECONDS


YEARMON

RTC Year and Month Counters Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

YEARMON YEARMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MON_CNT RESERVED YROFST

MON_CNT : no description available
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0 : 0

Illegal Value

#1 : 1

January

#10 : 10

October

#11 : 11

November

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

YROFST : Year Offset Count Value
bits : 8 - 15 (8 bit)
access : read-write


CTRL

RTC Control Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINEEN COMP_EN ALM_MATCH TIMER_STB_MASK RESERVED DST_EN RESERVED SWR RESERVED CLKOUT RESERVED

FINEEN : Fine compensation enable bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

Fine compensation is enabled.

#0 : 0

Fine compensation is disabled

End of enumeration elements list.

COMP_EN : no description available
bits : 1 - 1 (1 bit)
access : read-write

ALM_MATCH : Alarm Match bits.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Only Seconds, Minutes, and Hours matched.

#01 : 01

Only Seconds, Minutes, Hours, and Days matched.

#10 : 10

Only Seconds, Minutes, Hours, Days, and Months matched.

End of enumeration elements list.

TIMER_STB_MASK : Sampling timer clocks mask
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#1 : 1

Sampling clocks are gated in standby mode

#0 : 0

Sampling clocks are not gated when in standby mode

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only

DST_EN : Daylight Saving Enable.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled. Daylight saving changes are not applied. Daylight saving registers can be modified.

#1 : 1

Enabled. Daylight saving changes are applied.

End of enumeration elements list.

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

SWR : Software Reset bit.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

#0 : 0

Software Reset cleared.

#1 : 1

Software Reset asserted.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 12 (4 bit)
access : read-only

CLKOUT : RTC Clock Output Selection.
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

#00 : 00

No Output Clock

#01 : 01

Fine 1 Hz Clock

#10 : 10

32.768 kHz Clock

#11 : 11

Coarse 1 Hz Clock

End of enumeration elements list.

RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only


STATUS

RTC Status Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVAL_BIT WRITE_PROT_EN CPU_LOW_VOLT RST_SRC RESERVED CMP_INT WE BUS_ERR RESERVED RESERVED CMP_DONE RESERVED

INVAL_BIT : Invalidate CPU read/write access bit.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time /Date Counters can be read/written. Time /Date is valid.

#1 : 1

Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written.

End of enumeration elements list.

WRITE_PROT_EN : Write Protect Enable status bit.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Registers are unlocked and can be accessed.

#1 : 1

Registers are locked and in read-only mode.

End of enumeration elements list.

CPU_LOW_VOLT : CPU Low Voltage Warning status bit.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

CPU in Normal Operating Voltage.

#1 : 1

CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode.

End of enumeration elements list.

RST_SRC : Reset Source bit.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

Part was reset due to Standby Mode Exit (that is when VDD is powered up and VBAT was not powered down at all).

#1 : 1

Part was reset due to Power-On Reset (that is Power On Reset when both VBAT and VDD are powered up).

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

CMP_INT : Compensation Interval bit.
bits : 5 - 5 (1 bit)
access : read-only

WE : Write Enable bits.
bits : 6 - 7 (2 bit)
access : write-only

Enumeration:

#10 : 10

Enable Write Protection - Registers are locked.

End of enumeration elements list.

BUS_ERR : Bus Error bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Read and Write accesses are normal.

#1 : 1

Read or Write accesses occurred when INVAL_BIT was asserted.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only

RESERVED : no description available
bits : 10 - 10 (1 bit)
access : read-only

CMP_DONE : Compensation Done bit.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compensation busy or not enabled.

#1 : 1

Compensation completed.

End of enumeration elements list.

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only


ISR

RTC Interrupt Status Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMPER_IS RESERVED ALM_IS DAY_IS HOUR_IS MIN_IS IS_1HZ IS_2HZ IS_4HZ IS_8HZ IS_16HZ IS_32HZ IS_64HZ IS_128HZ IS_256HZ IS_512HZ

TAMPER_IS : Tamper Interrupt Status bit.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted (Default on reset) .

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

ALM_IS : Alarm Interrupt Status bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

DAY_IS : Days Interrupt Status bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

HOUR_IS : Hours Interrupt Status bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

MIN_IS : Minutes Interrupt Status bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_1HZ : 1 Hz Interval Interrupt Status bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_2HZ : 2 Hz Interval Interrupt Status bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_4HZ : 4 Hz Interval Interrupt Status bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_8HZ : 8 Hz Interval Interrupt Status bit.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_16HZ : 16 Hz Interval Interrupt Status bit.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_32HZ : 32 Hz Interval Interrupt Status bit.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_64HZ : 64 Hz Interval Interrupt Status bit.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_128HZ : 128 Hz Interval Interrupt Status bit.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_256HZ : 256 Hz Interval Interrupt Status bit.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.

IS_512HZ : 512 Hz Interval Interrupt Status bit.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is de-asserted.

#1 : 1

Interrupt is asserted.

End of enumeration elements list.


IER

RTC Interrupt Enable Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMPER_IE RESERVED ALM_IE DAY_IE HOUR_IE MIN_IE IE_1HZ IE_2HZ IE_4HZ IE_8HZ IE_16HZ IE_32HZ IE_64HZ IE_128HZ IE_256HZ IE_512HZ

TAMPER_IE : Tamper Interrupt Enable bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled (Default on reset).

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

ALM_IE : Alarm Interrupt Enable bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

DAY_IE : Days Interrupt Enable bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

HOUR_IE : Hours Interrupt Enable bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

MIN_IE : Minutes Interrupt Enable bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_1HZ : 1 Hz Interval Interrupt Enable bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_2HZ : 2 Hz Interval Interrupt Enable bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_4HZ : 4 Hz Interval Interrupt Enable bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_8HZ : 8 Hz Interval Interrupt Enable bit.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_16HZ : 16 Hz Interval Interrupt Enable bit.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_32HZ : 32 Hz Interval Interrupt Enable bit.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_64HZ : 64 Hz Interval Interrupt Enable bit.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_128HZ : 128 Hz Interval Interrupt Enable bit.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_256HZ : 256 Hz Interval Interrupt Enable bit.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.

IE_512HZ : 512 Hz Interval Interrupt Enable bit.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt is disabled.

#1 : 1

Interrupt is enabled.

End of enumeration elements list.


DAYS

RTC Days and Day-of-Week Counters Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAYS DAYS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY_CNT RESERVED DOW RESERVED

DAY_CNT : Days Counter Value.
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

DOW : Day of Week Counter Value.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0 : 0

Sunday

#1 : 1

Monday

End of enumeration elements list.

RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only


GP_DATA_REG

RTC General Purpose Data Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_DATA_REG GP_DATA_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP_DATA_REG

GP_DATA_REG : no description available
bits : 0 - 15 (16 bit)
access : read-write


DST_HOUR

RTC Daylight Saving Hour Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DST_HOUR DST_HOUR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST_END_HOUR RESERVED DST_START_HOUR RESERVED

DST_END_HOUR : Daylight Saving Time (DST) Hours End Value.
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

DST_START_HOUR : Daylight Saving Time (DST) Hours Start Value.
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only


DST_MONTH

RTC Daylight Saving Month Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DST_MONTH DST_MONTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST_END_MONTH RESERVED DST_START_MONTH RESERVED

DST_END_MONTH : Daylight Saving Time (DST) Month End Value.
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

DST_START_MONTH : Daylight Saving Time (DST) Month Start Value.
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only


DST_DAY

RTC Daylight Saving Day Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DST_DAY DST_DAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DST_END_DAY RESERVED DST_START_DAY RESERVED

DST_END_DAY : Daylight Saving Time (DST) Day End Value.
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

DST_START_DAY : Daylight Saving Time (DST) Day Start Value.
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only


COMPEN

RTC Compensation Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPEN COMPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPEN_VAL

COMPEN_VAL : Compensation Value
bits : 0 - 15 (16 bit)
access : read-write


TAMPER_DIRECTION

Tamper Direction Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAMPER_DIRECTION TAMPER_DIRECTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A_P_TAMP RESERVED I_O_TAMP RESERVED

A_P_TAMP : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

I_O_TAMP : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only


TAMPER_QSCR

Tamper Queue Status and Control Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAMPER_QSCR TAMPER_QSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q_FULL Q_FULL_INT_EN Q_CLEAR RESERVED LFSR_CLK_SEL RESERVED LFSR_DURATION

Q_FULL : no description available
bits : 0 - 0 (1 bit)
access : read-write

Q_FULL_INT_EN : no description available
bits : 1 - 1 (1 bit)
access : read-write

Q_CLEAR : no description available
bits : 2 - 2 (1 bit)
access : write-only

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

LFSR_CLK_SEL : no description available
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : no description available
bits : 11 - 11 (1 bit)
access : read-only

LFSR_DURATION : no description available
bits : 12 - 15 (4 bit)
access : read-write


TAMPER_SCR

RTC Tamper Status and Control Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAMPER_SCR TAMPER_SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMPR_EN RESERVED TMPR_STS RESERVED

TMPR_EN : Tamper Control
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

TMPR_STS : Tamper Status Bit
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only


FILTER01_CFG

RTC Tamper 0 1 Filter Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTER01_CFG FILTER01_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIL_DUR1 CLK_SEL1 POL1 FIL_DUR0 CLK_SEL0 POL0

FIL_DUR1 : Tamper Detect Bit 1 Filter Duration
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0 : 0

Filtering operation disabled.

End of enumeration elements list.

CLK_SEL1 : Tamper Filter 1 Clock Select
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 000

32 kHz clock

#001 : 001

512 Hz clock

#010 : 010

128 Hz clock

#011 : 011

64 Hz clock

#100 : 100

16 Hz clock

#101 : 101

8 Hz clock

#110 : 110

4 Hz clock

#111 : 111

2 Hz clock

End of enumeration elements list.

POL1 : Tamper Detect Input Bit 1 Polarity Control
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper detect input bit 1 is active high.

#1 : 1

Tamper detect input bit 1 is active low.

End of enumeration elements list.

FIL_DUR0 : Tamper Detect Bit 0 Filter Duration
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0 : 0

Filtering operation disabled.

End of enumeration elements list.

CLK_SEL0 : Tamper Filter 0 Clock Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

32 kHz clock

#001 : 001

512 Hz clock

#010 : 010

128 Hz clock

#011 : 011

64 Hz clock

#100 : 100

16 Hz clock

#101 : 101

8 Hz clock

#110 : 110

4 Hz clock

#111 : 111

2 Hz clock

End of enumeration elements list.

POL0 : Tamper Detect Input Bit 0 Polarity Control
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper detect input bit 0 is active high.

#1 : 1

Tamper detect input bit 0 is active low.

End of enumeration elements list.


FILTER2_CFG

RTC Tamper 2 Filter Configuration Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILTER2_CFG FILTER2_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED FIL_DUR2 CLK_SEL2 POL2

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

FIL_DUR2 : Tamper Detect Bit 2 Filter Duration
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0 : 0

Filtering operation disabled.

End of enumeration elements list.

CLK_SEL2 : Tamper Filter 2 Clock Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

32 kHz clock

#001 : 001

512 Hz clock

#010 : 010

128 Hz clock

#011 : 011

64 Hz clock

#100 : 100

16 Hz clock

#101 : 101

8 Hz clock

#110 : 110

4 Hz clock

#111 : 111

2 Hz clock

End of enumeration elements list.

POL2 : Tamper Detect Input Bit 2 Polarity Control
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper detect input bit 2 is active high.

#1 : 1

Tamper detect input bit 2 is active low.

End of enumeration elements list.


HOURMIN

RTC Hours and Minutes Counters Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOURMIN HOURMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN_CNT RESERVED HOUR_CNT RESERVED

MIN_CNT : Minutes Counter Value.
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

HOUR_CNT : Hours Counter Value.
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only


TAMPER_QUEUE

Tamper Queue Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAMPER_QUEUE TAMPER_QUEUE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMPER_DATA

TAMPER_DATA : Tamper type stamp and pin number information register
bits : 0 - 15 (16 bit)
access : read-only


CTRL2

RTC Control 2 Register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP_CFG_OVER RESERVED RESERVED WAKEUP_STATUS WAKEUP_MODE RESERVED

TAMP_CFG_OVER : Tamper Configuration Over
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper filter processing disabled.

#1 : 1

Tamper filter processing enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

WAKEUP_STATUS : Wakeup Status
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

The wakeup/hibernation pin is in HiZ mode.

#01 : 01

The wakeup/hibernation pin is at logic 0. MCU is in sleep mode.

#10 : 10

The wakeup/ hibernation pin is at logic 1. MCU is in sleep mode.

#11 : 11

Reserved

End of enumeration elements list.

WAKEUP_MODE : Wakeup Mode
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper pin 0 is used as the tamper pin.

#1 : 1

Tamper pin 0 is used as a wakeup/hibernation pin.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only


SECONDS

RTC Seconds Counters Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECONDS SECONDS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC_CNT RESERVED RESERVED

SEC_CNT : Seconds Counter Value.
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only


ALM_YEARMON

RTC Year and Months Alarm Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALM_YEARMON ALM_YEARMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM_MON RESERVED ALM_YEAR

ALM_MON : Months Value for Alarm.
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

ALM_YEAR : Year Value for Alarm.
bits : 8 - 15 (8 bit)
access : read-write


ALM_DAYS

RTC Days Alarm Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALM_DAYS ALM_DAYS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM_DAY RESERVED RESERVED

ALM_DAY : Days Value for Alarm.
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only


ALM_HOURMIN

RTC Hours and Minutes Alarm Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALM_HOURMIN ALM_HOURMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM_MIN RESERVED ALM_HOUR RESERVED

ALM_MIN : Minutes Value for Alarm.
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

ALM_HOUR : Hours Value for Alarm.
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only


ALM_SECONDS

RTC Seconds Alarm Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALM_SECONDS ALM_SECONDS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALM_SEC RESERVED DEC_SEC INC_SEC RESERVED

ALM_SEC : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

DEC_SEC : Decrement Seconds Counter by 1.
bits : 8 - 8 (1 bit)
access : write-only

INC_SEC : Increment Seconds Counter by 1.
bits : 9 - 9 (1 bit)
access : write-only

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only



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