\n

TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

COMP1

CMPLD1

CMPLD2

CSCTRL

FILT

ENBL

COMP2

CAPT

LOAD

HOLD

CNTR

CTRL

SCTRL


COMP1

Timer Channel Compare Register 1
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP1 COMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARISON_1

COMPARISON_1 : Comparison Value 1
bits : 0 - 15 (16 bit)
access : read-write


CMPLD1

Timer Channel Comparator Load Register 1
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPLD1 CMPLD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARATOR_LOAD_1

COMPARATOR_LOAD_1 : no description available
bits : 0 - 15 (16 bit)
access : read-write


CMPLD2

Timer Channel Comparator Load Register 2
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPLD2 CMPLD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARATOR_LOAD_2

COMPARATOR_LOAD_2 : no description available
bits : 0 - 15 (16 bit)
access : read-write


CSCTRL

Timer Channel Comparator Status and Control Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSCTRL CSCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL1 CL2 TCF1 TCF2 TCF1EN TCF2EN RESERVED UP TCI ROC ALT_LOAD FAULT DBG_EN

CL1 : Compare Load Control 1
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Never preload

#01 : 01

Load upon successful compare with the value in COMP1

#10 : 10

Load upon successful compare with the value in COMP2

#11 : 11

Reserved

End of enumeration elements list.

CL2 : Compare Load Control 2
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Never preload

#01 : 01

Load upon successful compare with the value in COMP1

#10 : 10

Load upon successful compare with the value in COMP2

#11 : 11

Reserved

End of enumeration elements list.

TCF1 : Timer Compare 1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

TCF2 : Timer Compare 2 Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

TCF1EN : Timer Compare 1 Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

TCF2EN : Timer Compare 2 Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 8 (1 bit)
access : read-only

UP : Counting Direction Indicator
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

The last count was in the DOWN direction.

#1 : 1

The last count was in the UP direction.

End of enumeration elements list.

TCI : Triggered Count Initialization Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stop counter upon receiving a second trigger event while still counting from the first trigger event.

#1 : 1

Reload the counter upon receiving a second trigger event while still counting from the first trigger event.

End of enumeration elements list.

ROC : Reload on Capture
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not reload the counter on a capture event.

#1 : 1

Reload the counter on a capture event.

End of enumeration elements list.

ALT_LOAD : Alternative Load Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Counter can be re-initialized only with the LOAD register.

#1 : 1

Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.

End of enumeration elements list.

FAULT : Fault Enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fault function disabled.

#1 : 1

Fault function enabled.

End of enumeration elements list.

DBG_EN : Debug Actions Enable
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

Continue with normal operation during debug mode. (default)

#01 : 01

Halt TMR counter during debug mode.

#10 : 10

Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).

#11 : 11

Both halt counter and force output to 0 during debug mode.

End of enumeration elements list.


FILT

Timer Channel Input Filter Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FILT FILT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT_PER FILT_CNT RESERVED

FILT_PER : Input Filter Sample Period
bits : 0 - 7 (8 bit)
access : read-write

FILT_CNT : Input Filter Sample Count
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only


ENBL

Timer Channel Enable Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENBL ENBL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBL RESERVED

ENBL : Timer Channel Enable
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0 : 0

Timer channel is disabled.

#1 : 1

Timer channel is enabled. (default)

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only


COMP2

Timer Channel Compare Register 2
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP2 COMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPARISON_2

COMPARISON_2 : Comparison Value 2
bits : 0 - 15 (16 bit)
access : read-write


CAPT

Timer Channel Capture Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPT CAPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTURE

CAPTURE : Capture Value
bits : 0 - 15 (16 bit)
access : read-write


LOAD

Timer Channel Load Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOAD

LOAD : Timer Load Register
bits : 0 - 15 (16 bit)
access : read-write


HOLD

Timer Channel Hold Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOLD HOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOLD

HOLD : no description available
bits : 0 - 15 (16 bit)
access : read-write


CNTR

Timer Channel Counter Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTR CNTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER

COUNTER : no description available
bits : 0 - 15 (16 bit)
access : read-write


CTRL

Timer Channel Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTMODE COINIT DIR LENGTH ONCE SCS PCS CM

OUTMODE : Output Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Asserted while counter is active

#001 : 001

Clear OFLAG output on successful compare

#010 : 010

Set OFLAG output on successful compare

#011 : 011

Toggle OFLAG output on successful compare

#100 : 100

Toggle OFLAG output using alternating compare registers

#101 : 101

Set on compare, cleared on secondary source input edge

#110 : 110

Set on compare, cleared on counter rollover

#111 : 111

Enable gated clock output while counter is active

End of enumeration elements list.

COINIT : Co-Channel Initialization
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Co-channel counter/timers cannot force a re-initialization of this counter/timer

#1 : 1

Co-channel counter/timers may force a re-initialization of this counter/timer

End of enumeration elements list.

DIR : Count Direction
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Count up.

#1 : 1

Count down.

End of enumeration elements list.

LENGTH : Count Length
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Roll over.

#1 : 1

Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.

End of enumeration elements list.

ONCE : Count Once
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Count repeatedly.

#1 : 1

Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.

End of enumeration elements list.

SCS : Secondary Count Source
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

#00 : 00

Counter 0 input pin

#01 : 01

Counter 1 input pin

#10 : 10

Counter 2 input pin

#11 : 11

Counter 3 input pin

End of enumeration elements list.

PCS : Primary Count Source
bits : 9 - 12 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Counter 0 input pin

#0001 : 0001

Counter 1 input pin

#0010 : 0010

Counter 2 input pin

#0011 : 0011

Counter 3 input pin

#0100 : 0100

Counter 0 output

#0101 : 0101

Counter 1 output

#0110 : 0110

Counter 2 output

#0111 : 0111

Counter 3 output

#1000 : 1000

IP bus clock divide by 1 prescaler

#1001 : 1001

IP bus clock divide by 2 prescaler

#1010 : 1010

IP bus clock divide by 4 prescaler

#1011 : 1011

IP bus clock divide by 8 prescaler

#1100 : 1100

IP bus clock divide by 16 prescaler

#1101 : 1101

IP bus clock divide by 32 prescaler

#1110 : 1110

IP bus clock divide by 64 prescaler

#1111 : 1111

IP bus clock divide by 128 prescaler

End of enumeration elements list.

CM : Count Mode
bits : 13 - 15 (3 bit)
access : read-write

Enumeration:

#000 : 000

No operation

#001 : 001

Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].

#010 : 010

Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.

#011 : 011

Count rising edges of primary source while secondary input high active

#100 : 100

Quadrature count mode, uses primary and secondary sources

#101 : 101

Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.

#110 : 110

Edge of secondary source triggers primary count until compare

#111 : 111

Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.

End of enumeration elements list.


SCTRL

Timer Channel Status and Control Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCTRL SCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OEN OPS FORCE VAL EEOF MSTR CAPTURE_MODE INPUT IPS IEFIE IEF TOFIE TOF TCFIE TCF

OEN : Output Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The external pin is configured as an input.

#1 : 1

The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.

End of enumeration elements list.

OPS : Output Polarity Select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

True polarity.

#1 : 1

Inverted polarity.

End of enumeration elements list.

FORCE : Force OFLAG Output
bits : 2 - 2 (1 bit)
access : write-only

VAL : Forced OFLAG Value
bits : 3 - 3 (1 bit)
access : read-write

EEOF : Enable External OFLAG Force
bits : 4 - 4 (1 bit)
access : read-write

MSTR : Master Mode
bits : 5 - 5 (1 bit)
access : read-write

CAPTURE_MODE : Input Capture Mode
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

Capture function is disabled

#01 : 01

Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input

#10 : 10

Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input

#11 : 11

Load capture register on both edges of input

End of enumeration elements list.

INPUT : External Input Signal
bits : 8 - 8 (1 bit)
access : read-only

IPS : Input Polarity Select
bits : 9 - 9 (1 bit)
access : read-write

IEFIE : Input Edge Flag Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

IEF : Input Edge Flag
bits : 11 - 11 (1 bit)
access : read-write

TOFIE : Timer Overflow Flag Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

TOF : Timer Overflow Flag
bits : 13 - 13 (1 bit)
access : read-write

TCFIE : Timer Compare Flag Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

TCF : Timer Compare Flag
bits : 15 - 15 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.