\n
address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
Channel0 Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 8 (9 bit)
access : read-only
HW_TRG : Hardware Trigger Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger select
#1 : 1
Hardware trigger select
End of enumeration elements list.
DEC_CLK_INP_SEL : Decimator Clock Input Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
On the chip modulator clock will be used
#1 : 1
External clock will be used.
End of enumeration elements list.
DEC_CLK_EDGE_SEL : Decimator Clock Edge Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Posedge will be used.
#1 : 1
Negedge will be used.
End of enumeration elements list.
CC : Continuous Conversion/Single Conversion Mode Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
One conversion following a triggering event
#1 : 1
Continuous conversions following a triggering event.
End of enumeration elements list.
DEC_EN : Decimation Filter enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Decimation filter is disabled.
#1 : 1
Decimation filter is enabled.
End of enumeration elements list.
SD_MOD_EN : Sigma Delta Modulator enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD ADC1 is disabled
#1 : 1
SD ADC1 is enabled
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 16 (2 bit)
access : read-only
BYP_MODE : AFE Channel0 bypass mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Bypass mode where ADC and PGA of channel0 are disabled.
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-only
PGA_GAIN_SEL : PGA Gain Select
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
#000 : 000
reserved
#001 : 001
1x (default)
#010 : 010
2x
#011 : 011
4x
#100 : 100
8x
#101 : 101
16x
#110 : 110
32x
#111 : 111
reserved
End of enumeration elements list.
RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only
PGA_EN : PGA enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PGA disabled
#1 : 1
PGA enabled
End of enumeration elements list.
RESERVED : no description available
bits : 25 - 28 (4 bit)
access : read-only
DEC_OSR : Decimator OverSampling Ratio select
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 000
64
#001 : 001
128
#010 : 010
256
#011 : 011
512
#100 : 100
1024
#101 : 101
2048
End of enumeration elements list.
Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 8 (9 bit)
access : read-only
STRTUP_CNT : Start up count
bits : 9 - 15 (7 bit)
access : read-write
RESERVED : no description available
bits : 16 - 17 (2 bit)
access : read-only
RESULT_FORMAT : Result Format
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Left justified 2's complement 32-bit : SVVVVVVVVVVVVVVVVVVVVVVV00000000 where (S= sign bit , V=valid result value, 0=zero)
#1 : 1
Right justified 2's complement 32-bit : SSSSSSSSSVVVVVVVVVVVVVVVVVVVVVVV where (S= sign bit , V= valid result value, 0= zero)
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 20 (2 bit)
access : read-only
DLY_OK : Delay OK
bits : 21 - 21 (1 bit)
access : write-only
RST_B : Software Reset
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
All ADCs, PGAs and Decimation filters are disabled. Clock Configuration bits will be reset.
#1 : 1
.= All ADCs, PGAs and Decimation filters are enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 23 - 24 (2 bit)
access : read-only
LPM_EN : Low power Mode enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
AFE will be in normal mode
#1 : 1
AFE will be in low power mode. Setting this bit reduce the current consumption of ADC and Buffer Amplifier , the max modulator clock frequency is below 1Mhz.
End of enumeration elements list.
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only
SOFT_TRG3 : Software Trigger3
bits : 27 - 27 (1 bit)
access : write-only
SOFT_TRG2 : Software Trigger2
bits : 28 - 28 (1 bit)
access : write-only
SOFT_TRG1 : Software Trigger1
bits : 29 - 29 (1 bit)
access : write-only
SOFT_TRG0 : Software Trigger0
bits : 30 - 30 (1 bit)
access : write-only
MSTR_EN : AFE Master Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
All ADCs are disabled.
#1 : 1
All ADCs and filters will get simultaneously enabled .
End of enumeration elements list.
Clock Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 20 (21 bit)
access : read-only
CLS : Clock Source Select
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 00
mod_clk0
#01 : 01
mod_clk1
#10 : 10
mod_clk2
#11 : 11
mod_clk3
End of enumeration elements list.
RESERVED : no description available
bits : 23 - 27 (5 bit)
access : read-only
DIV : Clock Divider Select
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
divide by 1
#0001 : 0001
divide by 2 (default)
#0010 : 0010
divide by 4
#0011 : 0011
divide by 8
#0100 : 0100
divide by 16
#0101 : 0101
divide by 32
#0110 : 0110
divide by 64
#0111 : 0111
divide by 128
#1xxx : 1xxx
divide by 256
End of enumeration elements list.
DMA and Interrupt Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 22 (23 bit)
access : read-only
INTEN3 : Interrupt Enable 3
bits : 23 - 23 (1 bit)
access : read-write
INTEN2 : Interrupt Enable 2
bits : 24 - 24 (1 bit)
access : read-write
INTEN1 : Interrupt Enable 1
bits : 25 - 25 (1 bit)
access : read-write
INTEN0 : Interrupt Enable 0
bits : 26 - 26 (1 bit)
access : read-write
RESERVED : no description available
bits : 27 - 27 (1 bit)
access : read-only
DMAEN3 : DMA Enable3
bits : 28 - 28 (1 bit)
access : read-write
DMAEN2 : DMA Enable2
bits : 29 - 29 (1 bit)
access : read-write
DMAEN1 : DMA Enable1
bits : 30 - 30 (1 bit)
access : read-write
DMAEN0 : DMA Enable0
bits : 31 - 31 (1 bit)
access : read-write
Channel0 Delay Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : Delay
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only
Channel1 Delay Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : Delay
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only
Channel2 Delay Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLY : Delay
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only
Channel1 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 8 (9 bit)
access : read-only
HW_TRG : Hardware Trigger Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger select
#1 : 1
Hardware trigger select
End of enumeration elements list.
DEC_CLK_INP_SEL : Decimator Clock Input Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
On the chip modulator clock will be used
#1 : 1
External clock will be used.
End of enumeration elements list.
DEC_CLK_EDGE_SEL : Decimator Clock Edge Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Posedge will be used.
#1 : 1
Negedge will be used.
End of enumeration elements list.
CC : Continuous Conversion/Single Conversion Mode Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
One conversion following a triggering event
#1 : 1
Continuous conversions following a triggering event.
End of enumeration elements list.
DEC_EN : Decimation Filter enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Decimation filter is disabled.
#1 : 1
Decimation filter is enabled.
End of enumeration elements list.
SD_MOD_EN : Sigma Delta Modulator enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD ADC1 is disabled
#1 : 1
SD ADC1 is enabled
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 16 (2 bit)
access : read-only
BYP_MODE : AFE Channel1 bypass mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Bypass mode where ADC and PGA of channel1 are disabled.
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-only
PGA_GAIN_SEL : PGA Gain Select
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
#000 : 000
reserved
#001 : 001
1x (default)
#010 : 010
2x
#011 : 011
4x
#100 : 100
8x
#101 : 101
16x
#110 : 110
32x
#111 : 111
reserved
End of enumeration elements list.
RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only
PGA_EN : PGA enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PGA disabled
#1 : 1
PGA enabled
End of enumeration elements list.
RESERVED : no description available
bits : 25 - 28 (4 bit)
access : read-only
DEC_OSR : Decimator OverSampling Ratio select
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 000
64
#001 : 001
128
#010 : 010
256
#011 : 011
512
#100 : 100
1024
#101 : 101
2048
End of enumeration elements list.
Channel0 Result Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDR : Sample Data Result
bits : 0 - 22 (23 bit)
access : read-only
SIGN_BITS : Sign Bits
bits : 23 - 31 (9 bit)
access : read-only
Channel1 Result Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDR : Sample Data Result
bits : 0 - 22 (23 bit)
access : read-only
SIGN_BITS : Sign Bits
bits : 23 - 31 (9 bit)
access : read-only
Channel2 Result Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SDR : Sample Data result
bits : 0 - 22 (23 bit)
access : read-only
SIGN_BITS : Sign Bits
bits : 23 - 31 (9 bit)
access : read-only
Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
RDY3 : AFE Ready4
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
AFE Channel3 is disabled or has not completed its start up period
#1 : 1
AFE Channel3 is ready to initiate conversions.
End of enumeration elements list.
RDY2 : AFE Ready3
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
AFE Channel2 is disabled or has not completed its start up period
#1 : 1
AFE Channel2 is ready to initiate conversions.
End of enumeration elements list.
RDY1 : AFE Ready2
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
AFE Channel1 is disabled or has not completed its start up period
#1 : 1
AFE Channel1 is ready to initiate conversions.
End of enumeration elements list.
RDY0 : AFE Ready1
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
AFE Channel0 is disabled or has not completed its start up period
#1 : 1
AFE Channel0 is ready to initiate conversions.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only
OVR3 : Overflow Flag
bits : 21 - 21 (1 bit)
access : read-only
OVR2 : Overflow Flag
bits : 22 - 22 (1 bit)
access : read-only
OVR1 : Overflow Flag
bits : 23 - 23 (1 bit)
access : read-only
OVR0 : Overflow Flag
bits : 24 - 24 (1 bit)
access : read-only
RESERVED : no description available
bits : 25 - 27 (3 bit)
access : read-only
COC3 : Conversion Complete
bits : 28 - 28 (1 bit)
access : read-only
COC2 : Conversion Complete
bits : 29 - 29 (1 bit)
access : read-only
COC1 : Conversion Complete
bits : 30 - 30 (1 bit)
access : read-only
COC0 : Conversion Complete
bits : 31 - 31 (1 bit)
access : read-only
Channel2 Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 8 (9 bit)
access : read-only
HW_TRG : Hardware Trigger Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger select
#1 : 1
Hardware trigger select
End of enumeration elements list.
DEC_CLK_INP_SEL : Decimator Clock Input Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
On the chip modulator clock will be used.
#1 : 1
External clock will be used.
End of enumeration elements list.
DEC_CLK_EDGE_SEL : Decimator Clock Edge Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Posedge will be used.
#1 : 1
Negedge will be used.
End of enumeration elements list.
CC : Continuous Conversion/Single Conversion Mode Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
One conversion following a triggering event
#1 : 1
Continuous conversions following a triggering event.
End of enumeration elements list.
DEC_EN : Decimation Filter enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Decimation filter is disabled.
#1 : 1
Decimation filter is enabled.
End of enumeration elements list.
SD_MOD_EN : Sigma Delta Modulator enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD ADC3 is disabled
#1 : 1
SD ADC3 is enabled
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 16 (2 bit)
access : read-only
BYP_MODE : AFE Channel2 bypass mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Bypass mode where ADC and PGA of channel2 are disabled.
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 28 (11 bit)
access : read-only
DEC_OSR : Decimator OverSampling Ratio select
bits : 29 - 31 (3 bit)
access : read-write
Enumeration:
#000 : 000
64
#001 : 001
128
#010 : 010
256
#011 : 011
512
#100 : 100
1024
#101 : 101
2048
End of enumeration elements list.
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