\n

Flash

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ACR

SR

CFGR

CR

ECCR

OPTR

PCROP1SR

PCROP1ER

WRP1AR

WRP2AR

PDKEYR

PCROP2SR

PCROP2ER

WRP1BR

WRP2BR

KEYR

OPTKEYR


ACR

Access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY PRFTEN ICEN DCEN ICRST DCRST RUN_PD SLEEP_PD

LATENCY : Latency
bits : 0 - 3 (4 bit)

PRFTEN : Prefetch enable
bits : 8 - 8 (1 bit)

ICEN : Instruction cache enable
bits : 9 - 9 (1 bit)

DCEN : Data cache enable
bits : 10 - 10 (1 bit)

ICRST : Instruction cache reset
bits : 11 - 11 (1 bit)

DCRST : Data cache reset
bits : 12 - 12 (1 bit)

RUN_PD : Flash Power-down mode during Low-power run mode
bits : 13 - 13 (1 bit)

SLEEP_PD : Flash Power-down mode during Low-power sleep mode
bits : 14 - 14 (1 bit)


SR

Status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOP OPERR PROGERR WRPERR PGAERR SIZERR PGSERR MISERR FASTERR RDERR OPTVERR BSY PEMPTY

EOP : End of operation
bits : 0 - 0 (1 bit)
access : read-write

OPERR : Operation error
bits : 1 - 1 (1 bit)
access : read-write

PROGERR : Programming error
bits : 3 - 3 (1 bit)
access : read-write

WRPERR : Write protected error
bits : 4 - 4 (1 bit)
access : read-write

PGAERR : Programming alignment error
bits : 5 - 5 (1 bit)
access : read-write

SIZERR : Size error
bits : 6 - 6 (1 bit)
access : read-write

PGSERR : Programming sequence error
bits : 7 - 7 (1 bit)
access : read-write

MISERR : Fast programming data miss error
bits : 8 - 8 (1 bit)
access : read-write

FASTERR : Fast programming error
bits : 9 - 9 (1 bit)
access : read-write

RDERR : PCROP read error
bits : 14 - 14 (1 bit)
access : read-write

OPTVERR : Option validity error
bits : 15 - 15 (1 bit)
access : read-write

BSY : Busy
bits : 16 - 16 (1 bit)
access : read-only

PEMPTY : Program EMPTY
bits : 17 - 17 (1 bit)
access : read-write


CFGR

Flash configuration register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVEN

LVEN : Low voltage enable
bits : 0 - 0 (1 bit)


CR

Flash control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER1 PNB BKER MER2 START OPTSTRT FSTPG EOPIE ERRIE RDERRIE OBL_LAUNCH OPTLOCK LOCK

PG : Programming
bits : 0 - 0 (1 bit)

PER : Page erase
bits : 1 - 1 (1 bit)

MER1 : Bank 1 Mass erase
bits : 2 - 2 (1 bit)

PNB : Page number
bits : 3 - 10 (8 bit)

BKER : Bank erase
bits : 11 - 11 (1 bit)

MER2 : Bank 2 Mass erase
bits : 15 - 15 (1 bit)

START : Start
bits : 16 - 16 (1 bit)

OPTSTRT : Options modification start
bits : 17 - 17 (1 bit)

FSTPG : Fast programming
bits : 18 - 18 (1 bit)

EOPIE : End of operation interrupt enable
bits : 24 - 24 (1 bit)

ERRIE : Error interrupt enable
bits : 25 - 25 (1 bit)

RDERRIE : PCROP read error interrupt enable
bits : 26 - 26 (1 bit)

OBL_LAUNCH : Force the option byte loading
bits : 27 - 27 (1 bit)

OPTLOCK : Options Lock
bits : 30 - 30 (1 bit)

LOCK : FLASH_CR Lock
bits : 31 - 31 (1 bit)


ECCR

Flash ECC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCR ECCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR_ECC BK_ECC SYSF_ECC ECCIE ECCC2 ECCD2 ECCC ECCD

ADDR_ECC : ECC fail address
bits : 0 - 20 (21 bit)
access : read-only

BK_ECC : ECC fail bank
bits : 21 - 21 (1 bit)
access : read-only

SYSF_ECC : System Flash ECC fail
bits : 22 - 22 (1 bit)
access : read-only

ECCIE : ECC correction interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

ECCC2 : ECC correction
bits : 28 - 28 (1 bit)
access : read-write

ECCD2 : ECC2 detection
bits : 29 - 29 (1 bit)
access : read-write

ECCC : ECC correction
bits : 30 - 30 (1 bit)
access : read-write

ECCD : ECC detection
bits : 31 - 31 (1 bit)
access : read-write


OPTR

Flash option register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPTR OPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDP BOR_LEV nRST_STOP nRST_STDBY nRST_SHDW IDWG_SW IWDG_SW IWDG_STOP IWDG_STDBY WWDG_SW BFB2 DUALBANK DB1M DBANK nBOOT1 SRAM2_PE SRAM2_RST nSWBOOT0 nBOOT0

RDP : Read protection level
bits : 0 - 7 (8 bit)

BOR_LEV : BOR reset Level
bits : 8 - 10 (3 bit)

nRST_STOP : nRST_STOP
bits : 12 - 12 (1 bit)

nRST_STDBY : nRST_STDBY
bits : 13 - 13 (1 bit)

nRST_SHDW : nRST_SHDW
bits : 14 - 14 (1 bit)

IDWG_SW : Independent watchdog selection
bits : 16 - 16 (1 bit)

IWDG_SW : Independent watchdog selection
bits : 16 - 16 (1 bit)

IWDG_STOP : Independent watchdog counter freeze in Stop mode
bits : 17 - 17 (1 bit)

IWDG_STDBY : Independent watchdog counter freeze in Standby mode
bits : 18 - 18 (1 bit)

WWDG_SW : Window watchdog selection
bits : 19 - 19 (1 bit)

BFB2 : Dual-bank boot
bits : 20 - 20 (1 bit)

DUALBANK : Dual-Bank on 512 KB or 256 KB Flash memory devices
bits : 21 - 21 (1 bit)

DB1M : Dual-bank on 1 Mbyte Flash memory devices
bits : 21 - 21 (1 bit)

DBANK : DBANK
bits : 22 - 22 (1 bit)

nBOOT1 : Boot configuration
bits : 23 - 23 (1 bit)

SRAM2_PE : SRAM2 parity check enable
bits : 24 - 24 (1 bit)

SRAM2_RST : SRAM2 Erase when system reset
bits : 25 - 25 (1 bit)

nSWBOOT0 : Software BOOT0
bits : 26 - 26 (1 bit)

nBOOT0 : nBOOT0 option bit
bits : 27 - 27 (1 bit)


PCROP1SR

Flash Bank 1 PCROP Start address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP1SR PCROP1SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP1_STRT

PCROP1_STRT : Bank 1 PCROP area start offset
bits : 0 - 16 (17 bit)


PCROP1ER

Flash Bank 1 PCROP End address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP1ER PCROP1ER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP1_END PCROP_RDP

PCROP1_END : Bank 1 PCROP area end offset
bits : 0 - 16 (17 bit)

PCROP_RDP : PCROP area preserved when RDP level decreased
bits : 31 - 31 (1 bit)


WRP1AR

Flash Bank 1 WRP area A address register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRP1AR WRP1AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP1A_STRT WRP1A_END

WRP1A_STRT : Bank 1 WRP first area start offset
bits : 0 - 7 (8 bit)

WRP1A_END : Bank 1 WRP first area A end offset
bits : 16 - 23 (8 bit)


WRP2AR

Flash WRP2 area A address register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRP2AR WRP2AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP2A_STRT WRP2A_END

WRP2A_STRT : WRP first area A start offset
bits : 0 - 7 (8 bit)

WRP2A_END : WRP first area A end offset
bits : 16 - 23 (8 bit)


PDKEYR

Power down key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDKEYR PDKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDKEYR

PDKEYR : RUN_PD in FLASH_ACR key
bits : 0 - 31 (32 bit)


PCROP2SR

Flash PCROP2 Start address register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP2SR PCROP2SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP2_STRT

PCROP2_STRT : PCROP area start offset
bits : 0 - 16 (17 bit)


PCROP2ER

Flash PCROP2 End address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCROP2ER PCROP2ER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCROP2_END

PCROP2_END : Bank 2 PCROP area end offset
bits : 0 - 16 (17 bit)


WRP1BR

Flash WRP1 area B address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRP1BR WRP1BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP1B_STRT WRP1B_END

WRP1B_STRT : Bank 2 WRP first area A start offset
bits : 0 - 7 (8 bit)

WRP1B_END : Bank 2 WRP first area A end offset
bits : 16 - 23 (8 bit)


WRP2BR

Flash Bank 2 WRP area B address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRP2BR WRP2BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP2B_STRT WRP2B_END

WRP2B_STRT : Bank 2 WRP second area B start offset
bits : 0 - 7 (8 bit)

WRP2B_END : Bank 2 WRP second area B end offset
bits : 16 - 23 (8 bit)


KEYR

Flash key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYR KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYR

KEYR : KEYR
bits : 0 - 31 (32 bit)


OPTKEYR

Option byte key register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OPTKEYR OPTKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEYR

OPTKEYR : Option byte key
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.