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LTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8FC byte (0x0)
mem_usage : registers
protection : not protected

Registers

MD

DS

CTXR_0

CTXR_1

CTXR_2

CTXR_3

CTXR_4

CTXR_5

CTXR_6

CTXR_7

CTXR_8

CTXR_9

CTXR_10

CTXR_11

CTXR_12

CTXR_13

CTXR_14

CTXR_15

ICVS

KEYR_0

KEYR_1

KEYR_2

KEYR_3

KEYR_4

KEYR_5

KEYR_6

KEYR_7

COM

CTL

CW

STA

ESTA

AADSZ

FIFOSTA

IFIFO

OFIFO

KS

VID1

CHAVID


MD

LTC Mode Register (non-PKHA/non-RNG use)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MD MD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENC ICV_TEST AS AAI ALG

ENC : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Decrypt.

#1 : 1

Encrypt.

End of enumeration elements list.

ICV_TEST : no description available
bits : 1 - 1 (1 bit)
access : read-write

AS : no description available
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Update

#01 : 01

Initialize

#10 : 10

Finalize

#11 : 11

Initialize/Finalize

End of enumeration elements list.

AAI : no description available
bits : 4 - 12 (9 bit)
access : read-write

ALG : no description available
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

#00010000 : 00010000

AES

End of enumeration elements list.


DS

LTC Data Size Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DS DS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DS

DS : no description available
bits : 0 - 11 (12 bit)
access : read-write


CTXR_0

LTC Context Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_0 CTXR_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_1

LTC Context Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_1 CTXR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_2

LTC Context Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_2 CTXR_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_3

LTC Context Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_3 CTXR_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_4

LTC Context Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_4 CTXR_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_5

LTC Context Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_5 CTXR_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_6

LTC Context Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_6 CTXR_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_7

LTC Context Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_7 CTXR_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_8

LTC Context Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_8 CTXR_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_9

LTC Context Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_9 CTXR_9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_10

LTC Context Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_10 CTXR_10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_11

LTC Context Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_11 CTXR_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_12

LTC Context Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_12 CTXR_12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_13

LTC Context Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_13 CTXR_13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_14

LTC Context Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_14 CTXR_14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


CTXR_15

LTC Context Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTXR_15 CTXR_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTX

CTX : no description available
bits : 0 - 31 (32 bit)
access : read-write


ICVS

LTC ICV Size Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICVS ICVS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICVS

ICVS : no description available
bits : 0 - 4 (5 bit)
access : read-write


KEYR_0

LTC Key Registers
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_0 KEYR_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_1

LTC Key Registers
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_1 KEYR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_2

LTC Key Registers
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_2 KEYR_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_3

LTC Key Registers
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_3 KEYR_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_4

LTC Key Registers
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_4 KEYR_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_5

LTC Key Registers
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_5 KEYR_5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_6

LTC Key Registers
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_6 KEYR_6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


KEYR_7

LTC Key Registers
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYR_7 KEYR_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : no description available
bits : 0 - 31 (32 bit)
access : read-write


COM

LTC Command Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COM COM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALL AES

ALL : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

Do Not Reset

#1 : 1

Reset all CHAs in use by this CCB.

End of enumeration elements list.

AES : no description available
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

Do Not Reset

#1 : 1

Reset AES Accelerator

End of enumeration elements list.


CTL

LTC Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM IFE IFR OFE OFR IFS OFS KIS KOS CIS COS KAL

IM : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt not masked.

#1 : 1

Interrupt masked

End of enumeration elements list.

IFE : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA Request and Done signals disabled for the Input FIFO.

#1 : 1

DMA Request and Done signals enabled for the Input FIFO.

End of enumeration elements list.

IFR : no description available
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA request size is 1 entry.

#1 : 1

DMA request size is 4 entries.

End of enumeration elements list.

OFE : no description available
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA Request and Done signals disabled for the Output FIFO.

#1 : 1

DMA Request and Done signals enabled for the Output FIFO.

End of enumeration elements list.

OFR : no description available
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA request size is 1 entry.

#1 : 1

DMA request size is 4 entries.

End of enumeration elements list.

IFS : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do Not Byte Swap Data.

#1 : 1

Byte Swap Data.

End of enumeration elements list.

OFS : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do Not Byte Swap Data.

#1 : 1

Byte Swap Data.

End of enumeration elements list.

KIS : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do Not Byte Swap Data.

#1 : 1

Byte Swap Data.

End of enumeration elements list.

KOS : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do Not Byte Swap Data.

#1 : 1

Byte Swap Data.

End of enumeration elements list.

CIS : no description available
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do Not Byte Swap Data.

#1 : 1

Byte Swap Data.

End of enumeration elements list.

COS : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do Not Byte Swap Data.

#1 : 1

Byte Swap Data.

End of enumeration elements list.

KAL : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Key Register is readable.

#1 : 1

Key Register is not readable.

End of enumeration elements list.


CW

LTC Clear Written Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CW CW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM CDS CICV CCR CKR COF CIF

CM : no description available
bits : 0 - 0 (1 bit)
access : write-only

CDS : no description available
bits : 2 - 2 (1 bit)
access : write-only

CICV : no description available
bits : 3 - 3 (1 bit)
access : write-only

CCR : no description available
bits : 5 - 5 (1 bit)
access : write-only

CKR : no description available
bits : 6 - 6 (1 bit)
access : write-only

COF : no description available
bits : 30 - 30 (1 bit)
access : write-only

CIF : no description available
bits : 31 - 31 (1 bit)
access : write-only


STA

LTC Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STA STA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AB DI EI

AB : no description available
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

AESA Idle

#1 : 1

AESA Busy.

End of enumeration elements list.

DI : no description available
bits : 16 - 16 (1 bit)
access : read-write

EI : no description available
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not Error.

#1 : 1

Error Interrupt.

End of enumeration elements list.


ESTA

LTC Error Status Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ESTA ESTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRID1 CL1

ERRID1 : no description available
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

#0001 : 0001

Mode Error

#0010 : 0010

Data Size Error

#0011 : 0011

Key Size Error

#0110 : 0110

Data Arrived out of Sequence Error

#1010 : 1010

ICV Check Failed

#1011 : 1011

Internal Hardware Failure

#1100 : 1100

CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)

#1111 : 1111

Invalid Crypto Engine Selected

End of enumeration elements list.

CL1 : no description available
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

#0000 : 0000

LTC General Error

#0001 : 0001

AES

End of enumeration elements list.


AADSZ

LTC AAD Size Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AADSZ AADSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AADSZ AL

AADSZ : no description available
bits : 0 - 3 (4 bit)
access : read-write

AL : no description available
bits : 31 - 31 (1 bit)
access : read-write


FIFOSTA

LTC FIFO Status Register
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFOSTA FIFOSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFL IFF OFL OFF

IFL : no description available
bits : 0 - 6 (7 bit)
access : read-only

IFF : no description available
bits : 15 - 15 (1 bit)
access : read-only

OFL : no description available
bits : 16 - 22 (7 bit)
access : read-only

OFF : no description available
bits : 31 - 31 (1 bit)
access : read-only


IFIFO

LTC Input Data FIFO
address_offset : 0x7E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFIFO IFIFO write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFIFO

IFIFO : no description available
bits : 0 - 31 (32 bit)
access : write-only


OFIFO

LTC Output Data FIFO
address_offset : 0x7F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OFIFO OFIFO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFIFO

OFIFO : no description available
bits : 0 - 31 (32 bit)
access : read-only


KS

LTC Key Size Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

KS KS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KS

KS : no description available
bits : 0 - 31 (32 bit)
access : read-only


VID1

LTC Version ID Register
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID1 VID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIN_REV MAJ_REV IP_ID

MIN_REV : no description available
bits : 0 - 7 (8 bit)
access : read-only

MAJ_REV : no description available
bits : 8 - 15 (8 bit)
access : read-only

IP_ID : no description available
bits : 16 - 31 (16 bit)
access : read-only


CHAVID

LTC CHA Version ID Register
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHAVID CHAVID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AESREV AESVID

AESREV : no description available
bits : 0 - 3 (4 bit)
access : read-only

AESVID : no description available
bits : 4 - 7 (4 bit)
access : read-only



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