Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
RX Digital Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_ADC_NEGEDGE : Receive ADC Negative Edge Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Register ADC data on positive edge of clock
#1 : 1
Register ADC data on negative edge of clock
End of enumeration elements list.
RX_CH_FILT_BYPASS : Receive Channel Filter Bypass
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel filter is enabled.
#1 : 1
Disable and bypass channel filter.
End of enumeration elements list.
RX_ADC_RAW_EN : ADC Raw Mode selection
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
The decimation filter's 12bit output consists of ADC samples in the 8 LSBs. This is for test purposes only to observe ADC output via XCVR DMA or DTEST.
End of enumeration elements list.
RX_ADC_POL : Receive ADC Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC output of 1'b0 maps to -1, 1'b1 maps to +1 (default)
#1 : 1
ADC output of 1'b0 maps to +1, 1'b1 maps to -1
End of enumeration elements list.
RX_DEC_FILT_OSR : Decimation Filter Oversampling
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
OSR 4
#001 : 1
OSR 8
#010 : 2
OSR 16
#100 : 4
OSR 32
#011 : 3
OSR 6
#101 : 5
OSR 12
#110 : 6
OSR 24
End of enumeration elements list.
RX_FSK_ZB_SEL : FSK / 802.15.4 demodulator select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
FSK demodulator.
#1 : 1
802.15.4 demodulator.
End of enumeration elements list.
RX_NORM_EN : Normalizer Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normalizer is disabled.
#1 : 1
Normalizer is enabled.
End of enumeration elements list.
RX_RSSI_EN : RSSI Measurement Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RSSI measurement is disabled.
#1 : 1
RSSI measurement is enabled.
End of enumeration elements list.
RX_AGC_EN : AGC Global Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
AGC is disabled.
#1 : 1
AGC is enabled.
End of enumeration elements list.
RX_DCOC_EN : DCOC Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCOC is disabled.
#1 : 1
DCOC is enabled.
End of enumeration elements list.
RX_DCOC_CAL_EN : DCOC Calibration Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCOC calibration is disabled.
#1 : 1
DCOC calibration is enabled.
End of enumeration elements list.
RX_IQ_SWAP : RX IQ Swap
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
IQ swap is disabled.
#1 : 1
IQ swap is enabled.
End of enumeration elements list.
RX_DC_RESID_EN : DC Residual Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
DC Residual block is disabled.
#1 : 1
DC Residual block is enabled.
End of enumeration elements list.
RX_SRC_EN : RX Sample Rate Converter Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRC is disabled.
#1 : 1
SRC is enabled.
End of enumeration elements list.
RX_SRC_RATE : RX Sample Rate Converter Rate Selections
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRC is configured for a First Order Hold rate of 8/13.
#1 : 1
SRC is configured for a Zero Order Hold rate of 12/13.
End of enumeration elements list.
RX_DMA_DTEST_EN : RX DMA and DTEST enable
bits : 18 - 18 (1 bit)
access : read-write
RX_DEC_FILT_GAIN : Decimation Filter Fractional Gain
bits : 20 - 24 (5 bit)
access : read-write
RX_DEC_FILT_HZD_CORR_DIS : Decimator filter hazard correction disable
bits : 25 - 25 (1 bit)
access : read-write
RX_DEC_FILT_HAZARD : Decimator output, hazard condition detected
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hazard condition has not been detected
#1 : 1
A hazard condition has been detected
End of enumeration elements list.
RX_RSSI_FILT_HAZARD : Decimator output for RSSI, hazard condition detected
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hazard condition has not been detected
#1 : 1
A hazard condition has been detected
End of enumeration elements list.
RX_DEC_FILT_SAT_I : Decimator output, saturation detected for I channel
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
A saturation condition has not occurred.
#1 : 1
A saturation condition has occurred.
End of enumeration elements list.
RX_DEC_FILT_SAT_Q : Decimator output, saturation detected for Q channel
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
A saturation condition has not occurred.
#1 : 1
A saturation condition has occurred.
End of enumeration elements list.
AGC Control 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_UNFREEZE_TIME : AGC Unfreeze Time
bits : 0 - 12 (13 bit)
access : read-write
AGC_PDET_LO_DLY : AGC Peak Detect Low Delay
bits : 13 - 15 (3 bit)
access : read-write
AGC_RSSI_DELT_H2S : AGC_RSSI_DELT_H2S
bits : 16 - 22 (7 bit)
access : read-write
AGC_H2S_STEP_SZ : AGC_H2S_STEP_SZ
bits : 23 - 27 (5 bit)
access : read-write
AGC_UP_STEP_SZ : AGC Up Step Size
bits : 28 - 31 (4 bit)
access : read-write
DCOC Offset
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC BBA DAC Step
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_DCOC_STEP_RECIP : DCOC BBA Reciprocal of Step Size
bits : 0 - 12 (13 bit)
access : read-write
BBA_DCOC_STEP : DCOC BBA Step Size
bits : 16 - 24 (9 bit)
access : read-write
DCOC TZA DAC Step 0
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_0 : DCOC_TZA_STEP_RCP_0
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_0 : DCOC_TZA_STEP_GAIN_0
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 1
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_1 : DCOC_TZA_STEP_RCP_1
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_1 : DCOC_TZA_STEP_GAIN_1
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 2
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_2 : DCOC_TZA_STEP_RCP_2
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_2 : DCOC_TZA_STEP_GAIN_2
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 3
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_3 : DCOC_TZA_STEP_RCP_3
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_3 : DCOC_TZA_STEP_GAIN_3
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 4
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_4 : DCOC_TZA_STEP_RCP_4
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_4 : DCOC_TZA_STEP_GAIN_4
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 5
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_5 : DCOC_TZA_STEP_RCP_5
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_5 : DCOC_TZA_STEP_GAIN_5
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 6
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_6 : DCOC_TZA_STEP_RCP_6
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_6 : DCOC_TZA_STEP_GAIN_6
bits : 16 - 27 (12 bit)
access : read-write
DCOC TZA DAC Step 7
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_7 : DCOC_TZA_STEP_RCP_7
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_7 : DCOC_TZA_STEP_GAIN_7
bits : 16 - 28 (13 bit)
access : read-write
DCOC TZA DAC Step 5
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_8 : DCOC_TZA_STEP_RCP_8
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_8 : DCOC_TZA_STEP_GAIN_8
bits : 16 - 28 (13 bit)
access : read-write
DCOC TZA DAC Step 9
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_9 : DCOC_TZA_STEP_RCP_9
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_9 : DCOC_TZA_STEP_GAIN_9
bits : 16 - 29 (14 bit)
access : read-write
DCOC TZA DAC Step 10
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TZA_STEP_RCP_10 : DCOC_TZA_STEP_RCP_10
bits : 0 - 12 (13 bit)
access : read-write
DCOC_TZA_STEP_GAIN_10 : DCOC_TZA_STEP_GAIN_10
bits : 16 - 29 (14 bit)
access : read-write
AGC Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BBA_PDET_LO_STAT : BBA Peak Detector Low Status
bits : 0 - 0 (1 bit)
access : read-only
BBA_PDET_HI_STAT : BBA Peak Detector High Status
bits : 1 - 1 (1 bit)
access : read-only
TZA_PDET_LO_STAT : TZA Peak Detector Low Status
bits : 2 - 2 (1 bit)
access : read-only
TZA_PDET_HI_STAT : TZA Peak Detector High Status
bits : 3 - 3 (1 bit)
access : read-only
CURR_AGC_IDX : Current AGC Gain Index
bits : 4 - 8 (5 bit)
access : read-only
AGC_FROZEN : AGC Frozen Status
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
AGC is not frozen.
#1 : 1
AGC is frozen.
End of enumeration elements list.
RSSI_ADC_RAW : ADC RAW RSSI Reading
bits : 16 - 23 (8 bit)
access : read-only
DCOC Calibration Alpha
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_ALPHA_I : DCOC Calibration I-channel ALPHA constant
bits : 0 - 10 (11 bit)
access : read-only
DCOC_CAL_ALPHA_Q : DCOC_CAL_ALPHA_Q
bits : 16 - 26 (11 bit)
access : read-only
DCOC Calibration Beta Q
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_BETA_Q : DCOC_CAL_BETA_Q
bits : 0 - 16 (17 bit)
access : read-only
DCOC Calibration Beta I
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_BETA_I : DCOC_CAL_BETA_I
bits : 0 - 16 (17 bit)
access : read-only
DCOC Calibration Gamma
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_GAMMA_I : DCOC_CAL_GAMMA_I
bits : 0 - 15 (16 bit)
access : read-only
DCOC_CAL_GAMMA_Q : DCOC_CAL_GAMMA_Q
bits : 16 - 31 (16 bit)
access : read-only
DCOC Calibration IIR
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_IIR1A_IDX : DCOC Calibration IIR 1A Index
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
1/1
#01 : 1
1/4
#10 : 2
1/8
#11 : 3
1/16
End of enumeration elements list.
DCOC_CAL_IIR2A_IDX : DCOC Calibration IIR 2A Index
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
1/1
#01 : 1
1/4
#10 : 2
1/8
#11 : 3
1/16
End of enumeration elements list.
DCOC_CAL_IIR3A_IDX : DCOC Calibration IIR 3A Index
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
1/4
#01 : 1
1/8
#10 : 2
1/16
#11 : 3
1/32
End of enumeration elements list.
RSSI Control 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSI_USE_VALS : RSSI Values Selection
bits : 0 - 0 (1 bit)
access : read-write
RSSI_HOLD_SRC : RSSI Hold Source Selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 00
Access Address match
#01 : 01
Preamble Detect
#11 : 11
802.15.4 LQI done (1=freeze, 0=run AGC)
End of enumeration elements list.
RSSI_HOLD_EN : RSSI Hold Enable
bits : 3 - 3 (1 bit)
access : read-write
RSSI_IIR_CW_WEIGHT : RSSI IIR CW Weighting
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 0
Bypass
#01 : 1
1/8
#10 : 2
1/16
#11 : 3
1/32
End of enumeration elements list.
RSSI_N_WINDOW_AVG : RSSI N Window Average
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
No averaging
#01 : 1
Averaging window length is 2 samples
#10 : 2
Averaging window length is 4 samples
#11 : 3
Averaging window length is 8 samples
End of enumeration elements list.
RSSI_HOLD_DELAY : RSSI Hold Delay
bits : 10 - 15 (6 bit)
access : read-write
RSSI_IIR_WEIGHT : RSSI IIR Weighting
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Bypass
#0001 : 1
1/2
#0010 : 2
1/4
#0011 : 3
1/8
#0100 : 4
1/16
#0101 : 5
1/32
End of enumeration elements list.
RSSI_VLD_SETTLE : RSSI Valid Settle
bits : 20 - 22 (3 bit)
access : read-write
RSSI_ADJ : RSSI Adjustment
bits : 24 - 31 (8 bit)
access : read-write
DCOC Calibration Result
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_RES_I : DCOC Calibration Result - I Channel
bits : 0 - 11 (12 bit)
access : read-only
DCOC_CAL_RES_Q : DCOC Calibration Result - Q Channel
bits : 16 - 27 (12 bit)
access : read-only
DCOC Calibration Result
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_RES_I : DCOC Calibration Result - I Channel
bits : 0 - 11 (12 bit)
access : read-only
DCOC_CAL_RES_Q : DCOC Calibration Result - Q Channel
bits : 16 - 27 (12 bit)
access : read-only
DCOC Calibration Result
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCOC_CAL_RES_I : DCOC Calibration Result - I Channel
bits : 0 - 11 (12 bit)
access : read-only
DCOC_CAL_RES_Q : DCOC Calibration Result - Q Channel
bits : 16 - 27 (12 bit)
access : read-only
RX_DIG CCA ED LQI Control Register 0
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LQI_CORR_THRESH : LQI Correlation Threshold
bits : 0 - 7 (8 bit)
access : read-write
CORR_CNTR_THRESH : Correlation Count Threshold
bits : 8 - 15 (8 bit)
access : read-write
LQI_CNTR : LQI Counter
bits : 16 - 23 (8 bit)
access : read-write
SNR_ADJ : SNR calculation adjustment
bits : 24 - 29 (6 bit)
access : read-write
RX_DIG CCA ED LQI Control Register 1
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSI_NOISE_AVG_DELAY : RSSI Noise Averaging Delay
bits : 0 - 5 (6 bit)
access : read-write
RSSI_NOISE_AVG_FACTOR : RSSI Noise Averaging Factor
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 0
1
#001 : 1
64
#010 : 2
70
#011 : 3
128
#100 : 4
139
#101 : 5
256
#110 : 6
277
#111 : 7
512
End of enumeration elements list.
LQI_RSSI_WEIGHT : LQI RSSI Weight
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
2.0
#001 : 1
2.125
#010 : 2
2.25
#011 : 3
2.375
#100 : 4
2.5
#101 : 5
2.625
#110 : 6
2.75
#111 : 7
2.875
End of enumeration elements list.
LQI_RSSI_SENS : LQI RSSI Sensitivity
bits : 12 - 15 (4 bit)
access : read-write
SNR_LQI_DIS : SNR LQI Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
The RX_DIG CCA/ED/LQI block ignores the AA match input which starts an LQI measurement.
End of enumeration elements list.
SEL_SNR_MODE : Select SNR Mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SNR estimate
#1 : 1
Mapped correlation magnitude
End of enumeration elements list.
MEAS_TRANS_TO_IDLE : Measurement Transition to IDLE
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Module transitions to RSSI state
#1 : 1
Module transitions to IDLE state
End of enumeration elements list.
CCA1_ED_EN_DIS : CCA1_ED_EN Disable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
CCA1_ED_EN input is disabled
End of enumeration elements list.
MAN_MEAS_COMPLETE : Manual measurement complete
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Manually asserts the measurement complete signal for the RX_DIG CCA/ED/LQI blocks. Intended to be used only for debug.
End of enumeration elements list.
MAN_AA_MATCH : Manual AA Match
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Manually asserts the AA match signal for the RX_DIG CCA/ED/LQI and AGC blocks. Intended to be used only for debug.
End of enumeration elements list.
SNR_LQI_WEIGHT : SNR LQI Weight
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
0.0
#0001 : 1
1.0
#0010 : 2
1.125
#0011 : 3
1.25
#0100 : 4
1.375
#0101 : 5
1.5
#0110 : 6
1.625
#0111 : 7
1.75
#1000 : 8
1.875
#1001 : 9
2.0
#1010 : 10
2.125
#1011 : 11
2.25
#1100 : 12
2.375
#1101 : 13
2.5
#1110 : 14
2.625
#1111 : 15
2.75
End of enumeration elements list.
LQI_BIAS : LQI Bias.
bits : 28 - 31 (4 bit)
access : read-write
RX_DIG CCA ED LQI Status Register 0
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LQI_OUT : LQI output
bits : 0 - 7 (8 bit)
access : read-only
ED_OUT : ED output
bits : 8 - 15 (8 bit)
access : read-only
SNR_OUT : SNR output
bits : 16 - 23 (8 bit)
access : read-only
CCA1_STATE : CCA1 State
bits : 24 - 24 (1 bit)
access : read-only
MEAS_COMPLETE : Measurement Complete
bits : 25 - 25 (1 bit)
access : read-only
Receive Channel Filter Coefficient 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H0 : RX Channel Filter Coefficient 0
bits : 0 - 5 (6 bit)
access : read-write
Receive Channel Filter Coefficient 1
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H1 : RX Channel Filter Coefficient 1
bits : 0 - 5 (6 bit)
access : read-write
Receive Channel Filter Coefficient 2
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H2 : RX Channel Filter Coefficient 2
bits : 0 - 6 (7 bit)
access : read-write
Receive Channel Filter Coefficient 3
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H3 : RX Channel Filter Coefficient 3
bits : 0 - 6 (7 bit)
access : read-write
Receive Channel Filter Coefficient 4
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H4 : RX Channel Filter Coefficient 4
bits : 0 - 6 (7 bit)
access : read-write
Receive Channel Filter Coefficient 5
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H5 : RX Channel Filter Coefficient 5
bits : 0 - 6 (7 bit)
access : read-write
Receive Channel Filter Coefficient 6
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H6 : RX Channel Filter Coefficient 6
bits : 0 - 7 (8 bit)
access : read-write
Receive Channel Filter Coefficient 7
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H7 : RX Channel Filter Coefficient 7
bits : 0 - 7 (8 bit)
access : read-write
RSSI Control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSSI_OUT : RSSI Reading
bits : 24 - 31 (8 bit)
access : read-only
Receive Channel Filter Coefficient 8
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H8 : RX Channel Filter Coefficient 8
bits : 0 - 8 (9 bit)
access : read-write
Receive Channel Filter Coefficient 9
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H9 : RX Channel Filter Coefficient 9
bits : 0 - 8 (9 bit)
access : read-write
Receive Channel Filter Coefficient 10
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H10 : RX Channel Filter Coefficient 10
bits : 0 - 9 (10 bit)
access : read-write
Receive Channel Filter Coefficient 11
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CH_FILT_H11 : RX Channel Filter Coefficient 11
bits : 0 - 9 (10 bit)
access : read-write
AGC Manual AGC Index
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGC_MAN_IDX : AGC Manual Index
bits : 16 - 20 (5 bit)
access : read-write
AGC_MAN_IDX_EN : AGC Manual Index Enable
bits : 24 - 24 (1 bit)
access : read-write
AGC_DCOC_START_PT : AGC DCOC Start Point
bits : 25 - 25 (1 bit)
access : read-write
DC Residual Control
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_RESID_NWIN : DC Residual NWIN
bits : 0 - 6 (7 bit)
access : read-write
DC_RESID_ITER_FREEZE : DC Residual Iteration Freeze
bits : 8 - 11 (4 bit)
access : read-write
DC_RESID_ALPHA : DC Residual Alpha
bits : 12 - 14 (3 bit)
access : read-write
DC_RESID_DLY : DC Residual Delay
bits : 16 - 18 (3 bit)
access : read-write
DC_RESID_EXT_DC_EN : DC Residual External DC Enable
bits : 20 - 20 (1 bit)
access : read-write
DC_RESID_MIN_AGC_IDX : DC Residual Minimum AGC Table Index
bits : 24 - 28 (5 bit)
access : write-only
DC Residual Estimate
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DC_RESID_OFFSET_I : DC Residual Offset I
bits : 0 - 12 (13 bit)
access : read-only
DC_RESID_OFFSET_Q : DC Residual Offset Q
bits : 16 - 28 (13 bit)
access : read-only
RX RC Calibration Control0
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_RCCAL_OFFSET : BBA RC Calibration value offset
bits : 0 - 3 (4 bit)
access : read-write
BBA_RCCAL_MANUAL : BBA RC Calibration manual value
bits : 4 - 8 (5 bit)
access : read-write
BBA_RCCAL_DIS : BBA RC Calibration Disable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
BBA RC Calibration is enabled
#1 : 1
BBA RC Calibration is disabled
End of enumeration elements list.
RCCAL_SMP_DLY : RC Calibration Sample Delay
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
The comp_out signal is sampled 0 clk cycle after sample signal is deasserted
#01 : 01
The comp_out signal is sampled 1 clk cycle after sample signal is deasserted
#10 : 10
The comp_out signal is sampled 2 clk cycle after sample signal is deasserted
#11 : 11
The comp_out signal is sampled 3 clk cycle after sample signal is deasserted
End of enumeration elements list.
RCCAL_COMP_INV : RC Calibration comp_out Invert
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The comp_out signal polarity is NOT inverted
#1 : 1
The comp_out signal polarity is inverted
End of enumeration elements list.
TZA_RCCAL_OFFSET : TZA RC Calibration value offset
bits : 16 - 19 (4 bit)
access : read-write
TZA_RCCAL_MANUAL : TZA RC Calibration manual value
bits : 20 - 24 (5 bit)
access : read-write
TZA_RCCAL_DIS : TZA RC Calibration Disable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TZA RC Calibration is enabled
#1 : 1
TZA RC Calibration is disabled
End of enumeration elements list.
RX RC Calibration Control1
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC_RCCAL_OFFSET : ADC RC Calibration value offset
bits : 0 - 3 (4 bit)
access : read-write
ADC_RCCAL_MANUAL : ADC RC Calibration manual value
bits : 4 - 8 (5 bit)
access : read-write
ADC_RCCAL_DIS : ADC RC Calibration Disable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC RC Calibration is enabled
#1 : 1
ADC RC Calibration is disabled
End of enumeration elements list.
BBA2_RCCAL_OFFSET : BBA2 RC Calibration value offset
bits : 16 - 19 (4 bit)
access : read-write
BBA2_RCCAL_MANUAL : BBA2 RC Calibration manual value
bits : 20 - 24 (5 bit)
access : read-write
BBA2_RCCAL_DIS : BBA2 RC Calibration Disable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
BBA2 RC Calibration is enabled
#1 : 1
BBA2 RC Calibration is disabled
End of enumeration elements list.
RX RC Calibration Status
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCCAL_CODE : RC Calibration code
bits : 0 - 4 (5 bit)
access : read-only
ADC_RCCAL : ADC RC Calibration
bits : 5 - 9 (5 bit)
access : read-only
BBA2_RCCAL : BBA2 RC Calibration
bits : 10 - 14 (5 bit)
access : read-only
BBA_RCCAL : BBA RC Calibration
bits : 16 - 20 (5 bit)
access : read-only
TZA_RCCAL : TZA RC Calibration
bits : 21 - 25 (5 bit)
access : read-only
Aux PLL Frequency Calibration Control
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC_CAL_ADJUST_MANUAL : Aux PLL Frequency DAC Calibration Adjust Manual value
bits : 0 - 6 (7 bit)
access : read-write
AUXPLL_DAC_CAL_ADJUST_DIS : Aux PLL Frequency Calibration Disable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Calibration is enabled
#1 : 1
Calibration is disabled
End of enumeration elements list.
FCAL_RUN_CNT : Aux PLL Frequency Calibration Run Count
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Run count is 256 clock cycles
#1 : 1
Run count is 512 clock cycles
End of enumeration elements list.
FCAL_COMP_INV : Aux PLL Frequency Calibration Comparison Invert
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
(Default) The comparison associated with the count is not inverted.
#1 : 1
The comparison associated with the count is inverted
End of enumeration elements list.
FCAL_SMP_DLY : Aux PLL Frequency Calibration Sample Delay
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
The count signal is sampled 1 clk cycle after fcal_run signal is deasserted
#01 : 01
The count signal is sampled 2 clk cycle after fcal_run signal is deasserted
#10 : 10
The count signal is sampled 3 clk cycle after fcal_run signal is deasserted
#11 : 11
The count signal is sampled 4 clk cycle after fcal_run signal is deasserted
End of enumeration elements list.
DAC_CAL_ADJUST : Aux PLL DAC Calibration Adjust value
bits : 16 - 22 (7 bit)
access : read-only
Aux PLL Frequency Calibration Count 6
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAL_COUNT_6 : Aux PLL Frequency Calibration Count 6
bits : 0 - 9 (10 bit)
access : read-only
FCAL_BESTDIFF : Aux PLL Frequency Calibration Best Difference
bits : 16 - 25 (10 bit)
access : read-only
Aux PLL Frequency Calibration Count 5 and 4
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAL_COUNT_4 : Aux PLL Frequency Calibration Count 4
bits : 0 - 9 (10 bit)
access : read-only
FCAL_COUNT_5 : Aux PLL Frequency Calibration Count 5
bits : 16 - 25 (10 bit)
access : read-only
Aux PLL Frequency Calibration Count 3 and 2
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAL_COUNT_2 : Aux PLL Frequency Calibration Count 2
bits : 0 - 9 (10 bit)
access : read-only
FCAL_COUNT_3 : Aux PLL Frequency Calibration Count 3
bits : 16 - 25 (10 bit)
access : read-only
Aux PLL Frequency Calibration Count 1 and 0
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAL_COUNT_0 : Frequency Calibration Count 0
bits : 0 - 9 (10 bit)
access : read-only
FCAL_COUNT_1 : Frequency Calibration Count 1
bits : 16 - 25 (10 bit)
access : read-only
RXDIG DFT
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFT_TONE_FREQ : DFT Tone Generator Frequency
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
1/64 of the ref osc frequency (500kHz for 32MHz ref osc)
#001 : 1
1/128 of the ref osc frequency (250kHz for 32MHz ref osc)
#010 : 2
1/256 of the ref osc frequency (125kHz for 32MHz ref osc)
#011 : 3
1/512 of the ref osc frequency (62.5kHz for 32MHz ref osc)
#100 : 4
1/1024 of the ref osc frequency (31.25kHz for 32MHz ref osc)
End of enumeration elements list.
DFT_TONE_SCALE : DFT Tone Generator Scale
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DFT tone generator uses 3/4 of the DC offset correction DAC range.
#1 : 1
The DFT tone generator uses 1/2 of the DC offset correction DAC range.
End of enumeration elements list.
DFT_TONE_TZA_EN : DFT Tone Generator TZA Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DCOC controls the TZA DC offset correction DACs
#1 : 1
A tone is generated using the TZA DC offset correction DACs.
End of enumeration elements list.
DFT_TONE_BBA_EN : DFT Tone Generator BBA Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DCOC controls the BBA DC offset correction DACs
#1 : 1
A tone is generated using the BBA DC offset correction DACs.
End of enumeration elements list.
RSSI DFT
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFT_MAG : RSSI MAG
bits : 0 - 12 (13 bit)
access : read-only
DFT_NOISE : RSSI MAG
bits : 16 - 28 (13 bit)
access : read-only
DCOC Control 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_MIDPWR_TRK_DIS : DCOC Mid Power Tracking Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tracking corrections are enabled as determined by DCOC_CORRECT_SRC and DCOC_TRK_MIN_AGC_IDX.
#1 : 1
Tracking corrections are disabled when either the TZA or BBA lo peak detector asserts.
End of enumeration elements list.
DCOC_MAN : DCOC Manual Override
bits : 1 - 1 (1 bit)
access : read-write
DCOC_TRK_EST_OVR : Override for the DCOC tracking estimator
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The tracking estimator is enabled only as needed by the corrector
#1 : 1
The tracking estimator remains enabled whenever the DCOC is active
End of enumeration elements list.
DCOC_CORRECT_SRC : DCOC Corrector Source
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If correction is enabled, the DCOC will use only the DCOC calibration table to correct the DC offset.
#1 : 1
If correction is enabled, the DCOC will use the DCOC calibration table and then the tracking estimator to correct the DC offset.
End of enumeration elements list.
DCOC_CORRECT_EN : DCOC Correction Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Correction disabled. The DCOC will not correct the DC offset.
#1 : 1
Correction enabled. The DCOC will use the TZA and BBA DACs, and apply digital corrections (if DCOC_CORRECT_SRC=1) to correct the DC offset.
End of enumeration elements list.
TRACK_FROM_ZERO : Track from Zero
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Track from current I/Q sample.
#1 : 1
Track from zero.
End of enumeration elements list.
BBA_CORR_POL : BBA Correction Polarity
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity.
#1 : 1
Negative polarity. This should be set if the ADC output is inverted, or if the BBA DACs were implemented with negative polarity.
End of enumeration elements list.
TZA_CORR_POL : TZA Correction Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity.
#1 : 1
Negative polarity. This should be set if the ADC output is inverted, or if the TZA DACs were implemented with negative polarity.
End of enumeration elements list.
DCOC_CAL_DURATION : DCOC Calibration Duration
bits : 8 - 12 (5 bit)
access : read-write
DCOC_CORR_DLY : DCOC Correction Delay
bits : 16 - 20 (5 bit)
access : read-write
DCOC_CORR_HOLD_TIME : DCOC Correction Hold Time
bits : 24 - 30 (7 bit)
access : read-write
Enumeration:
#1111111 : 127
The DC correction is not frozen.
End of enumeration elements list.
DCOC Control 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_SIGN_SCALE_IDX : DCOC Sign Scaling
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
1/8
#01 : 01
1/16
#10 : 10
1/32
#11 : 11
1/64
End of enumeration elements list.
DCOC_ALPHAC_SCALE_IDX : DCOC Alpha-C Scaling
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
#000 : 000
1/2
#001 : 001
1/4
#010 : 010
1/8
#011 : 011
1/16
#100 : 100
1/32
#101 : 101
1/64
End of enumeration elements list.
DCOC_ALPHA_RADIUS_IDX : Alpha-R Scaling
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
1
#001 : 001
1/2
#010 : 010
1/4
#011 : 011
1/8
#100 : 100
1/16
#101 : 101
1/32
#110 : 110
1/64
End of enumeration elements list.
DCOC_TRK_EST_GS_CNT : DCOC Tracking Estimator Gearshift Count
bits : 12 - 14 (3 bit)
access : read-write
DCOC_SIGN_SCALE_GS_IDX : DCOC Sign Scaling for Gearshift
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1/8
#01 : 01
1/16
#10 : 10
1/32
#11 : 11
1/64
End of enumeration elements list.
DCOC_ALPHAC_SCALE_GS_IDX : DCOC Alpha-C Scaling for Gearshift
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
#000 : 000
1/2
#001 : 001
1/4
#010 : 010
1/8
#011 : 011
1/16
#100 : 100
1/32
#101 : 101
1/64
End of enumeration elements list.
DCOC_ALPHA_RADIUS_GS_IDX : Alpha-R Scaling for Gearshift
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
1
#001 : 001
1/2
#010 : 010
1/4
#011 : 011
1/8
#100 : 100
1/16
#101 : 101
1/32
#110 : 110
1/64
End of enumeration elements list.
DCOC_TRK_MIN_AGC_IDX : DCOC Tracking Minimum AGC Table Index
bits : 24 - 28 (5 bit)
access : read-write
DCOC DAC Initialization
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_DCOC_INIT_I : DCOC BBA Init I
bits : 0 - 5 (6 bit)
access : read-write
BBA_DCOC_INIT_Q : DCOC BBA Init Q
bits : 8 - 13 (6 bit)
access : read-write
TZA_DCOC_INIT_I : DCOC TZA Init I
bits : 16 - 23 (8 bit)
access : read-write
TZA_DCOC_INIT_Q : DCOC TZA Init Q
bits : 24 - 31 (8 bit)
access : read-write
DCOC Digital Correction Manual Override
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIG_DCOC_INIT_I : DCOC DIG Init I
bits : 0 - 11 (12 bit)
access : read-write
DIG_DCOC_INIT_Q : DCOC DIG Init Q
bits : 16 - 27 (12 bit)
access : read-write
DCOC Calibration Gain
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_CAL_GAIN1 : DCOC BBA Calibration Gain 1
bits : 8 - 11 (4 bit)
access : read-write
DCOC_LNA_CAL_GAIN1 : DCOC LNA Calibration Gain 1
bits : 12 - 15 (4 bit)
access : read-write
DCOC_BBA_CAL_GAIN2 : DCOC BBA Calibration Gain 2
bits : 16 - 19 (4 bit)
access : read-write
DCOC_LNA_CAL_GAIN2 : DCOC LNA Calibration Gain 2
bits : 20 - 23 (4 bit)
access : read-write
DCOC_BBA_CAL_GAIN3 : DCOC BBA Calibration Gain 3
bits : 24 - 27 (4 bit)
access : read-write
DCOC_LNA_CAL_GAIN3 : DCOC LNA Calibration Gain 3
bits : 28 - 31 (4 bit)
access : read-write
DCOC Status
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BBA_DCOC_I : DCOC BBA DAC I
bits : 0 - 5 (6 bit)
access : read-only
BBA_DCOC_Q : DCOC BBA DAC Q
bits : 8 - 13 (6 bit)
access : read-only
TZA_DCOC_I : DCOC TZA DAC I
bits : 16 - 23 (8 bit)
access : read-only
TZA_DCOC_Q : DCOC TZA DAC Q
bits : 24 - 31 (8 bit)
access : read-only
DCOC DC Estimate
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DC_EST_I : DCOC DC Estimate I
bits : 0 - 11 (12 bit)
access : read-only
DC_EST_Q : DCOC DC Estimate Q
bits : 16 - 27 (12 bit)
access : read-only
AGC Control 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOW_AGC_EN : Slow AGC Enable
bits : 0 - 0 (1 bit)
access : read-write
SLOW_AGC_SRC : Slow AGC Source Selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Access Address match (for active protocol)
#01 : 1
Preamble Detect (for active protocol)
#10 : 2
Fast AGC expire timer
End of enumeration elements list.
AGC_FREEZE_EN : AGC Freeze Enable
bits : 3 - 3 (1 bit)
access : read-write
AGC_FREEZE_PRE_OR_AA : AGC Freeze Source Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access Address match (for active protocol)
#1 : 1
Preamble Detect (for active protocol)
End of enumeration elements list.
AGC_UP_EN : AGC Up Enable
bits : 6 - 6 (1 bit)
access : read-write
AGC_UP_SRC : AGC Up Source
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDET LO
#1 : 1
RSSI
End of enumeration elements list.
AGC_DOWN_BBA_STEP_SZ : AGC_DOWN_BBA_STEP_SZ
bits : 8 - 11 (4 bit)
access : read-write
AGC_DOWN_LNA_STEP_SZ : AGC_DOWN_LNA_STEP_SZ
bits : 12 - 15 (4 bit)
access : read-write
AGC_UP_RSSI_THRESH : AGC UP RSSI Threshold
bits : 16 - 23 (8 bit)
access : read-write
AGC_DOWN_RSSI_THRESH : AGC DOWN RSSI Threshold
bits : 24 - 31 (8 bit)
access : read-write
DCOC Calibration Reciprocals
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_TMP_CALC_RECIP : DCOC Calculation Reciprocal
bits : 0 - 10 (11 bit)
access : read-write
ALPHA_CALC_RECIP : Alpha Calculation Reciprocal
bits : 16 - 26 (11 bit)
access : read-write
IQMC Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQMC_CAL_EN : IQ Mismatch Cal Enable
bits : 0 - 0 (1 bit)
access : read-write
IQMC_NUM_ITER : IQ Mismatch Cal Num Iter
bits : 8 - 15 (8 bit)
access : read-write
IQMC_DC_GAIN_ADJ : IQ Mismatch Correction DC Gain Coeff
bits : 16 - 26 (11 bit)
access : read-write
IQMC Calibration
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IQMC_GAIN_ADJ : IQ Mismatch Correction Gain Coeff
bits : 0 - 10 (11 bit)
access : read-write
IQMC_PHASE_ADJ : IQ Mismatch Correction Phase Coeff
bits : 16 - 27 (12 bit)
access : read-write
LNA_GAIN Step Values 3..0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_VAL_0 : LNA_GAIN step 0
bits : 0 - 7 (8 bit)
access : read-write
LNA_GAIN_VAL_1 : LNA_GAIN step 1
bits : 8 - 15 (8 bit)
access : read-write
LNA_GAIN_VAL_2 : LNA_GAIN step 2
bits : 16 - 23 (8 bit)
access : read-write
LNA_GAIN_VAL_3 : LNA_GAIN step 3
bits : 24 - 31 (8 bit)
access : read-write
LNA_GAIN Step Values 7..4
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_VAL_4 : LNA_GAIN step 4
bits : 0 - 7 (8 bit)
access : read-write
LNA_GAIN_VAL_5 : LNA_GAIN step 5
bits : 8 - 15 (8 bit)
access : read-write
LNA_GAIN_VAL_6 : LNA_GAIN step 6
bits : 16 - 23 (8 bit)
access : read-write
LNA_GAIN_VAL_7 : LNA_GAIN step 7
bits : 24 - 31 (8 bit)
access : read-write
LNA_GAIN Step Values 8
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_VAL_8 : LNA_GAIN step 8
bits : 0 - 7 (8 bit)
access : read-write
LNA_GAIN_VAL_9 : LNA_GAIN step 9
bits : 8 - 15 (8 bit)
access : read-write
BBA Resistor Tune Values 7..0
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_RES_TUNE_VAL_0 : BBA Resistor Tune Step 0
bits : 0 - 3 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_1 : BBA Resistor Tune Step 1
bits : 4 - 7 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_2 : BBA Resistor Tune Step 2
bits : 8 - 11 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_3 : BBA Resistor Tune Step 3
bits : 12 - 15 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_4 : BBA Resistor Tune Step 4
bits : 16 - 19 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_5 : BBA Resistor Tune Step 5
bits : 20 - 23 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_6 : BBA Resistor Tune Step 6
bits : 24 - 27 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_7 : BBA Resistor Tune Step 7
bits : 28 - 31 (4 bit)
access : read-write
BBA Resistor Tune Values 10..8
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_RES_TUNE_VAL_8 : BBA Resistor Tune Step 8
bits : 0 - 3 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_9 : BBA Resistor Tune Step 9
bits : 4 - 7 (4 bit)
access : read-write
BBA_RES_TUNE_VAL_10 : BBA Resistor Tune Step 10
bits : 8 - 11 (4 bit)
access : read-write
LNA Linear Gain Values 2..0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_LIN_VAL_0 : LNA Linear Gain Step 0
bits : 0 - 9 (10 bit)
access : read-write
LNA_GAIN_LIN_VAL_1 : LNA Linear Gain Step 1
bits : 10 - 19 (10 bit)
access : read-write
LNA_GAIN_LIN_VAL_2 : LNA Linear Gain Step 2
bits : 20 - 29 (10 bit)
access : read-write
LNA Linear Gain Values 5..3
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_LIN_VAL_3 : LNA Linear Gain Step 3
bits : 0 - 9 (10 bit)
access : read-write
LNA_GAIN_LIN_VAL_4 : LNA Linear Gain Step 4
bits : 10 - 19 (10 bit)
access : read-write
LNA_GAIN_LIN_VAL_5 : LNA Linear Gain Step 5
bits : 20 - 29 (10 bit)
access : read-write
LNA Linear Gain Values 8..6
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_LIN_VAL_6 : LNA Linear Gain Step 6
bits : 0 - 9 (10 bit)
access : read-write
LNA_GAIN_LIN_VAL_7 : LNA Linear Gain Step 7
bits : 10 - 19 (10 bit)
access : read-write
LNA_GAIN_LIN_VAL_8 : LNA Linear Gain Step 8
bits : 20 - 29 (10 bit)
access : read-write
LNA Linear Gain Values 9
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LNA_GAIN_LIN_VAL_9 : LNA Linear Gain Step 9
bits : 0 - 9 (10 bit)
access : read-write
BBA Resistor Tune Values 3..0
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_RES_TUNE_LIN_VAL_0 : BBA Resistor Tune Linear Gain Step 0
bits : 0 - 7 (8 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_1 : BBA Resistor Tune Linear Gain Step 1
bits : 8 - 15 (8 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_2 : BBA Resistor Tune Linear Gain Step 2
bits : 16 - 23 (8 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_3 : BBA Resistor Tune Linear Gain Step 3
bits : 24 - 31 (8 bit)
access : read-write
BBA Resistor Tune Values 7..4
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_RES_TUNE_LIN_VAL_4 : BBA Resistor Tune Linear Gain Step 4
bits : 0 - 7 (8 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_5 : BBA Resistor Tune Linear Gain Step 5
bits : 8 - 15 (8 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_6 : BBA Resistor Tune Linear Gain Step 6
bits : 16 - 23 (8 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_7 : BBA Resistor Tune Linear Gain Step 7
bits : 24 - 31 (8 bit)
access : read-write
BBA Resistor Tune Values 10..8
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_RES_TUNE_LIN_VAL_8 : BBA Resistor Tune Linear Gain Step 8
bits : 0 - 9 (10 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_9 : BBA Resistor Tune Linear Gain Step 9
bits : 10 - 19 (10 bit)
access : read-write
BBA_RES_TUNE_LIN_VAL_10 : BBA Resistor Tune Linear Gain Step 10
bits : 20 - 29 (10 bit)
access : read-write
AGC Control 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_ALT_CODE : BBA_ALT_CODE
bits : 0 - 3 (4 bit)
access : read-write
LNA_ALT_CODE : LNA_ALT_CODE
bits : 4 - 11 (8 bit)
access : read-write
LNA_USER_GAIN : LNA_USER_GAIN
bits : 12 - 15 (4 bit)
access : read-write
BBA_USER_GAIN : BBA_USER_GAIN
bits : 16 - 19 (4 bit)
access : read-write
USER_LNA_GAIN_EN : User LNA Gain Enable
bits : 20 - 20 (1 bit)
access : read-write
USER_BBA_GAIN_EN : User BBA Gain Enable
bits : 21 - 21 (1 bit)
access : read-write
PRESLOW_EN : Pre-slow Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-slow is disabled.
#1 : 1
Pre-slow is enabled.
End of enumeration elements list.
LNA_GAIN_SETTLE_TIME : LNA_GAIN_SETTLE_TIME
bits : 24 - 31 (8 bit)
access : read-write
AGC Gain Tables Step 03..00
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_00 : BBA Gain 00
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_00 : LNA Gain 00
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_01 : BBA Gain 01
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_01 : LNA Gain 01
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_02 : BBA Gain 02
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_02 : LNA Gain 02
bits : 20 - 23 (4 bit)
access : read-write
BBA_GAIN_03 : BBA Gain 03
bits : 24 - 27 (4 bit)
access : read-write
LNA_GAIN_03 : LNA Gain 03
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 07..04
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_04 : BBA Gain 04
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_04 : LNA Gain 04
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_05 : BBA Gain 05
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_05 : LNA Gain 05
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_06 : BBA Gain 06
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_06 : LNA Gain 06
bits : 20 - 23 (4 bit)
access : read-write
BBA_GAIN_07 : BBA Gain 07
bits : 24 - 27 (4 bit)
access : read-write
LNA_GAIN_07 : LNA Gain 07
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 11..08
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_08 : BBA Gain 08
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_08 : LNA Gain 08
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_09 : BBA Gain 09
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_09 : LNA Gain 09
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_10 : BBA Gain 10
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_10 : LNA Gain 10
bits : 20 - 23 (4 bit)
access : read-write
BBA_GAIN_11 : BBA Gain 11
bits : 24 - 27 (4 bit)
access : read-write
LNA_GAIN_11 : LNA Gain 11
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 15..12
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_12 : BBA Gain 12
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_12 : LNA Gain 12
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_13 : BBA Gain 13
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_13 : LNA Gain 13
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_14 : BBA Gain 14
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_14 : LNA Gain 14
bits : 20 - 23 (4 bit)
access : read-write
BBA_GAIN_15 : BBA Gain 15
bits : 24 - 27 (4 bit)
access : read-write
LNA_GAIN_15 : LNA Gain 15
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 19..16
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_16 : BBA Gain 16
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_16 : LNA Gain 16
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_17 : BBA Gain 17
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_17 : LNA Gain 17
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_18 : BBA Gain 18
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_18 : LNA Gain 18
bits : 20 - 23 (4 bit)
access : read-write
BBA_GAIN_19 : BBA Gain 193
bits : 24 - 27 (4 bit)
access : read-write
LNA_GAIN_19 : LNA Gain 19
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 23..20
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_20 : BBA Gain 20
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_20 : LNA Gain 20
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_21 : BBA Gain 21
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_21 : LNA Gain 21
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_22 : BBA Gain 22
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_22 : LNA Gain 22
bits : 20 - 23 (4 bit)
access : read-write
BBA_GAIN_23 : BBA Gain 23
bits : 24 - 27 (4 bit)
access : read-write
LNA_GAIN_23 : LNA Gain 23
bits : 28 - 31 (4 bit)
access : read-write
AGC Gain Tables Step 26..24
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_GAIN_24 : BBA Gain 24
bits : 0 - 3 (4 bit)
access : read-write
LNA_GAIN_24 : LNA Gain 24
bits : 4 - 7 (4 bit)
access : read-write
BBA_GAIN_25 : BBA Gain 25
bits : 8 - 11 (4 bit)
access : read-write
LNA_GAIN_25 : LNA Gain 25
bits : 12 - 15 (4 bit)
access : read-write
BBA_GAIN_26 : BBA Gain 26
bits : 16 - 19 (4 bit)
access : read-write
LNA_GAIN_26 : LNA Gain 26
bits : 20 - 23 (4 bit)
access : read-write
DCOC Offset
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
AGC Control 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BBA_PDET_RST : BBA PDET Reset
bits : 0 - 0 (1 bit)
access : read-write
TZA_PDET_RST : TZA PDET Reset
bits : 1 - 1 (1 bit)
access : read-write
MAN_PDET_RST : MAN PDET Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The peak detector reset signals are controlled automatically by the AGC.
#1 : 1
The BBA_PDET_RST and TZA_PDET_RST are used to manually control the peak detector reset signals.
End of enumeration elements list.
BBA_GAIN_SETTLE_TIME : BBA Gain Settle Time
bits : 4 - 11 (8 bit)
access : read-write
BBA_PDET_SEL_LO : BBA PDET Threshold Low
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.600V
#001 : 001
0.615V
#010 : 010
0.630V
#011 : 011
0.645V
#100 : 100
0.660V
#101 : 101
0.675V
#110 : 110
0.690V
#111 : 111
0.705V
End of enumeration elements list.
BBA_PDET_SEL_HI : BBA PDET Threshold High
bits : 15 - 17 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.600V
#001 : 001
0.795V
#010 : 010
0.900V
#011 : 011
0.945V
#100 : 100
1.005V
#101 : 101
1.050V
#110 : 110
1.095V
#111 : 111
1.155V
End of enumeration elements list.
TZA_PDET_SEL_LO : TZA PDET Threshold Low
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.600V
#001 : 001
0.615V
#010 : 010
0.630V
#011 : 011
0.645V
#100 : 100
0.660V
#101 : 101
0.675V
#110 : 110
0.690V
#111 : 111
0.705V
End of enumeration elements list.
TZA_PDET_SEL_HI : TZA PDET Threshold High
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
0.60V
#001 : 001
0.63V
#010 : 010
0.66V
#011 : 011
0.69V
#100 : 100
0.72V
#101 : 101
0.75V
#110 : 110
0.78V
#111 : 111
0.81V
End of enumeration elements list.
AGC_FAST_EXPIRE : AGC Fast Expire
bits : 24 - 29 (6 bit)
access : read-write
LNA_LG_ON_OVR : LNA_LG_ON override
bits : 30 - 30 (1 bit)
access : read-write
LNA_HG_ON_OVR : LNA_HG_ON override
bits : 31 - 31 (1 bit)
access : read-write
DCOC Offset
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
DCOC Offset
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCOC_BBA_OFFSET_I : DCOC BBA I-channel offset
bits : 0 - 5 (6 bit)
access : read-write
DCOC_BBA_OFFSET_Q : DCOC BBA Q-channel offset
bits : 8 - 13 (6 bit)
access : read-write
DCOC_TZA_OFFSET_I : DCOC TZA I-channel offset
bits : 16 - 23 (8 bit)
access : read-write
DCOC_TZA_OFFSET_Q : DCOC TZA Q-channel offset
bits : 24 - 31 (8 bit)
access : read-write
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