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XCVR_ANA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BB_LDO_1

RX_LNA

RX_TZA

RX_AUXPLL

SY_CTRL_1

SY_CTRL_2

TX_DAC_PA

BALUN_TX

BALUN_RX

DFT_OBSV_1

DFT_OBSV_2

BB_LDO_2

RX_ADC

RX_BBA


BB_LDO_1

RF Analog Baseband LDO Control 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BB_LDO_1 BB_LDO_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BB_LDO_ADCDAC_BYP BB_LDO_ADCDAC_DIAGSEL BB_LDO_ADCDAC_SPARE BB_LDO_ADCDAC_TRIM BB_LDO_BBA_BYP BB_LDO_BBA_DIAGSEL BB_LDO_BBA_SPARE BB_LDO_BBA_TRIM BB_LDO_FDBK_BYP BB_LDO_FDBK_DIAGSEL BB_LDO_FDBK_SPARE BB_LDO_FDBK_TRIM BB_LDO_HF_BYP BB_LDO_HF_DIAGSEL BB_LDO_HF_SPARE BB_LDO_HF_TRIM

BB_LDO_ADCDAC_BYP : rmap_bb_ldo_adcdac_byp
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bypass disabled.

#1 : 1

Bypass enabled

End of enumeration elements list.

BB_LDO_ADCDAC_DIAGSEL : rmap_bb_ldo_adcdac_diagsel
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_ADCDAC_SPARE : rmap_bb_ldo_adcdac_spare[1:0]
bits : 2 - 3 (2 bit)
access : read-write

BB_LDO_ADCDAC_TRIM : rmap_bb_ldo_adcdac_trim[2:0]
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 000

1.20 V ( Default )

#001 : 001

1.25 V

#010 : 010

1.28 V

#011 : 011

1.33 V

#100 : 100

1.40 V

#101 : 101

1.44 V

#110 : 110

1.50 V

#111 : 111

1.66 V

End of enumeration elements list.

BB_LDO_BBA_BYP : rmap_bb_ldo_bba_byp
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bypass disabled.

#1 : 1

Bypass enabled

End of enumeration elements list.

BB_LDO_BBA_DIAGSEL : rmap_bb_ldo_bba_diagsel
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_BBA_SPARE : rmap_bb_ldo_bba_spare[1:0]
bits : 10 - 11 (2 bit)
access : read-write

BB_LDO_BBA_TRIM : rmap_bb_ldo_bba_trim[2:0]
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

1.20 V ( Default )

#001 : 1

1.25 V

#010 : 2

1.28 V

#011 : 3

1.33 V

#100 : 4

1.40 V

#101 : 5

1.44 V

#110 : 6

1.50 V

#111 : 7

1.66 V

End of enumeration elements list.

BB_LDO_FDBK_BYP : rmap_bb_ldo_fdbk_byp
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bypass disabled.

#1 : 1

Bypass enabled

End of enumeration elements list.

BB_LDO_FDBK_DIAGSEL : rmap_bb_ldo_fdbk_diagsel
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_FDBK_SPARE : rmap_bb_ldo_fdbk_spare[1:0]
bits : 18 - 19 (2 bit)
access : read-write

BB_LDO_FDBK_TRIM : rmap_bb_ldo_fdbk_trim[2:0]
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

1.2/1.176 V ( Default )

#001 : 1

1.138/1.115 V

#010 : 2

1.085/1.066 V

#011 : 3

1.04/1.025 V

#100 : 4

1.28/1.25 V

#101 : 5

1.4/1.35 V

#110 : 6

1.55/1.4 V

#111 : 7

1.78/1.4 V

End of enumeration elements list.

BB_LDO_HF_BYP : rmap_bb_ldo_hf_byp
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bypass disabled.

#1 : 1

Bypass enabled

End of enumeration elements list.

BB_LDO_HF_DIAGSEL : rmap_bb_ldo_hf_diagsel
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_HF_SPARE : rmap_bb_ldo_hf_spare[1:0]
bits : 26 - 27 (2 bit)
access : read-write

BB_LDO_HF_TRIM : rmap_bb_ldo_hf_trim[2:0]
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#000 : 0

1.20 V ( Default )

#001 : 1

1.25 V

#010 : 2

1.28 V

#011 : 3

1.33 V

#100 : 4

1.40 V

#101 : 5

1.44 V

#110 : 6

1.50 V

#111 : 7

1.66 V

End of enumeration elements list.


RX_LNA

RF Analog LNA Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_LNA RX_LNA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_LNA_BUMP RX_LNA_HG_DIAGSEL RX_LNA_HIZ_ENABLE RX_LNA_LG_DIAGSEL RX_LNA_SPARE RX_MIXER_BUMP RX_MIXER_SPARE

RX_LNA_BUMP : rmap_rx_lna_bump[3:0]
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Default

#0001 : 1

-25%

#0010 : 2

+50%

#0011 : 3

+25%

#0100 : 4

CM 480mV

#1000 : 8

CM 600mV

#1100 : 12

CM 660mV

End of enumeration elements list.

RX_LNA_HG_DIAGSEL : rmap_rx_lna_hg_diagsel
bits : 4 - 4 (1 bit)
access : read-write

RX_LNA_HIZ_ENABLE : rmap_rx_lna_hiZ_enable
bits : 5 - 5 (1 bit)
access : read-write

RX_LNA_LG_DIAGSEL : rmap_rx_lna_lg_diagsel
bits : 6 - 6 (1 bit)
access : read-write

RX_LNA_SPARE : rmap_rx_lna_spare[1:0]
bits : 8 - 9 (2 bit)
access : read-write

RX_MIXER_BUMP : rmap_rx_mixer_bump[3:0]
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0

825mV (Default)

#0001 : 1

750mV

#0010 : 2

900mV

#0011 : 3

975mV

End of enumeration elements list.

RX_MIXER_SPARE : rmap_rx_mixer_spare
bits : 20 - 20 (1 bit)
access : read-write


RX_TZA

RF Analog TZA Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_TZA RX_TZA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_TZA_BW_SEL RX_TZA_CUR_BUMP RX_TZA_GAIN_BUMP RX_TZA_SPARE RX_TZA1_DIAGSEL RX_TZA2_DIAGSEL RX_TZA3_DIAGSEL RX_TZA4_DIAGSEL

RX_TZA_BW_SEL : rmap_rx_tza_bw_sel[2:0]
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

1000K

#001 : 001

900K

#010 : 010

800K

#011 : 011

700K Default

#100 : 100

600K

#101 : 101

500K

End of enumeration elements list.

RX_TZA_CUR_BUMP : rmap_rx_tza_cur_bump
bits : 3 - 3 (1 bit)
access : read-write

RX_TZA_GAIN_BUMP : rmap_rx_tza_gain_bump
bits : 4 - 4 (1 bit)
access : read-write

RX_TZA_SPARE : rmap_rx_tza_spare[5:0]
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

#0 : 00

600mV (Default)

#1 : 01

675mV

#10 : 10

450mV

#11 : 11

525mV

End of enumeration elements list.

RX_TZA1_DIAGSEL : rmap_rx_tza1_diagsel
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_TZA2_DIAGSEL : rmap_rx_tza2_diagsel
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_TZA3_DIAGSEL : rmap_rx_tza3_diagsel
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_TZA4_DIAGSEL : rmap_rx_tza4_diagsel
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.


RX_AUXPLL

RF Analog Aux PLL Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_AUXPLL RX_AUXPLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIAS_TRIM DIAGSEL1 DIAGSEL2 LF_CNTL SPARE VCO_DAC_REF_ADJUST VTUNE_TESTMODE RXTX_BAL_BIAST RXTX_BAL_SPARE RXTX_RCCAL_DIAGSEL

BIAS_TRIM : rmap_rxtx_auxpll_bias_trim[2:0]
bits : 0 - 2 (3 bit)
access : read-write

DIAGSEL1 : rmap_rxtx_auxpll_diagsel1
bits : 3 - 3 (1 bit)
access : read-write

DIAGSEL2 : rmap_rxtx_auxpll_diagsel2
bits : 4 - 4 (1 bit)
access : read-write

LF_CNTL : rmap_rxtx_auxpll_lf_cntl[2:0]
bits : 5 - 7 (3 bit)
access : read-write

SPARE : rmap_rxtx_auxpll_spare[3:0]
bits : 8 - 11 (4 bit)
access : read-write

VCO_DAC_REF_ADJUST : rmap_rxtx_auxpll_vco_dac_ref_adjust[3:0]
bits : 12 - 15 (4 bit)
access : read-write

VTUNE_TESTMODE : rmap_rxtx_auxpll_vtune_testmode
bits : 16 - 16 (1 bit)
access : read-write

RXTX_BAL_BIAST : rmap_rxtx_bal_biast[1:0]
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

0.6

#01 : 1

0.4

#10 : 2

0.9

#11 : 3

1.2

End of enumeration elements list.

RXTX_BAL_SPARE : rmap_rxtx_bal_spare[2:0]
bits : 24 - 26 (3 bit)
access : read-write

RXTX_RCCAL_DIAGSEL : rmap_rxtx_rccal_diagsel
bits : 28 - 28 (1 bit)
access : read-write


SY_CTRL_1

RF Analog Synthesizer Control 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SY_CTRL_1 SY_CTRL_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SY_DIVN_SPARE SY_FCAL_SPARE SY_LO_BUMP_RTLO_FDBK SY_LO_BUMP_RTLO_RX SY_LO_BUMP_RTLO_TX SY_LO_DIAGSEL SY_LO_SPARE SY_LPF_FILT_CTRL SY_LPF_SPARE SY_PD_DIAGSEL SY_PD_PCH_TUNE SY_PD_PCH_SEL SY_PD_SPARE SY_PD_VTUNE_OVERRIDE_TEST_MODE

SY_DIVN_SPARE : rmap_sy_divn_spare
bits : 0 - 0 (1 bit)
access : read-write

SY_FCAL_SPARE : rmap_sy_fcal_spare
bits : 1 - 1 (1 bit)
access : read-write

SY_LO_BUMP_RTLO_FDBK : rmap_sy_lo_bump_rtlo_fdbk[1:0]
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

1.045 V

#01 : 1

1.084 V

#10 : 2

1.097 V

#11 : 3

1.10 V

End of enumeration elements list.

SY_LO_BUMP_RTLO_RX : rmap_sy_lo_bump_rtlo_rx[1:0]
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

1.051/1.037 V

#01 : 1

1.082/1.075 V

#10 : 2

1.092/1.088 V

#11 : 3

1.098/1.094 V

End of enumeration elements list.

SY_LO_BUMP_RTLO_TX : rmap_sy_lo_bump_rtlo_tx[1:0]
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

1.071/1.065 V

#01 : 1

1.092/1.090 V

#10 : 2

1.099/1.098 V

#11 : 3

1.10/1.1 V

End of enumeration elements list.

SY_LO_DIAGSEL : rmap_sy_lo_diagsel
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

SY_LO_SPARE : rmap_sy_lo_spare[2:0]
bits : 12 - 14 (3 bit)
access : read-write

SY_LPF_FILT_CTRL : rmap_sy_lpf_filt_ctrl[2:0]
bits : 16 - 18 (3 bit)
access : read-write

SY_LPF_SPARE : rmap_sy_lpf_spare
bits : 19 - 19 (1 bit)
access : read-write

SY_PD_DIAGSEL : rmap_sy_pd_diagsel
bits : 20 - 20 (1 bit)
access : read-write

SY_PD_PCH_TUNE : rmap_sy_pd_pch_tune[1:0]
bits : 21 - 22 (2 bit)
access : read-write

SY_PD_PCH_SEL : rmap_sy_pd_pch_sel
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

inverter based precharge

#1 : 1

resistor divider based precharge

End of enumeration elements list.

SY_PD_SPARE : rmap_sy_pd_spare[1:0]
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Default

#01 : 1

PD output is pulled down.

End of enumeration elements list.

SY_PD_VTUNE_OVERRIDE_TEST_MODE : rmap_sy_pd_vtune_override_test_mode
bits : 28 - 28 (1 bit)
access : read-write


SY_CTRL_2

RF Analog Synthesizer Control 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SY_CTRL_2 SY_CTRL_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SY_VCO_BIAS SY_VCO_DIAGSEL SY_VCO_KV SY_VCO_KVM SY_VCO_PK_DET_ON SY_VCO_SPARE

SY_VCO_BIAS : rmap_sy_vco_bias[2:0]
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

0.97V

#001 : 1

1.033V

#010 : 2

1.06V

#011 : 3

1.07V

#100 : 4

1.08V

#101 : 5

1.085V

#110 : 6

1.090V

#111 : 7

1.095V

End of enumeration elements list.

SY_VCO_DIAGSEL : rmap_sy_vco_diagsel
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#1 : 1

Diag enable

#0 : 0

Diag disable

End of enumeration elements list.

SY_VCO_KV : rmap_sy_vco_kv[2:0]
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

50MHz/V

#001 : 1

60MHz/V

#010 : 2

70MHz/V

#011 : 3

80MHz/V

#100 : 4

80MHz/V

#101 : 5

80MHz/V

#110 : 6

80MHz/V

#111 : 7

80MHz/V

End of enumeration elements list.

SY_VCO_KVM : rmap_sy_vco_kvm[2:0]
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

10MHz/V

#001 : 1

20MHz/V

#010 : 2

30MHz/V

#011 : 3

40MHz/V

#100 : 4

40MHz/V

#101 : 5

40MHz/V

#110 : 6

40MHz/V

#111 : 7

40MHz/V

End of enumeration elements list.

SY_VCO_PK_DET_ON : rmap_sy_vco_pk_det_on
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#1 : 1

Enable

#0 : 0

Disable

End of enumeration elements list.

SY_VCO_SPARE : rmap_sy_vco_spare[2:0]
bits : 14 - 16 (3 bit)
access : read-write


TX_DAC_PA

RF Analog TX HPM DAC and PA Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_DAC_PA TX_DAC_PA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_DAC_BUMP_CAP TX_DAC_BUMP_IDAC TX_DAC_BUMP_RLOAD TX_DAC_DIAGSEL TX_DAC_INVERT_CLK TX_DAC_OPAMP_DIAGSEL TX_DAC_SPARE TX_PA_BUMP_VBIAS TX_PA_DIAGSEL TX_PA_SPARE

TX_DAC_BUMP_CAP : rmap_tx_dac_bump_cap[1:0]
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

1pF(default)

#01 : 1

1.5pF

#10 : 2

1.5pF

#11 : 3

2pF

End of enumeration elements list.

TX_DAC_BUMP_IDAC : rmap_tx_dac_bump_idac[1:0]
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

#00 : 0

250nA(default)

#01 : 1

207nA

#10 : 2

312nA

#11 : 3

415nA

End of enumeration elements list.

TX_DAC_BUMP_RLOAD : rmap_tx_dac_bump_rload[1:0]
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

3.12 kohms(default)

#01 : 1

2.34 kohms

#10 : 2

3.9 kohms

#11 : 3

4.6 kohms

End of enumeration elements list.

TX_DAC_DIAGSEL : rmap_tx_dac_diagsel
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Diag

#1 : 1

Enable Diag

End of enumeration elements list.

TX_DAC_INVERT_CLK : rmap_tx_dac_invert_clk
bits : 10 - 10 (1 bit)
access : read-write

TX_DAC_OPAMP_DIAGSEL : rmap_tx_dac_opamp_diagsel
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Diag

#1 : 1

Enable Diag

End of enumeration elements list.

TX_DAC_SPARE : rmap_tx_dac_spare[2:0]
bits : 13 - 15 (3 bit)
access : read-write

TX_PA_BUMP_VBIAS : rmap_tx_pa_bump_vbias[2:0]
bits : 17 - 19 (3 bit)
access : read-write

Enumeration:

#000 : 0

0.557

#001 : 1

0.651

#010 : 2

0.741

#011 : 3

0.822

#100 : 4

0.590

#101 : 5

0.683

#110 : 6

0.771

#111 : 7

0.850

End of enumeration elements list.

TX_PA_DIAGSEL : rmap_tx_pa_diagsel
bits : 21 - 21 (1 bit)
access : read-write

TX_PA_SPARE : rmap_tx_pa_spare[2:0]
bits : 23 - 25 (3 bit)
access : read-write


BALUN_TX

RF Analog Balun TX Mode Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BALUN_TX BALUN_TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTX_BAL_TX_CODE

RXTX_BAL_TX_CODE : Balun Tuning Cap Settings in Transmit Mode
bits : 0 - 23 (24 bit)
access : read-write


BALUN_RX

RF Analog Balun RX Mode Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BALUN_RX BALUN_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTX_BAL_RX_CODE

RXTX_BAL_RX_CODE : Balun Tuning Cap Settings in Receive Mode
bits : 0 - 23 (24 bit)
access : read-write


DFT_OBSV_1

RF Analog DFT Observation Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFT_OBSV_1 DFT_OBSV_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFT_FREQ_COUNTER CTUNE_MAX_DIFF

DFT_FREQ_COUNTER : VCO Frequency Counter Value
bits : 0 - 18 (19 bit)
access : read-only

CTUNE_MAX_DIFF : Maximum Frequency Count Difference found by the Coarse Tune BIST
bits : 20 - 27 (8 bit)
access : read-only


DFT_OBSV_2

RF Analog DFT Observation Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFT_OBSV_2 DFT_OBSV_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYN_BIST_MAX_DIFF SYN_BIST_MAX_DIFF_CH SYN_BIST_IGNORE_FAILS

SYN_BIST_MAX_DIFF : PLL Frequency Synthesizer BIST Worst Frequency Count
bits : 0 - 16 (17 bit)
access : read-only

SYN_BIST_MAX_DIFF_CH : PLL Frequency Synthesizer BIST Worst Channel
bits : 24 - 30 (7 bit)
access : read-only

SYN_BIST_IGNORE_FAILS : PLL Frequency Synthesizer BIST Ignore Fails
bits : 31 - 31 (1 bit)
access : read-write


BB_LDO_2

RF Analog Baseband LDO Control 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BB_LDO_2 BB_LDO_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BB_LDO_PD_BYP BB_LDO_PD_DIAGSEL BB_LDO_PD_SPARE BB_LDO_PD_TRIM BB_LDO_VCO_SPARE BB_LDO_VCOLO_BYP BB_LDO_VCOLO_DIAGSEL BB_LDO_VCOLO_TRIM BB_LDO_VTREF_DIAGSEL BB_LDO_VTREF_TC

BB_LDO_PD_BYP : rmap_bb_ldo_pd_byp
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bypass disabled.

#1 : 1

Bypass enabled

End of enumeration elements list.

BB_LDO_PD_DIAGSEL : rmap_bb_ldo_pd_diagsel
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_PD_SPARE : rmap_bb_ldo_pd_spare[1:0]
bits : 2 - 3 (2 bit)
access : read-write

BB_LDO_PD_TRIM : rmap_bb_ldo_pd_trim[2:0]
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

1.20 V ( Default )

#001 : 1

1.25 V

#010 : 2

1.28 V

#011 : 3

1.33 V

#100 : 4

1.40 V

#101 : 5

1.44 V

#110 : 6

1.50 V

#111 : 7

1.66 V

End of enumeration elements list.

BB_LDO_VCO_SPARE : rmap_bb_ldo_vco_spare[1:0]
bits : 8 - 9 (2 bit)
access : read-write

BB_LDO_VCOLO_BYP : rmap_bb_ldo_vcolo_byp
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bypass disabled.

#1 : 1

Bypass enabled

End of enumeration elements list.

BB_LDO_VCOLO_DIAGSEL : rmap_bb_ldo_vcolo_diagsel
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_VCOLO_TRIM : rmap_bb_ldo_vcolo_trim[2:0]
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

1.138/1.117 V ( Default )

#001 : 1

1.076/1.058 V

#010 : 2

1.027/1.012 V

#011 : 3

0.98/0.97 V

#100 : 4

1.22/1.19 V

#101 : 5

1.33/1.3 V

#110 : 6

1.5/1.4 V

#111 : 7

1.82/1.4 V

End of enumeration elements list.

BB_LDO_VTREF_DIAGSEL : rmap_bb_ldo_vtref_diagsel
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

BB_LDO_VTREF_TC : rmap_bb_ldo_vtref_tc[1:0]
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

#00 : 0

1.117/1.176 V

#01 : 1

1.134/1.188 V

#10 : 2

1.10/1.162 V

#11 : 3

1.09/1.152 V

End of enumeration elements list.


RX_ADC

RF Analog ADC Control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_ADC RX_ADC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_ADC_BUMP RX_ADC_FS_SEL RX_ADC_I_DIAGSEL RX_ADC_Q_DIAGSEL RX_ADC_SPARE

RX_ADC_BUMP : rmap_rx_adc_bump[7:0]
bits : 0 - 7 (8 bit)
access : read-write

RX_ADC_FS_SEL : rmap_rx_adc_fs_sel[1:0]
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

52MHz (2x26MHz)

#01 : 1

64MHz (2x32MHz)

#10 : 2

+13% of 64MHz

#11 : 3

- 11% of 64MHz

End of enumeration elements list.

RX_ADC_I_DIAGSEL : rmap_rx_adc_i_diagsel
bits : 10 - 10 (1 bit)
access : read-write

RX_ADC_Q_DIAGSEL : rmap_rx_adc_q_diagsel
bits : 11 - 11 (1 bit)
access : read-write

RX_ADC_SPARE : rmap_rx_adc_spare[3:0]
bits : 12 - 15 (4 bit)
access : read-write


RX_BBA

RF Analog BBA Control
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_BBA RX_BBA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_BBA_BW_SEL RX_BBA_CUR_BUMP RX_BBA_DIAGSEL1 RX_BBA_DIAGSEL2 RX_BBA_DIAGSEL3 RX_BBA_DIAGSEL4 RX_BBA_SPARE RX_BBA2_BW_SEL RX_BBA2_SPARE

RX_BBA_BW_SEL : rmap_rx_bba_bw_sel[2:0]
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

1000K

#001 : 001

900K

#010 : 010

800K

#011 : 011

700K Default

#100 : 100

600K

#101 : 101

500K

End of enumeration elements list.

RX_BBA_CUR_BUMP : rmap_rx_bba_cur_bump
bits : 3 - 3 (1 bit)
access : read-write

RX_BBA_DIAGSEL1 : rmap_rx_bba_diagsel1
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_BBA_DIAGSEL2 : rmap_rx_bba_diagsel2
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_BBA_DIAGSEL3 : rmap_rx_bba_diagsel3
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_BBA_DIAGSEL4 : rmap_rx_bba_diagsel4
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diag disable

#1 : 1

Diag enable

End of enumeration elements list.

RX_BBA_SPARE : rmap_rx_bba_spare[5:0]
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

#0 : 00

600mV (Default)

#1 : 01

675mV

#10 : 10

450mV

#11 : 11

525mV

End of enumeration elements list.

RX_BBA2_BW_SEL : rmap_bba2_bw_sel[2:0]
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

1000K

#001 : 001

900K

#010 : 010

800K

#011 : 011

700K Default

#100 : 100

600K

#101 : 101

500K

End of enumeration elements list.

RX_BBA2_SPARE : rmap_rx_bba2_spare[2:0]
bits : 28 - 30 (3 bit)
access : read-write



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