\n
address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
IRQ CONTROL
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQ_END_IRQ : Sequence End Interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sequence End Interrupt is not asserted.
#1 : 1
Sequence End Interrupt is asserted.
End of enumeration elements list.
TX_IRQ : TX Interrupt
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX Interrupt is not asserted.
#1 : 1
TX Interrupt is asserted.
End of enumeration elements list.
RX_IRQ : RX Interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX Interrupt is not asserted.
#1 : 1
RX Interrupt is asserted.
End of enumeration elements list.
NTW_ADR_IRQ : Network Address Match Interrupt
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Network Address Match Interrupt is not asserted.
#1 : 1
Network Address Match Interrupt is asserted.
End of enumeration elements list.
T1_IRQ : Timer1 (T1) Compare Interrupt
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 (T1) Compare Interrupt is not asserted.
#1 : 1
Timer1 (T1) Compare Interrupt is asserted.
End of enumeration elements list.
T2_IRQ : Timer2 (T2) Compare Interrupt
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 (T2) Compare Interrupt is not asserted.
#1 : 1
Timer2 (T2) Compare Interrupt is asserted.
End of enumeration elements list.
PLL_UNLOCK_IRQ : PLL Unlock Interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL Unlock Interrupt is not asserted.
#1 : 1
PLL Unlock Interrupt is asserted.
End of enumeration elements list.
WAKE_IRQ : Wake Interrrupt
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake Interrupt is not asserted.
#1 : 1
Wake Interrupt is asserted.
End of enumeration elements list.
RX_WATERMARK_IRQ : RX Watermark Interrupt
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX Watermark Interrupt is not asserted.
#1 : 1
RX Watermark Interrupt is asserted.
End of enumeration elements list.
TSM_IRQ : TSM Interrupt
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
TSM0_IRQ and TSM1_IRQ are both clear.
#1 : 1
Indicates TSM0_IRQ or TSM1_IRQ is set in XCVR_STATUS.
End of enumeration elements list.
SEQ_END_IRQ_EN : SEQ_END_IRQ Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sequence End Interrupt is not enabled.
#1 : 1
Sequence End Interrupt is enabled.
End of enumeration elements list.
TX_IRQ_EN : TX_IRQ Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX Interrupt is not enabled.
#1 : 1
TX Interrupt is enabled.
End of enumeration elements list.
RX_IRQ_EN : RX_IRQ Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX Interrupt is not enabled.
#1 : 1
RX Interrupt is enabled.
End of enumeration elements list.
NTW_ADR_IRQ_EN : NTW_ADR_IRQ Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Network Address Match Interrupt is not enabled.
#1 : 1
Network Address Match Interrupt is enabled.
End of enumeration elements list.
T1_IRQ_EN : T1_IRQ Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 (T1) Compare Interrupt is not enabled.
#1 : 1
Timer1 (T1) Compare Interrupt is enabled.
End of enumeration elements list.
T2_IRQ_EN : T2_IRQ Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 (T2) Compare Interrupt is not enabled.
#1 : 1
Timer1 (T2) Compare Interrupt is enabled.
End of enumeration elements list.
PLL_UNLOCK_IRQ_EN : PLL_UNLOCK_IRQ Enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL Unlock Interrupt is not enabled.
#1 : 1
PLL Unlock Interrupt is enabled.
End of enumeration elements list.
WAKE_IRQ_EN : WAKE_IRQ Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake Interrupt is not enabled.
#1 : 1
Wake Interrupt is enabled.
End of enumeration elements list.
RX_WATERMARK_IRQ_EN : RX_WATERMARK_IRQ Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX Watermark Interrupt is not enabled.
#1 : 1
RX Watermark Interrupt is enabled.
End of enumeration elements list.
TSM_IRQ_EN : TSM_IRQ Enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSM Interrupt is not enabled.
#1 : 1
TSM Interrupt is enabled.
End of enumeration elements list.
GENERIC_FSK_IRQ_EN : GENERIC_FSK_IRQ Master Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
All GENERIC_FSK Interrupts are disabled.
#1 : 1
All GENERIC_FSK Interrupts can be enabled.
End of enumeration elements list.
CRC_IGNORE : CRC Ignore
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX_IRQ will not be asserted for a received packet which fails CRC verification.
#1 : 1
RX_IRQ will be asserted even for a received packet which fails CRC verification.
End of enumeration elements list.
CRC_VALID : CRC Valid
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
CRC of RX packet is not valid.
#1 : 1
CRC of RX packet is valid.
End of enumeration elements list.
TIMESTAMP
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TIMESTAMP : Received Packet Timestamp
bits : 0 - 23 (24 bit)
access : read-only
TRANSCEIVER CONTROL
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQCMD : Sequence Commands
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0x0
No Action
#0001 : 0x1
TX Start Now
#0010 : 0x2
TX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
#0011 : 0x3
TX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
#0100 : 0x4
TX Cancel -- Cancels pending TX events but do not abort a TX-in-progress
#0101 : 0x5
RX Start Now
#0110 : 0x6
RX Start @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
#0111 : 0x7
RX Start @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
#1000 : 0x8
RX Stop @ T1 Timer Compare Match (EVENT_TMR = T1_CMP)
#1001 : 0x9
RX Stop @ T2 Timer Compare Match (EVENT_TMR = T2_CMP)
#1010 : 0xA
RX Cancel -- Cancels pending RX events but do not abort a RX-in-progress
#1011 : 0xB
Abort All - Cancels all pending events and abort any sequence-in-progress
End of enumeration elements list.
CMDDEC_CS : Command Decode
bits : 24 - 26 (3 bit)
access : read-only
XCVR_BUSY : Transceiver Busy
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
IDLE
#1 : 1
BUSY
End of enumeration elements list.
TRANSCEIVER STATUS
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_START_T1_PEND : TX T1 Start Pending Status
bits : 0 - 0 (1 bit)
access : read-only
TX_START_T2_PEND : TX T2 Start Pending Status
bits : 1 - 1 (1 bit)
access : read-only
TX_IN_WARMUP : TX Warmup Status
bits : 2 - 2 (1 bit)
access : read-only
TX_IN_PROGRESS : TX in Progress Status
bits : 3 - 3 (1 bit)
access : read-only
TX_IN_WARMDN : TX Warmdown Status
bits : 4 - 4 (1 bit)
access : read-only
RX_START_T1_PEND : RX T1 Start Pending Status
bits : 5 - 5 (1 bit)
access : read-only
RX_START_T2_PEND : RX T2 Start Pending Status
bits : 6 - 6 (1 bit)
access : read-only
RX_STOP_T1_PEND : RX T1 Stop Pending Status
bits : 7 - 7 (1 bit)
access : read-only
RX_STOP_T2_PEND : RX T2 Start Pending Status
bits : 8 - 8 (1 bit)
access : read-only
RX_IN_WARMUP : RX Warmup Status
bits : 9 - 9 (1 bit)
access : read-only
RX_IN_SEARCH : RX Search Status
bits : 10 - 10 (1 bit)
access : read-only
RX_IN_PROGRESS : RX in Progress Status
bits : 11 - 11 (1 bit)
access : read-only
RX_IN_WARMDN : RX Warmdown Status
bits : 12 - 12 (1 bit)
access : read-only
LQI_VALID : LQI Valid Indicator
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
LQI is not yet valid for RX packet.
#1 : 1
LQI is valid for RX packet.
End of enumeration elements list.
CRC_VALID : CRC Valid Indicator
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
CRC is not valid for RX packet.
#1 : 1
CRC is valid for RX packet.
End of enumeration elements list.
RSSI : Received Signal Stength Indicator, in dBm
bits : 16 - 23 (8 bit)
access : read-only
LQI : Link Quality Indicator
bits : 24 - 31 (8 bit)
access : read-only
TRANSCEIVER CONFIGURATION
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_WHITEN_DIS : TX Whitening Disable
bits : 0 - 0 (1 bit)
access : read-write
RX_DEWHITEN_DIS : RX De-Whitening Disable
bits : 1 - 1 (1 bit)
access : read-write
SW_CRC_EN : Software CRC Enable
bits : 2 - 2 (1 bit)
access : read-write
PREAMBLE_SZ : Preamble Size
bits : 4 - 6 (3 bit)
access : read-write
TX_WARMUP : Transmit Warmup Time
bits : 8 - 15 (8 bit)
access : read-only
RX_WARMUP : Receive Warmup Time
bits : 16 - 23 (8 bit)
access : read-only
CHANNEL NUMBER
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL_NUM : Channel Number
bits : 0 - 6 (7 bit)
access : read-write
TRANSMIT POWER
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_POWER : Transmit Power
bits : 0 - 5 (6 bit)
access : read-write
NETWORK ADDRESS CONTROL
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTW_ADR_EN : Network Address Enable
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
Enable Network Address 0 for correlation
#0010 : 0010
Enable Network Address 1 for correlation
#0100 : 0100
Enable Network Address 2 for correlation
#1000 : 1000
Enable Network Address 3 for correlation
End of enumeration elements list.
NTW_ADR_MCH : Network Address Match
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
#0001 : 0001
Network Address 0 has matched
#0010 : 0010
Network Address 1 has matched
#0100 : 0100
Network Address 2 has matched
#1000 : 1000
Network Address 3 has matched
End of enumeration elements list.
NTW_ADR0_SZ : Network Address 0 Size
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Network Address 0 requires a 8-bit correlation
#01 : 1
Network Address 0 requires a 16-bit correlation
#10 : 2
Network Address 0 requires a 24-bit correlation
#11 : 3
Network Address 0 requires a 32-bit correlation
End of enumeration elements list.
NTW_ADR1_SZ : Network Address 1 Size
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Network Address 1 requires a 8-bit correlation
#01 : 1
Network Address 1 requires a 16-bit correlation
#10 : 2
Network Address 1 requires a 24-bit correlation
#11 : 3
Network Address 1 requires a 32-bit correlation
End of enumeration elements list.
NTW_ADR2_SZ : Network Address 2 Size
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Network Address 2 requires a 8-bit correlation
#01 : 1
Network Address 2 requires a 16-bit correlation
#10 : 2
Network Address 2 requires a 24-bit correlation
#11 : 3
Network Address 2 requires a 32-bit correlation
End of enumeration elements list.
NTW_ADR3_SZ : Network Address 3 Size
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Network Address 3 requires a 8-bit correlation
#01 : 1
Network Address 3 requires a 16-bit correlation
#10 : 2
Network Address 3 requires a 24-bit correlation
#11 : 3
Network Address 3 requires a 32-bit correlation
End of enumeration elements list.
NTW_ADR_THR0 : Network Address 0 Threshold
bits : 16 - 18 (3 bit)
access : read-write
NTW_ADR_THR1 : Network Address 1 Threshold
bits : 20 - 22 (3 bit)
access : read-write
NTW_ADR_THR2 : Network Address 2 Threshold
bits : 24 - 26 (3 bit)
access : read-write
NTW_ADR_THR3 : Network Address 3 Threshold
bits : 28 - 30 (3 bit)
access : read-write
NETWORK ADDRESS 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTW_ADR_0 : Network Address 0
bits : 0 - 31 (32 bit)
access : read-write
NETWORK ADDRESS 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTW_ADR_1 : Network Address 1
bits : 0 - 31 (32 bit)
access : read-write
NETWORK ADDRESS 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTW_ADR_2 : Network Address 2
bits : 0 - 31 (32 bit)
access : read-write
NETWORK ADDRESS 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTW_ADR_3 : Network Address 2
bits : 0 - 31 (32 bit)
access : read-write
RECEIVE WATERMARK
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_WATERMARK : Receive Watermark
bits : 0 - 12 (13 bit)
access : read-write
BYTE_COUNTER : Byte Counter
bits : 16 - 28 (13 bit)
access : read-only
EVENT TIMER
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENT_TMR : Event Timer
bits : 0 - 23 (24 bit)
access : read-write
EVENT_TMR_LD : Event Timer Load
bits : 24 - 24 (1 bit)
access : write-only
EVENT_TMR_ADD : Event Timer Add
bits : 25 - 25 (1 bit)
access : write-only
DSM CONTROL
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GENERIC_FSK_SLEEP_EN : GENERIC_FSK DSM Sleep Enable
bits : 0 - 0 (1 bit)
access : write-only
PART ID
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_ID : Part ID
bits : 0 - 7 (8 bit)
access : read-only
PACKET CONFIGURATION
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENGTH_SZ : LENGTH Size
bits : 0 - 4 (5 bit)
access : read-write
LENGTH_BIT_ORD : LENGTH Bit Order
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LS Bit First
#1 : 1
MS Bit First
End of enumeration elements list.
SYNC_ADDR_SZ : Sync Address Size
bits : 6 - 7 (2 bit)
access : read-write
LENGTH_ADJ : Length Adjustment
bits : 8 - 13 (6 bit)
access : read-write
LENGTH_FAIL : Maximum Length Violated Status Bit
bits : 15 - 15 (1 bit)
access : read-only
H0_SZ : H0 Size
bits : 16 - 20 (5 bit)
access : read-write
H0_FAIL : H0 Violated Status Bit
bits : 23 - 23 (1 bit)
access : read-only
H1_SZ : H1 Size
bits : 24 - 28 (5 bit)
access : read-write
H1_FAIL : H1 Violated Status Bit
bits : 31 - 31 (1 bit)
access : read-only
H0 CONFIGURATION
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H0_MATCH : H0 Match Register
bits : 0 - 15 (16 bit)
access : read-write
H0_MASK : H0 Mask Register
bits : 16 - 31 (16 bit)
access : read-write
H1 CONFIGURATION
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H1_MATCH : H1 Match Register
bits : 0 - 15 (16 bit)
access : read-write
H1_MASK : H1 Mask Register
bits : 16 - 31 (16 bit)
access : read-write
CRC CONFIGURATION
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_SZ : CRC Size (in octets)
bits : 0 - 2 (3 bit)
access : read-write
CRC_START_BYTE : Configure CRC Start Point
bits : 8 - 11 (4 bit)
access : read-write
CRC_REF_IN : CRC Reflect In
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not manipulate input data stream
#1 : 1
reflect each byte in the input stream bitwise
End of enumeration elements list.
CRC_REF_OUT : CRC Reflect Out
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
do not manipulate CRC result
#1 : 1
CRC result is to be reflected bitwise (operated on entire word)
End of enumeration elements list.
CRC_BYTE_ORD : CRC Byte Order
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
LS Byte First
#1 : 1
MS Byte First
End of enumeration elements list.
CRC INITIALIZATION
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_SEED : CRC Seed Value
bits : 0 - 31 (32 bit)
access : read-write
CRC POLYNOMIAL
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_POLY : CRC Polynomial.
bits : 0 - 31 (32 bit)
access : read-write
CRC XOR OUT
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_XOR_OUT : CRC XOR OUT Register
bits : 0 - 31 (32 bit)
access : read-write
WHITENER CONFIGURATION
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHITEN_START : Configure Whitener Start Point
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
no whitening
#01 : 1
start whitening at start-of-H0
#10 : 2
start whitening at start-of-H1 but only if LENGTH > WHITEN_SZ_THR
#11 : 3
start whitening at start-of-payload but only if LENGTH > WHITEN_SZ_THR
End of enumeration elements list.
WHITEN_END : Configure end-of-whitening
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
end whiten at end-of-payload
#1 : 1
end whiten at end-of-crc
End of enumeration elements list.
WHITEN_B4_CRC : Congifure for Whitening-before-CRC
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC before whiten/de-whiten
#1 : 1
Whiten/de-whiten before CRC
End of enumeration elements list.
WHITEN_POLY_TYPE : Whiten Polynomial Type
bits : 4 - 4 (1 bit)
access : read-write
WHITEN_REF_IN : Whiten Reflect Input
bits : 5 - 5 (1 bit)
access : read-write
WHITEN_PAYLOAD_REINIT : Configure for Whitener re-initialization
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't re-initialize Whitener LFSR at start-of-payload
#1 : 1
Re-initialize Whitener LFSR at start-of-payload
End of enumeration elements list.
WHITEN_SIZE : Length of Whitener LFSR
bits : 8 - 11 (4 bit)
access : read-write
MANCHESTER_EN : Configure for Manchester Encoding/Decoding
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Manchester encoding (TX) and decoding (RX)
#1 : 1
Enable Manchester encoding (TX) and decoding (RX)
End of enumeration elements list.
MANCHESTER_INV : Configure for Inverted Manchester Encoding
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Manchester coding as per 802.3
#1 : 1
Manchester coding as per 802.3 but with the encoding signal inverted
End of enumeration elements list.
MANCHESTER_START : Configure Manchester Encoding Start Point
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Start Manchester coding at start-of-payload
#1 : 1
Start Manchester coding at start-of-header
End of enumeration elements list.
WHITEN_INIT : Initialization Value for Whitening/De-whitening
bits : 16 - 24 (9 bit)
access : read-write
T1 COMPARE
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T1_CMP : Timer1 (T1) Compare Value
bits : 0 - 23 (24 bit)
access : read-write
T1_CMP_EN : Timer1 (T1) Compare Enable
bits : 24 - 24 (1 bit)
access : read-write
WHITENER POLYNOMIAL
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHITEN_POLY : Whitener Polynomial
bits : 0 - 8 (9 bit)
access : read-write
WHITENER SIZE THRESHOLD
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHITEN_SZ_THR : Whitener Size Threshold
bits : 0 - 11 (12 bit)
access : read-write
LENGTH_MAX : Maximum Length for Received Packets
bits : 16 - 22 (7 bit)
access : read-write
REC_BAD_PKT : Receive Bad Packets
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
packets which fail H0, H1, or LENGTH_MAX result in an automatic recycle after the header is received and parsed
#1 : 1
packets which fail H0, H1, or LENGTH_MAX are received in their entirety
End of enumeration elements list.
BIT RATE
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITRATE : Bit Rate
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
1Mbit/sec
#01 : 1
500Kbit/sec
#10 : 2
250Kbit/sec (not supported if WHITEN_CFG[MANCHESTER_EN]=1
End of enumeration elements list.
PACKET BUFFER PARTITION POINT
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB_PARTITION : Packet Buffer Partition Point
bits : 0 - 10 (11 bit)
access : read-write
T2 COMPARE
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2_CMP : Timer2 (T2) Compare Value
bits : 0 - 23 (24 bit)
access : read-write
T2_CMP_EN : Timer2 (T2) Compare Enable
bits : 24 - 24 (1 bit)
access : read-write
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