\n
address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
SRC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CA5_WDGRST_MASK : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0101 : 0101
wdog_rst_b is masked
#1010 : 1010
wdog_rst_b is not masked (default)
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 6 (3 bit)
access : read-only
CM4_WDGRST_MASK : no description available
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#0101 : 0101
wdog_rst_b is masked
#1010 : 1010
wdog_rst_b is not masked (default)
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 11 (1 bit)
access : read-only
SW_RST : no description available
bits : 12 - 12 (1 bit)
access : write-only
Enumeration:
#0 : 0
Software reset not requested
#1 : 1
Software reset requested
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 31 (19 bit)
access : read-only
General purpose Status register.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-only
HAB
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
SRC Reset Interrupt Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only
CA5_WDG_RST : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-write
WDOG_RST : no description available
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
JTAG_RST : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
RESERVED : Reserved
bits : 16 - 16 (1 bit)
access : read-only
SNVS_HARD_RST : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-only
CSU_ALARM_RST : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-write
REG_1P1 : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
REG_2P5 : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
RESERVED : Reserved
bits : 26 - 26 (1 bit)
access : read-only
CMU_OLR : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
CMU_FLL_FHH : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
FOSC_OK_CFG : no description available
bits : 29 - 29 (1 bit)
access : read-write
RESERVED : Reserved
bits : 30 - 30 (1 bit)
access : read-only
CM4_LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#1 : 1
The bitfield is configured as interrupt
#0 : 0
The bitfield is reset.
End of enumeration elements list.
HAB
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
SRC Interrupt Masking Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only
CA5_WDG_RST : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-write
WDOG_RST : no description available
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
JTAG_RST : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
RESERVED : Reserved
bits : 16 - 16 (1 bit)
access : read-only
SNVS_HARD_RST : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-only
CSU_ALARM_RST : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-write
REG_1P1_OK : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
REG_2P5_OK : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
REG_3P0_OK : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
CMU_OLR : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
CMU_FLL_FHH : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only
SOSC_OK : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
CM4_LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#1 : 1
Interrupts are non-masked
#0 : 0
Interrupts are masked
End of enumeration elements list.
HAB
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
SRC Boot Mode Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC_CONFIG : no description available
bits : 0 - 1 (2 bit)
access : read-only
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only
DIR_BT_DIS : no description available
bits : 3 - 3 (1 bit)
access : read-only
BT_FUSE_SEL : no description available
bits : 4 - 4 (1 bit)
access : read-only
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
BMOD : no description available
bits : 24 - 25 (2 bit)
access : read-only
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
SRC Boot Mode Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOOT_CFG1 : no description available
bits : 0 - 7 (8 bit)
access : read-only
BOOT_CFG2 : no description available
bits : 8 - 15 (8 bit)
access : read-only
BOOT_CFG3 : no description available
bits : 16 - 23 (8 bit)
access : read-only
BOOT_CFG4 : no description available
bits : 24 - 31 (8 bit)
access : read-only
General Purpose Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
MISC0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC0_15_1 : no description available
bits : 0 - 15 (16 bit)
access : read-write
MISC0_25_16 : no description available
bits : 16 - 25 (10 bit)
access : read-only
MISC0_26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
usb0 sof
#1 : 1
external trigger
End of enumeration elements list.
MISC0_27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
usb0 sof
#1 : 1
external trigger
End of enumeration elements list.
MISC0_28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
adc1_coco
#1 : 1
usb1 sof
End of enumeration elements list.
MISC0_29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
usb0 sof
#1 : 1
external trigger
End of enumeration elements list.
MISC0_30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
adc1_coco
#1 : 1
usb1 sof
End of enumeration elements list.
MISC0_31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
usb0 sof
#1 : 1
external trigger
End of enumeration elements list.
MISC1
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC1_0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MISC1_1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MISC1_2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MISC1_3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MISC1_4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MISC1_5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MISC1_6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MISC1_7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MISC1_8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MISC1_9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MISC1_10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#1 : 1
Fault deasserted
#0 : 0
Fault asserted
End of enumeration elements list.
MISC1_11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault deasserted
#1 : 1
Fault asserted
End of enumeration elements list.
MISC1_12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MISC1_13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault deasserted
#1 : 1
Fault asserted
End of enumeration elements list.
MISC1_14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MISC1_15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MISC1_25_16 : no description available
bits : 16 - 25 (10 bit)
access : read-write
MISC1_26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger
#1 : 1
LPTIMER trigger
End of enumeration elements list.
MISC1_27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger
#1 : 1
LPTIMER trigger
End of enumeration elements list.
MISC1_28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ext_hwts[0] is not selected
#1 : 1
ext_hwts[0] is selected.
End of enumeration elements list.
MISC1_29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
ext_hwts[1] is not selected
#1 : 1
ext_hwts[1] is selected.
End of enumeration elements list.
MISC1_30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ext_hwts[0] is not selected
#1 : 1
ext_hwts[0] is selected.
End of enumeration elements list.
MISC1_31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ext_hwts[1] is not selected
#1 : 1
ext_hwts[1] is selected.
End of enumeration elements list.
MISC2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC2_0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DDR memory reset is driven by DDR PHY
#1 : 1
will remain high (inactive)
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 2 (2 bit)
access : read-only
MISC2_7_3 : no description available
bits : 3 - 7 (5 bit)
access : read-write
MISC2_8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
VADC disabled
#1 : 1
VADC enabled
End of enumeration elements list.
MISC2_9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
VIU is selected
#1 : 1
VADC is selected
End of enumeration elements list.
MISC2_15_10 : no description available
bits : 10 - 15 (6 bit)
access : read-write
MISC2_31_16 : no description available
bits : 16 - 31 (16 bit)
access : read-write
MISC3
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISC3_0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ENET MAC1 as Master9 port
#1 : 1
MLB as Master9 port
End of enumeration elements list.
MISC3_1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
CA5 dbg_ack is Ored with CM4 debug_ack
#1 : 1
Ignore dbg_ack for CA5
End of enumeration elements list.
MISC3_2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CM4 dbg_ack is Ored with CA5 debug_ack
#1 : 1
Ignore dbg_ack for CM4
End of enumeration elements list.
MISC3_3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MISC3_4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MISC3_5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MISC3_6 : no description available
bits : 6 - 6 (1 bit)
access : read-only
MISC3_7 : no description available
bits : 7 - 7 (1 bit)
access : read-only
MISC3_8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MISC3_9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive USB0 OverCurrent from IOMUX.
#1 : 1
Drive USB0 OverCurrent from SRC_MISC3[8].
End of enumeration elements list.
MISC3_10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MISC3_11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive USB1 OverCurrent from IOMUX
#1 : 1
Drive USB1 OverCurrent from SRC_MISC3[10].
End of enumeration elements list.
MISC3_12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MISC3_15_13 : no description available
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
#000 : 000
65536
#001 : 001
32768
#010 : 010
16384
#011 : 011
8192
#100 : 100
4096
#101 : 101
2048
#110 : 110
1024
#111 : 111
512
End of enumeration elements list.
MISC3_31_16 : no description available
bits : 16 - 31 (16 bit)
access : read-only
General Purpose Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
HAB
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
SRC Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR_RST : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
CA5_WDG_RST : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only
WDOG_RST : no description available
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
JTAG_RST : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-only
RESETB : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
POR1P2 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
HP_LVD : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
ULP_LVD : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
reset.set when the event occurs
End of enumeration elements list.
LVD_P3P : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
LP_LVD : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
MDM_SYS_RST : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
SNVS_HARD_RST : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
SRC_SW_RST : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
CSU_ALARM_RST : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
REG_1P1_OK : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs.
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
REG_2P5_OK : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
REG_3P0_OK : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
CMU_OLR : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
CMU_FLL_FHH : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset .
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only
SOSC_OK : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset.
End of enumeration elements list.
CM4_LCK : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#1 : 1
The SRSR register bit is set when the event occurs
#0 : 0
The SRSR register bit is reset .
End of enumeration elements list.
General Purpose Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
HAB
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
General Purpose Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
no description available
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPNIDEN : no description available
bits : 0 - 0 (1 bit)
access : read-write
SPIDEN : no description available
bits : 1 - 1 (1 bit)
access : read-write
RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only
WRLOCK : no description available
bits : 4 - 4 (1 bit)
access : read-write
RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only
HAB
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
General Purpose Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GP : no description available
bits : 0 - 31 (32 bit)
access : read-write
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