DDRMC

AODT_RWSMCS : Additional delay to insert between read and write transaction types to the same chip select to meet ODT timing requirements.
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

AODT_WRSMCS : Additional delay to insert between write and read transaction types to the same chip select to meet ODT timing requirements. Any value including 0x0 supported.
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only

CR90

Control Register 90
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR91

Control Register 91
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

R2R_SMCSDL : Additional delay to insert between two reads to the same chip select. Any value including 0x0 supported.
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only

R2W_SMCSDL : Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value.
bits : 16 - 18 (3 bit)
access : read-write

RESERVED : no description available
bits : 19 - 23 (5 bit)
access : read-only

W2R_SMCSDL : Additional delay to insert between writes and reads to the same chip select.
bits : 24 - 26 (3 bit)
access : read-write

RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only

CR92

Control Register 92
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W2W_SMCSDL : Additional delay to insert between two writes to the same chip select. Any value including 0x0 supported.
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

TDQSCK_MAX : Additional delay needed for tDQSCK.
bits : 8 - 9 (2 bit)
access : read-write

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

TDQSCK_MIN : Additional delay needed for tDQSCK.
bits : 16 - 17 (2 bit)
access : read-write

RESERVED : no description available
bits : 18 - 31 (14 bit)
access : read-only

CR93

Control Register 93
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

SW_LVL_MODE : Defines the leveling operation for software leveling. Set to 0 for none, set to 1 for write leveling, set to 2 for read leveling, or set to 3 for gate training.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

No Leveling

#01 : 01

Write Leveling

#10 : 10

Read Leveling

#11 : 11

Gate Training

End of enumeration elements list.

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

SWLVL_LOAD : User request to load delays and execute software leveling. Set to to trigger.
bits : 16 - 16 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Load delays and start software leveling

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

SWLVL_START : User request to initiate software leveling of type in the SW_LVL_MODE bits. Set to 1 to trigger.
bits : 24 - 24 (1 bit)
access : write-only

Enumeration:

#0 : 0

No Action

#1 : 1

Initiate software leveling operation

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR94

Control Register 94
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWLVL_EXIT : User request to exit software leveling. Set to 1 to exit.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Exit software leveling

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

SWLVL_OP_DONE : Signals that software leveling is currently in progress. Value of 1 indicates operation complete.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

Operation in process

#1 : 1

Operation completed

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only

LVL_STATUS : Status of write level, read level, and gate training requests. This is used with the LVL_REQ interrupt. Bit (0) correlates to write leveling request, bit (1) correlates to read leveling request, and bit (2) correlates to gate training request. Value of 1indicates request received.
bits : 16 - 18 (3 bit)
access : read-only

RESERVED : no description available
bits : 19 - 23 (5 bit)
access : read-only

SWLVL_RESP_0 : Leveling response for data slice 0.
bits : 24 - 31 (8 bit)
access : read-only

CR95

Control Register 95
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWLVL_RESP_1 : Leveling response for data slice 1.
bits : 0 - 7 (8 bit)
access : read-only

SWLVL_RESP_2 : Leveling response for data slice 2.
bits : 8 - 15 (8 bit)
access : read-only

WRLVL_REQ : User request to initiate write leveling. Set to 1 to trigger.
bits : 16 - 16 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action

#1 : 1

Trigger write leveling

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

WRLVL_CS : Specifies the target chip select for the write leveling operation.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Targets CS0

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR06

Control Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR96

Control Register 96
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WLDQSEN : Delay from issuing MRS to first DQS strobe for write leveling.
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

WLMRD : Delay from issuing MRS to first write leveling strobe.
bits : 8 - 13 (6 bit)
access : read-write

RESERVED : no description available
bits : 14 - 15 (2 bit)
access : read-only

WRLVL_EN : Enable the MC write leveling module. Set to 1 to enable.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. The memory controller will never drive the PHY WRITE LEVEL ENABLE signal. The user may program the write leveling delay manually in the wrlvl_delay_X parameters.

#1 : 1

Enable. Write leveling will automatically be run at initialization, may be run on demand by setting the PHY WRITE LEVEL ENABLE parameter to 1 to assert the signal, or may be run periodically based on the programming of the wrlvl_refresh_interval parameter.

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR97

Control Register 97
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRLVL_REFRESH_INTERVAL : Number of refreshes counted between automatic write leveling commands
bits : 0 - 15 (16 bit)
access : read-write

WRLVL_ERR_STAT : no description available
bits : 16 - 23 (8 bit)
access : read-only

WRLVL_REG_EN : Enable the PHY WRITE LEVEL DELAY X signals to be programmed when hardware and software leveling are disabled. Set to 1 to enable.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR98

Control Register 98
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRLVL_DL_0 : Number of delay elements for write data slice 0. This is readonly if the WRLVL_EN parameter is 1. If both the WRLVL_EN and the WRLVL_REG_EN parameters are 0, this can only be programmed during initialization or through software leveling. If the WRLVL_EN parameter is 0 and the WRLVL_REG_EN parameter is 1, this can be programmed at any time.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR99

Control Register 99
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRLVL_DL_1 : Number of delay elements for write data slice 1. This is readonly if the WRLVL_EN parameter is 1. If both the WRLVL_EN and the WRLVL_REG_EN parameters are 0, this can only be programmed during initialization or through software leveling. If the WRLVL_EN parameter is 0 and the WRLVL_REG_EN parameter is 1, this can be programmed at any time.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR100

Control Register 100
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRLVL_DL_2 : Number of delay elements for write data slice 2. This is readonly if the WRLVL_EN parameter is 1. If both the WRLVL_EN and the WRLVL_REG_EN parameters are 0, this can only be programmed during initialization or through software leveling. If the WRLVL_EN parameter is 0 and the WRLVL_REG_EN parameter is 1, this can be programmed at any time.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR101

Control Register 101
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_REQ : no description available
bits : 0 - 0 (1 bit)
access : write-only

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

RDLVL_GT_REQ : no description available
bits : 8 - 8 (1 bit)
access : write-only

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only

RDLVL_CS : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

RDLVL_EDGE : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR102

Control Register 102
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_BGN_DLEN : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

RDLVL_REG_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only

RDLVL_GT_REGEN : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR103

Control Register 103
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDLVL_BGN_DL0 : no description available
bits : 0 - 15 (16 bit)
access : read-only

RDLVL_END_DL0 : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR104

Control Register 104
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_MP_DL0 : no description available
bits : 0 - 15 (16 bit)
access : read-only

RDLVL_OFF_DL0 : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR105

Control Register 105
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_OFF_DIR_0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

RDLVL_DL_0 : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR106

Control Register 106
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_GTDL_0 : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only

CR107

Control Register 107
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RDLVL_BGN_DL1 : no description available
bits : 16 - 23 (8 bit)
access : read-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR108

Control Register 108
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDLVL_END_DL1 : no description available
bits : 0 - 15 (16 bit)
access : read-only

RDLVL_MP_DL1 : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR109

Control Register 109
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_OFF_DL1 : no description available
bits : 0 - 15 (16 bit)
access : read-write

RDLVL_OFF_DIR1 : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR110

Control Register 110
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_DL_1 : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

RDLVL_GTDL_1 : no description available
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR111

Control Register 111
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR07

Control Register 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR112

Control Register 112
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDLVL_BGN_DL2 : no description available
bits : 0 - 15 (16 bit)
access : read-only

RDLVL_END_DL2 : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR113

Control Register 113
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_MP_DL2 : no description available
bits : 0 - 15 (16 bit)
access : read-only

RDLVL_OFF_DL2 : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR114

Control Register 114
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_OFF_DIR2 : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

RDLVL_GTDL_2 : no description available
bits : 8 - 23 (16 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR115

Control Register 115
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_GTDL_2 : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only

CR116

Control Register 116
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR117

Control Register 117
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI0_R_PRI : no description available
bits : 0 - 1 (2 bit)
access : read-write

RESERVED : no description available
bits : 2 - 7 (6 bit)
access : read-only

AXI0_W_PRI : no description available
bits : 8 - 9 (2 bit)
access : read-write

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

AXI0_FITYPREG : no description available
bits : 16 - 17 (2 bit)
access : read-write

RESERVED : no description available
bits : 18 - 31 (14 bit)
access : read-only

CR118

Control Register 118
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

AXI1_R_PRI : no description available
bits : 16 - 17 (2 bit)
access : read-write

RESERVED : no description available
bits : 18 - 23 (6 bit)
access : read-only

AXI1_W_PRI : no description available
bits : 24 - 25 (2 bit)
access : read-write

RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only

CR119

Control Register 119
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI1_FITYPREG : no description available
bits : 0 - 1 (2 bit)
access : read-write

RESERVED : no description available
bits : 2 - 15 (14 bit)
access : read-only

AXI_ASTB_DIS : no description available
bits : 16 - 17 (2 bit)
access : read-write

RESERVED : no description available
bits : 18 - 23 (6 bit)
access : read-only

WRR_LATCTL : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR120

Control Register 120
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W_RR_WSHR : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

WRR_ERR : no description available
bits : 8 - 11 (4 bit)
access : read-only

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

AXI0_PRI0_RPRI : no description available
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

AXI0_PRI1_RPRI : no description available
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only

CR121

Control Register 121
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI0_PRI2_RPRI : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

AXI0_PRI3_RPRI : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

AXI0_P_ODR : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR122

Control Register 122
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI0_PRIRLX : no description available
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

AXI1_PRI0_RPRI : no description available
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

AXI1_PRI1_RPRI : no description available
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only

CR123

Control Register 123
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI1_PRI2_RPRI : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

AXI1_PRI3_RPRI : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

AXI1_P_ODR : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR124

Control Register 124
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AXI1_PRIRLX : no description available
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

CKE_STAT : no description available
bits : 16 - 17 (2 bit)
access : read-only

RESERVED : no description available
bits : 18 - 23 (6 bit)
access : read-only

MEM_RST_VAL : no description available
bits : 24 - 24 (1 bit)
access : read-only

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR125

Control Register 125
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_RST_DELAY : no description available
bits : 0 - 15 (16 bit)
access : read-write

DLL_RST_ADJ_DLY : no description available
bits : 16 - 23 (8 bit)
access : read-write

PHY_WRLAT : no description available
bits : 24 - 28 (5 bit)
access : read-only

RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only

CR126

Control Register 126
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UP_ERR_STAT : no description available
bits : 0 - 6 (7 bit)
access : read-only

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

PHY_RDLAT : no description available
bits : 8 - 13 (6 bit)
access : read-write

RESERVED : no description available
bits : 14 - 23 (10 bit)
access : read-only

PHY_RDDATA_EN : no description available
bits : 24 - 29 (6 bit)
access : read-only

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-write

CR127

Controla Register 127
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRAM_CK_DI : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enables

#1 : 1

Disabled clk is gated

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only

CR08

Control Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR128

Control Register 128
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR129

Control Register 129
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR130

Control Register 130
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR131

Control Register 131
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYUPD_INT : Holds the PHY t CTRLUPD_INTERVAL timing parameter. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the UP_ERR_STAT parameter.
bits : 0 - 31 (32 bit)
access : read-write

CR132

Control Register 132
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLAT_ADJ : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

WRLAT_ADJ : no description available
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 31 (19 bit)
access : read-only

CR133

Control Register 133
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR134

Control Register 134
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR135

Control Register 135
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR136

Control Register 136
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR137

Control Register 137
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

PHYCTL_DL : no description available
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only

CR138

Control Register 138
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYDRAM_CK_DIS : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

PHYDRAM_CK_EN : no description available
bits : 8 - 10 (3 bit)
access : read-write

RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only

PHY_WRLV_MXDL : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR139

Control Register 139
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_WRLV_EN : no description available
bits : 0 - 7 (8 bit)
access : read-write

PHY_WRLV_DLL : no description available
bits : 8 - 15 (8 bit)
access : read-write

PHY_WRLV_LOAD : no description available
bits : 16 - 23 (8 bit)
access : read-write

PHY_WRLV_RESPLAT : no description available
bits : 24 - 31 (8 bit)
access : read-write

CR140

Control Register 140
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_WRLV_WW : no description available
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-only

CR141

Control Register 141
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_WRLV_RESP : no description available
bits : 0 - 31 (32 bit)
access : read-write

CR142

Control Register 142
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_WRLV_MAX : no description available
bits : 0 - 31 (32 bit)
access : read-write

CR143

Control Register 143
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLV_MXDL : no description available
bits : 0 - 15 (16 bit)
access : read-write

RDLV_GAT_MXDL : Defines the maximum number of delay elements that may be included in the gate delay line. This parameter is used by the hardware gate training logic and is only applicable when the MC is programmed for the following memory systems: DDR3 (dram_class = 'b0110)
bits : 16 - 31 (16 bit)
access : read-write

CR09

Control Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only

NO_MRR : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

No restrictions on MRR commands during initialization.

#1 : 1

Do not issue MRR commands during DLL initialization of the DRAM memories.

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR144

Control Register 144
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_RDLV_EN : no description available
bits : 0 - 7 (8 bit)
access : read-write

PHY_RDLV_DLL : no description available
bits : 8 - 15 (8 bit)
access : read-write

PHY_RDLV_LOAD : no description available
bits : 16 - 23 (8 bit)
access : read-write

PHY_RDLVL_RES : no description available
bits : 24 - 31 (8 bit)
access : read-write

CR145

Control Register 145
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_RDLV_RR : no description available
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-only

CR146

Control Register 146
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_RDLVL_RESP : no description available
bits : 0 - 31 (32 bit)
access : read-write

CR147

Control Register 147
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLV_RESP_MASK : no description available
bits : 0 - 19 (20 bit)
access : read-write

RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only

CR148

Control Register 148
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLV_GATE_RESP_MASK : no description available
bits : 0 - 19 (20 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

RDLVL_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR149

Control Register 149
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_GATE_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

RDLV_GT_CHKENS : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 31 (23 bit)
access : read-only

CR150

Control Register 150
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_RDLVLMAX : no description available
bits : 0 - 31 (32 bit)
access : read-write

CR151

Control Register 151
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLVL_DQ_ZERO_CNT : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

RDLV_GAT_DQ_ZERO_CNT : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

RDLV_ERR_STA : no description available
bits : 16 - 29 (14 bit)
access : read-only

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only

CR152

Control Register 152
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDLV_REFINT : no description available
bits : 0 - 15 (16 bit)
access : read-write

RDLV_GTREFINT : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR153

Control Register 153
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

EN_1T_TMG : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 31 (23 bit)
access : read-only

CR154

Control Register 154
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 11 (12 bit)
access : read-only

PAD_ZQ_CMP_OUT_SMP : no description available
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

7 cycles (Default)

#01 : 01

15 cycles

#10 : 10

23 cycles

#11 : 11

31 cycles

End of enumeration elements list.

PAD_ZQ_HW_FOR : no description available
bits : 14 - 14 (1 bit)
access : read-write

RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only

DDR_SEL_ZQ_PAD_Contr : no description available
bits : 16 - 17 (2 bit)
access : read-write

DDR_SEL_PAD_Contr : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

PAD_ZQ_MODE : no description available
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

#0 : 0

No pad calibration issued (Default)

#1 : 1

Pad calibration issued whenever memory controller issues a external memory short or Long (ZQCL or ZQCS) commands, including during memory initialization and after self refresh exit (provided controller has been configured for this).

#10 : 10

pad calibration issued whenever memory controller drives only long calibration command to the external memory (ZQCL), including during memory initialization.

#11 : 11

reserved

End of enumeration elements list.

RESERVED : no description available
bits : 23 - 26 (4 bit)
access : read-only

PAD_ZQ_EARLY_CMP_EN_TIMER : no description available
bits : 27 - 31 (5 bit)
access : read-write

CR155

Control Register 155
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAD_ODT_BYTE0 : no description available
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

termination disabled

#001 : 001

120 Ohm

#010 : 010

60 Ohm

#011 : 011

40 Ohm

#100 : 100

30 Ohm

#101 : 101

24 Ohm

#110 : 110

20 Ohm

#111 : 111

17 Ohm

End of enumeration elements list.

PAD_ODT_BYTE1 : no description available
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 000

termination disabled

#001 : 001

120 Ohm

#010 : 010

60 Ohm

#011 : 011

40 Ohm

#100 : 100

30 Ohm

#101 : 101

24 Ohm

#110 : 110

20 Ohm

#111 : 111

17 Ohm

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

AXI0_COBUF : Control for AXI0_COBUF signal.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Response returned when command and data have been received by the port.

#1 : 1

Response returned when command accepted into the memory controller command queue and all associated data has been received by the AXI data port.

End of enumeration elements list.

AXI1_COBUF : Control for AXI1_COBUF signal.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Response returned when command and data have been received by the port.

#1 : 1

Response returned when command accepted into the memory controller core command queue and all associated data has been received by the AXI data port.

End of enumeration elements list.

AXI0_AWCACHE : no description available
bits : 10 - 10 (1 bit)
access : read-write

AXI1_AWCACHE : no description available
bits : 11 - 11 (1 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

PAD_IBE_SEL0 : no description available
bits : 16 - 16 (1 bit)
access : read-write

PAD_IBE_SEL1 : no description available
bits : 17 - 17 (1 bit)
access : read-write

PAD_IBE0 : no description available
bits : 18 - 18 (1 bit)
access : read-write

PAD_IBE1 : no description available
bits : 19 - 19 (1 bit)
access : read-write

RESERVED : no description available
bits : 20 - 24 (5 bit)
access : read-only

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR156

Control Register 156
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only

PAD_ZQ_HW_PU_RES : no description available
bits : 1 - 5 (5 bit)
access : read-write

PAD_ZQ_HW_PD_RES : no description available
bits : 6 - 10 (5 bit)
access : read-write

RESERVED : no description available
bits : 11 - 11 (1 bit)
access : read-only

PAD_ZQ_HW_IN_PROG : no description available
bits : 12 - 12 (1 bit)
access : read-write

RESERVED : no description available
bits : 13 - 31 (19 bit)
access : read-only

CR157

Control Register 157
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAD_IBE : no description available
bits : 0 - 1 (2 bit)
access : read-write

RD_PEND_UFLO : no description available
bits : 2 - 2 (1 bit)
access : read-write

RD_PEND_OFLO : no description available
bits : 3 - 3 (1 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

RD_PEND_CNT : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR158

Control Register 158
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWR : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only

CR159

Control Register 159
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR10

Control Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRST_PWRON : no description available
bits : 0 - 31 (32 bit)
access : read-write

CR160

Control Register 160
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR161

Control Register 161
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TODTH_WR : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

TODTH_RD : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

ODT_EN : Enables the use of the DRAM ODT pin.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

The ODT output will not be used.

#1 : 1

The Controller will assert and deassert the ODT output to DRAM as needed

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR11

Control Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKE_INACTIVE : no description available
bits : 0 - 31 (32 bit)
access : read-write

CR12

Control Register 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CASLAT_LIN : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

WRLAT : no description available
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR13

Control Register 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TBST_INT_INTERVAL : no description available
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

TCCD : no description available
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

TRRD : no description available
bits : 16 - 23 (8 bit)
access : read-write

TRC : no description available
bits : 24 - 31 (8 bit)
access : read-write

CR14

Control Register 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRAS_MIN : no description available
bits : 0 - 7 (8 bit)
access : read-write

TWTR : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

TRP : no description available
bits : 16 - 20 (5 bit)
access : read-write

RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only

TFAW : no description available
bits : 24 - 29 (6 bit)
access : read-write

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only

CR15

Control Register 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR01

Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MAX_ROW_REG : no description available
bits : 0 - 4 (5 bit)
access : read-only

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

MAX_COL_REG : no description available
bits : 8 - 11 (4 bit)
access : read-only

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

MAX_CS_REG : no description available
bits : 16 - 16 (1 bit)
access : read-only

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR16

Control Register 16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

TRTP : no description available
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

TMRD : no description available
bits : 24 - 28 (5 bit)
access : read-write

RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only

PHY00

PHY Register 00
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OE_END : no description available
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

OE_START : no description available
bits : 4 - 6 (3 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

TSEL_END : no description available
bits : 8 - 11 (4 bit)
access : read-write

TSEL_START : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY01

PHY Register 01
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OE_END : no description available
bits : 0 - 3 (4 bit)
access : read-write

OE_START : no description available
bits : 4 - 7 (4 bit)
access : read-write

TSEL_END : no description available
bits : 8 - 11 (4 bit)
access : read-write

TSEL_START : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY02

PHY Register 02
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Gate_CFG : Coarse adjust of gate open time.
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 18 (16 bit)
access : read-only

RD_DL_SET : no description available
bits : 19 - 21 (3 bit)
access : read-write

RESERVED : no description available
bits : 22 - 24 (3 bit)
access : read-only

WRLVL_CLKDL : no description available
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

No change

#1 : 1

Adds extra clock to the PHY if the delay is at max value, it is not already asserted, and the rising edge has not been located.

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only

SW_HALF_CYCLE_SHIFT : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Adds a half clock delay to the write level delay line.

End of enumeration elements list.

RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only

EN_HALF_CAS : no description available
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not adjust

#1 : 1

Adjust the DQS gate by 1/2 clock forward.

End of enumeration elements list.

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only

PHY03

PHY Register 03
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_START_POINT : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only

PHY04

PHY Register 04
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

DLL_WRITE_DL : DLL Write delay
bits : 8 - 14 (7 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-only

PHY10

PHY Register 10
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPBK_START : no description available
bits : 0 - 0 (1 bit)
access : read-write

LPBK_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-write

RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only

LPBK_DM_DATA : no description available
bits : 4 - 7 (4 bit)
access : read-write

LPBK_DQ_DATA : Reports the actual data or expected data, depending on the setting of the PHY02[RD_DL_SET] parameter bit.
bits : 8 - 23 (16 bit)
access : read-write

DQS_ERROR_STATUS : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

PHY11

PHY Register 11
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DLL has not locked

#1 : 1

DLL is locked

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

DLL_LOCK_VALUE : no description available
bits : 8 - 15 (8 bit)
access : read-write

LOCK : no description available
bits : 16 - 23 (8 bit)
access : read-write

DLL_UNLOCK_VALUE : no description available
bits : 24 - 31 (8 bit)
access : read-write

PHY12

PHY Register 12
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DLL has not locked

#1 : 1

DLL is locked

End of enumeration elements list.

DEC_OUT_RD : Holds the encoded value for the read delay line for this slice.
bits : 1 - 7 (7 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-write

DEC_OUT_WR : Holds the encoded value for the clock write delay line for this slice.
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write

PHY13

PHY Register 13
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEC_OUT_WR_DQS : Reports the encoded value for the clock write DQS delay line
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR17

Control Register 17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMOD : no description available
bits : 0 - 7 (8 bit)
access : read-write

TRAS_MAX : no description available
bits : 8 - 24 (17 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

PHY16

PHY Register 01
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OE_END : no description available
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

OE_START : no description available
bits : 4 - 6 (3 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

TSEL_END : no description available
bits : 8 - 11 (4 bit)
access : read-write

TSEL_START : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY17

PHY Register 17
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OE_END : no description available
bits : 0 - 3 (4 bit)
access : read-write

OE_START : no description available
bits : 4 - 7 (4 bit)
access : read-write

TSEL_END : no description available
bits : 8 - 11 (4 bit)
access : read-write

TSEL_START : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY18

PHY Register 18
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Gate_CFG : Coarse adjust of gate open time.
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 18 (16 bit)
access : read-only

RD_DL_SET : no description available
bits : 19 - 21 (3 bit)
access : read-write

RESERVED : no description available
bits : 22 - 24 (3 bit)
access : read-only

WRLVL_CLKDL : no description available
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

No change

#1 : 1

Adds extra clock to the PHY if the delay is at max value, it is not already asserted, and the rising edge has not been located.

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only

SW_HALF_CYCLE_SHIFT : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Adds a half clock delay to the write level delay line.

End of enumeration elements list.

RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only

EN_HALF_CAS : no description available
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not adjust

#1 : 1

Adjust the DQS gate by 1/2 clock forward.

End of enumeration elements list.

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only

PHY19

PHY Register 19
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_START_POINT : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only

PHY20

PHY Register 20
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

DLL_WRITE_DL : DLL Write delay
bits : 8 - 14 (7 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-only

PHY26

PHY Register 26
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPBK_START : no description available
bits : 0 - 0 (1 bit)
access : read-write

LPBK_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-write

RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only

LPBK_DM_DATA : no description available
bits : 4 - 7 (4 bit)
access : read-write

LPBK_DQ_DATA : Reports the actual data or expected data, depending on the setting of the PHY02[RD_DL_SET] parameter bit.
bits : 8 - 23 (16 bit)
access : read-write

DQS_ERROR_STATUS : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

PHY27

PHY Register 27
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DLL has not locked

#1 : 1

DLL is locked

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

DLL_LOCK_VALUE : no description available
bits : 8 - 15 (8 bit)
access : read-write

LOCK : no description available
bits : 16 - 23 (8 bit)
access : read-write

DLL_UNLOCK_VALUE : no description available
bits : 24 - 31 (8 bit)
access : read-write

PHY28

PHY Register 28
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DLL has not locked

#1 : 1

DLL is locked

End of enumeration elements list.

DEC_OUT_RD : Holds the encoded value for the read delay line for this slice.
bits : 1 - 7 (7 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-write

DEC_OUT_WR : Holds the encoded value for the clock write delay line for this slice.
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write

PHY29

PHY Register 29
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEC_OUT_WR_DQS : Reports the encoded value for the clock write DQS delay line
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR18

Control Register 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCKE : no description available
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

TCKESR : no description available
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY32

PHY Register 32
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OE_END : no description available
bits : 0 - 3 (4 bit)
access : read-write

OE_START : no description available
bits : 4 - 7 (4 bit)
access : read-write

TSEL_END : no description available
bits : 8 - 11 (4 bit)
access : read-write

TSEL_START : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY33

PHY Register 33
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OE_END : no description available
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

OE_START : no description available
bits : 4 - 6 (3 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

TSEL_END : no description available
bits : 8 - 11 (4 bit)
access : read-write

TSEL_START : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY34

PHY Register 34
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Gate_CFG : Coarse adjust of gate open time.
bits : 0 - 2 (3 bit)
access : read-write

RESERVED : no description available
bits : 3 - 18 (16 bit)
access : read-only

RD_DL_SET : no description available
bits : 19 - 21 (3 bit)
access : read-write

RESERVED : no description available
bits : 22 - 24 (3 bit)
access : read-only

WRLVL_CLKDL : no description available
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

No change

#1 : 1

Adds extra clock to the PHY if the delay is at max value, it is not already asserted, and the rising edge has not been located.

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-only

SW_HALF_CYCLE_SHIFT : no description available
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Adds a half clock delay to the write level delay line.

End of enumeration elements list.

RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only

EN_HALF_CAS : no description available
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not adjust

#1 : 1

Adjust the DQS gate by 1/2 clock forward.

End of enumeration elements list.

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only

PHY35

PHY Register 35
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_START_POINT : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only

PHY36

PHY Register 36
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

DLL_WRITE_DL : DLL Write delay
bits : 8 - 14 (7 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-only

PHY42

PHY Register 42
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPBK_START : no description available
bits : 0 - 0 (1 bit)
access : read-write

LPBK_STATUS : no description available
bits : 1 - 1 (1 bit)
access : read-write

RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only

LPBK_DM_DATA : no description available
bits : 4 - 7 (4 bit)
access : read-write

LPBK_DQ_DATA : Reports the actual data or expected data, depending on the setting of the PHY02[RD_DL_SET] parameter bit.
bits : 8 - 23 (16 bit)
access : read-write

DQS_ERROR_STATUS : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

PHY43

PHY Register 43
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DLL has not locked

#1 : 1

DLL is locked

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

DLL_LOCK_VALUE : no description available
bits : 8 - 15 (8 bit)
access : read-write

LOCK : no description available
bits : 16 - 23 (8 bit)
access : read-write

DLL_UNLOCK_VALUE : no description available
bits : 24 - 31 (8 bit)
access : read-write

PHY44

PHY Register 44
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLL_LOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

DLL has not locked

#1 : 1

DLL is locked

End of enumeration elements list.

DEC_OUT_RD : Holds the encoded value for the read delay line for this slice.
bits : 1 - 7 (7 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-write

DEC_OUT_WR : Holds the encoded value for the clock write delay line for this slice.
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write

PHY45

PHY Register 45
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEC_OUT_WR_DQS : Reports the encoded value for the clock write DQS delay line
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR19

Control Register 19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

PHY49

PHY Register 49
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

PHY_RDLV_DL : PHY Read Level Delay
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

PHY50

PHY Register 50
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only

CLEAR_FIFO : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action

#1 : 1

Clear the FIFO

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

EN_SW_HALF_CYCLE : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Hardware automatically controls any shifting needed for the write level delay line.

#1 : 1

The setting in PHY_GATE_CR[SW_HALF_CYCLE_SHIFT] bit defines the shift. If the user chooses to control the half cycle shift manually, it is important that PHY_GATE_CR[SW_HALF_CYCLE_SHIFT] be cleared to 'b0 if the delay is less than a 1/2 cycle and set to 'b1 if the delay is greater than a 1/2 cycle. It is recommended to allow the hardware to control this automatically.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 10 (2 bit)
access : read-only

DDR_SEL : no description available
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

non-LPDDR2 mode

#1 : 1

LPDDR2 mode

End of enumeration elements list.

DDR3_MODE : no description available
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No Action

#1 : 1

Generate Pulse (DDR3 memories)

End of enumeration elements list.

DFI_MOBILE_EN : no description available
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PHY gating logic configured for standard DDR

#1 : 1

PHY gating logic configured for Mobile (LPDDR2) operating logic. The DRAM DQS signals are assumed to be pulled down on the board.

End of enumeration elements list.

RESERVED : no description available
bits : 14 - 31 (18 bit)
access : read-only

Enumeration:

#0 : 0

PHY logic configured for standard DDR operation

#1 : 1

PHY gating logic configured for Mobile (LPDDR2) gating operation. The DRAM DQS signals are assumed to be pulled down on the board.

End of enumeration elements list.

PHY52

PHY Register 52
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

tsel_rd_value_dm : Termination select read value for the data mask
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-write

tsel_off_value_dm : Termination select off value for the data mask
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-write

tsel_rd_value_dqs : Termination select read value for the data strobe
bits : 8 - 8 (1 bit)
access : read-write

RESERVED : no description available
bits : 9 - 11 (3 bit)
access : read-write

tsel_off_value_dqs : Termination select off value for the data strobe
bits : 12 - 12 (1 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-write

tsel_rd_value_data : Termination select read value for the data
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 19 (3 bit)
access : read-write

tsel_off_value_data : Termination select off value for the data
bits : 20 - 20 (1 bit)
access : read-write

RESERVED : no description available
bits : 21 - 31 (11 bit)
access : read-write

CR20

Control Register 20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

WRITEINTERP : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

The memory does not support read commands interrupting write commands.

#1 : 1

The memory does support read commands interrupting write commands

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

AP : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable auto pre-charge mode. Memory banks will stay open until another request requires this bank, the maximum open memory clocks has elapsed,or a refresh command closes all the blanks.

#1 : 1

Enable auto pre-charge mode. All read and write transactions must be terminated by an auto pre-charge command. If a transaction consists of multiple read or write bursts, only the last command is issued with an auto pre-charge.

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR21

Control Register 21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCMAP : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable concurrent auto precharge.

#1 : 1

Enable concurrent auto precharge.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

TRAS_LOCKOUT : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

tRAS lockout not supported by memory.

#1 : 1

tRAS lockout supported by memory.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only

TRCD_INT : no description available
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR22

Control Register 22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

TDAL : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only

CR23

Control register 23
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDLL : no description available
bits : 0 - 15 (16 bit)
access : read-write

TMRR : no description available
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

BSTLEN : no description available
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#010 : 010

4 memory words. Applicable for these memory systems: LPDDR2 (dram_class = 0101).

#011 : 011

8 memory words. Applicable for these memory systems: LPDDR2 (dram_class = 0101) DDR3 (dram_class = 0110)

End of enumeration elements list.

RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only

CR24

Control Register 24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRP_AB : no description available
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-only

DIMM_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Enable registered DIMM operation

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

ADD_MIR : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Standard pinout (for each chip select).

#1 : 1

Mirrored wiring (for each chip select).

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR25

Control Register 25
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREF : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action.

#1 : 1

Issue refresh to the DRAM memories.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

AUTO_RFM : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Issue refresh on the next memory burst boundary, even if the current command is not complete.

#1 : 1

Issue refresh on the next command boundary.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only

TREF_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable refresh commands.

#1 : 1

Enable refresh commands.

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only

CR26

Control Register 26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRFC : no description available
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

TREF : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR27

Control Register 27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR28

Control Register 28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TREF_INT : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR29

Control Register 29
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPDEX : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR30

Control Register 30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXPDLL : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR31

Control Register 31
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXSR : no description available
bits : 0 - 15 (16 bit)
access : read-write

TXSNR : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR02

Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TINIT : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR32

Control Register 32
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR33

Control Register 33
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWUP_SREF_EX : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable.

#1 : 1

Enable. If this option is being used.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

SREF_EX_NOREF : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Allow automatic refresh.

#1 : 1

Inhibit automatic refresh.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-write

EN_QK_SREF : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Continue memory initialization.

#1 : 1

Interrupt memory initialization and enter self-refresh mode.

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

CKE_DELAY : no description available
bits : 24 - 26 (3 bit)
access : read-write

RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only

CR34

Control Register 34
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LP_REFEN : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Refreshes still occur.

#1 : 1

Refreshes do not occur.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

RESERVED : no description available
bits : 2 - 7 (6 bit)
access : read-only

CKSRE : no description available
bits : 8 - 11 (4 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

CKSRX : no description available
bits : 16 - 19 (4 bit)
access : read-write

RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only

CR35

Control Register 35
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-write

LP_CMD : no description available
bits : 8 - 15 (8 bit)
access : write-only

LP_ST : no description available
bits : 16 - 21 (6 bit)
access : read-only

RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only

LP_ARBST : no description available
bits : 24 - 27 (4 bit)
access : read-only

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only

CR36

Control register 36
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPAUTO : no description available
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0 : 0

(For all bits) Disable automatic entry into this low power state.

#1 : 1

(For all bits) Enable automatic entry into this low power state. The state will be entered automatically when the proper counters expire.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

LP_AEXEN : no description available
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0 : 0

(For all bits) Disable automatic exit from this low power state.

#1 : 1

(For all bits) Enable automatic exit from this low power state. The state will be exited automatically when a read or write command enters the memory controller core command queue.

End of enumeration elements list.

RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only

LP_AMEMEN : no description available
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#0 : 0

(For all bits) Disable memory clock gating when automatically entering into this low power state.

#1 : 1

(For all bits) Enable memory clock gating when automatically entering into this low power state.

End of enumeration elements list.

RESERVED : no description available
bits : 18 - 31 (14 bit)
access : read-only

CR37

Control Register 37
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LP_A_PD_IDL : no description available
bits : 0 - 11 (12 bit)
access : read-write

RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only

LP_A_SR_IDL : no description available
bits : 16 - 23 (8 bit)
access : read-write

LP_A_SR_MC_IDL : no description available
bits : 24 - 31 (8 bit)
access : read-write

CR38

Control Register 38
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

FREQ_CHG_EN : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only

FRQ_CHG_HOEN : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

FREQ_CHG_HOCL : no description available
bits : 24 - 24 (1 bit)
access : write-only

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR39

Control Register 39
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQ_CH_DLLOFF : no description available
bits : 0 - 1 (2 bit)
access : read-write

RESERVED : no description available
bits : 2 - 7 (6 bit)
access : read-only

PHY_INI_STA : no description available
bits : 8 - 15 (8 bit)
access : read-write

PHY_INI_COM : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR40

Control Register 40
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only

CURR_REG_CP : no description available
bits : 24 - 24 (1 bit)
access : read-only

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR41

Control Register 41
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHY_INI_STRT_INI_DIS : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Allow the frequency change request signal to assert.

#1 : 1

Disable the frequency change request signal assertion.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only

CR42

Control Register 42
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR43

Control Register 43
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR44

Control Register 44
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR45

Control Register 45
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRMD : no description available
bits : 0 - 25 (26 bit)
access : read-write

RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only

CR46

Control Register 46
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRW_STAT : no description available
bits : 0 - 7 (8 bit)
access : read-only

RMD : no description available
bits : 8 - 24 (17 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR47

Control Register 47
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERI_MRR_DA : no description available
bits : 0 - 15 (16 bit)
access : read-only

AU_TMPCHK_VAL : no description available
bits : 16 - 19 (4 bit)
access : read-only

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

REF_AU_TMPCHK : no description available
bits : 24 - 31 (8 bit)
access : read-write

CR03

Control Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TINIT3 : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR48

Control Register 48
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR0_DA_0 : no description available
bits : 0 - 15 (16 bit)
access : read-write

MR1_DA_0 : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR49

Control Register 49
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR2_DA_0 : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR50

Control Register 50
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR51

Control Register 51
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR_SINDA0 : no description available
bits : 0 - 15 (16 bit)
access : read-write

MR3_DA0 : no description available
bits : 16 - 31 (16 bit)
access : read-write

CR52

Control Register 52
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR8_DA0 : no description available
bits : 0 - 7 (8 bit)
access : read-only

MR16_DA0 : no description available
bits : 8 - 15 (8 bit)
access : read-write

MR17_DA0 : no description available
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only

CR53

Control Register 53
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR54

Control Register 54
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR55

Control Register 55
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR56

Control Register 56
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only

CR57

Control Register 57
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only

CTRL_RAW : no description available
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

ECC not being used.

#01 : 01

ECC reporting is on, but no attempts to correct.

#10 : 10

No ECC RAM storage available.

#11 : 11

ECC reporting and correcting on.

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only

CR58

Control Register 58
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FWC : no description available
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

No action.

#1 : 1

Force a write check.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only

XOR_CHK_BITS : no description available
bits : 8 - 21 (14 bit)
access : read-write

RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only

ECC_DIS_WCRER : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Allow the ECC codes for the entire user word to be corrupted. (Default)

#1 : 1

Disable the corruption. The ECC codes written to memory will match the new write data written to memory.

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only

CR59

Control Register 59
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECC_U_ADR : no description available
bits : 0 - 31 (32 bit)
access : read-only

CR60

Control Register 60
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECC_U_SYND : no description available
bits : 0 - 6 (7 bit)
access : read-only

RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-only

CR61

Control Register 61
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECC_U_DATA : no description available
bits : 0 - 31 (32 bit)
access : read-only

CR62

Control Register 62
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECC_C_ADDR : no description available
bits : 0 - 31 (32 bit)
access : read-only

CR63

Control Register 63
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ECC_C_SYND : no description available
bits : 0 - 5 (6 bit)
access : read-only

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only

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DDRMC

Peripheral Memory Blocks

Registers

CR00

CR04

CR64

CR65

CR66

CR67

CR68

CR69

CR70

CR71

CR72

CR73

CR74

CR75

CR76

CR77

CR78

CR79

CR05

CR80

CR81

CR82

CR83

CR84

CR85

CR86

CR87

CR88

CR89

CR90

CR91

CR92

CR93

CR94

CR95

CR06

CR96

CR97

CR98

CR99

CR100

CR101

CR102

CR103

CR104

CR105

CR106

CR107

CR108

CR109

CR110

CR111

CR07

CR112

CR113

CR114

CR115

CR116

CR117

CR118

CR119

CR120

CR121

CR122

CR123

CR124

CR125

CR126

CR127

CR08

CR128

CR129

CR130

CR131

CR132

CR133