Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
Chip Select Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
#1 : 1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_BE is asserted for data write only.
#1 : 1
FB_BE is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
#01 : 01
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
#1 : 1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-aligned on FB_AD.
#1 : 1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 cycle (default for all but FB_CS0 )
#01 : 01
2 cycles
#10 : 10
3 cycles
#11 : 11
4 cycles (default for FB_CS0 )
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
#01 : 01
When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
#10 : 10
When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
#11 : 11
When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
#01 : 01
Assert FB_CSn on the second rising clock edge after the address is asserted.
#10 : 10
Assert FB_CSn on the third rising clock edge after the address is asserted.
#11 : 11
Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
#1 : 1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
#1 : 1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip-select is invalid.
#1 : 1
Chip-select is valid.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write accesses are allowed.
#1 : 1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding address bit in CSAR is used in the chip-select decode.
#1 : 1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
#1 : 1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_BE is asserted for data write only.
#1 : 1
FB_BE is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
#01 : 01
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
#1 : 1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-aligned on FB_AD.
#1 : 1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 cycle (default for all but FB_CS0 )
#01 : 01
2 cycles
#10 : 10
3 cycles
#11 : 11
4 cycles (default for FB_CS0 )
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
#01 : 01
When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
#10 : 10
When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
#11 : 11
When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
#01 : 01
Assert FB_CSn on the second rising clock edge after the address is asserted.
#10 : 10
Assert FB_CSn on the third rising clock edge after the address is asserted.
#11 : 11
Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
#1 : 1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
#1 : 1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip-select is invalid.
#1 : 1
Chip-select is valid.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write accesses are allowed.
#1 : 1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding address bit in CSAR is used in the chip-select decode.
#1 : 1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
#1 : 1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_BE is asserted for data write only.
#1 : 1
FB_BE is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
#01 : 01
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
#1 : 1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-aligned on FB_AD.
#1 : 1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 cycle (default for all but FB_CS0 )
#01 : 01
2 cycles
#10 : 10
3 cycles
#11 : 11
4 cycles (default for FB_CS0 )
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
#01 : 01
When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
#10 : 10
When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
#11 : 11
When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
#01 : 01
Assert FB_CSn on the second rising clock edge after the address is asserted.
#10 : 10
Assert FB_CSn on the third rising clock edge after the address is asserted.
#11 : 11
Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
#1 : 1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
#1 : 1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Address Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip-select is invalid.
#1 : 1
Chip-select is valid.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write accesses are allowed.
#1 : 1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding address bit in CSAR is used in the chip-select decode.
#1 : 1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select port Multiplexing Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 11 (12 bit)
access : read-only
GROUP5 : FlexBus Signal Group 5 Multiplex control
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_TA
#0001 : 0001
FB_CS3 . You must also write 1b to CSCR[AA].
#0010 : 0010
FB_BE_7_0 . You must also write 1b to CSCR[AA].
End of enumeration elements list.
GROUP4 : FlexBus Signal Group 4 Multiplex control
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_TBST
#0001 : 0001
FB_CS2
#0010 : 0010
FB_BE_15_8
End of enumeration elements list.
GROUP3 : FlexBus Signal Group 3 Multiplex control
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_CS5
#0001 : 0001
FB_TSIZ1
#0010 : 0010
FB_BE_23_16
End of enumeration elements list.
GROUP2 : FlexBus Signal Group 2 Multiplex control
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_CS4
#0001 : 0001
FB_TSIZ0
#0010 : 0010
FB_BE_31_24
End of enumeration elements list.
GROUP1 : FlexBus Signal Group 1 Multiplex control
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
FB_ALE
#0001 : 0001
FB_CS1
#0010 : 0010
FB_TS
End of enumeration elements list.
Chip Select Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
#1 : 1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_BE is asserted for data write only.
#1 : 1
FB_BE is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
#01 : 01
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
#1 : 1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-aligned on FB_AD.
#1 : 1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 cycle (default for all but FB_CS0 )
#01 : 01
2 cycles
#10 : 10
3 cycles
#11 : 11
4 cycles (default for FB_CS0 )
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
#01 : 01
When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
#10 : 10
When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
#11 : 11
When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
#01 : 01
Assert FB_CSn on the second rising clock edge after the address is asserted.
#10 : 10
Assert FB_CSn on the third rising clock edge after the address is asserted.
#11 : 11
Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
#1 : 1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
#1 : 1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Address Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
Chip Select Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip-select is invalid.
#1 : 1
Chip-select is valid.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write accesses are allowed.
#1 : 1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding address bit in CSAR is used in the chip-select decode.
#1 : 1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V : Valid
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip-select is invalid.
#1 : 1
Chip-select is valid.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 7 (7 bit)
access : read-only
WP : Write Protect
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write accesses are allowed.
#1 : 1
Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only
BAM : Base Address Mask
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding address bit in CSAR is used in the chip-select decode.
#1 : 1
The corresponding address bit in CSAR is a don't care in the chip-select decode.
End of enumeration elements list.
Chip Select Control Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only
BSTW : Burst-Write Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
#1 : 1
Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BSTR : Burst-Read Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
#1 : 1
Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
End of enumeration elements list.
BEM : Byte-Enable Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FB_BE is asserted for data write only.
#1 : 1
FB_BE is asserted for data read and write accesses.
End of enumeration elements list.
PS : Port Size
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit port size. Valid data is sampled and driven on FB_D[31:0].
#01 : 01
8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
End of enumeration elements list.
AA : Auto-Acknowledge Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
#1 : 1
Enabled. Internal transfer acknowledge is asserted as specified by WS.
End of enumeration elements list.
BLS : Byte-Lane Shift
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not shifted. Data is left-aligned on FB_AD.
#1 : 1
Shifted. Data is right-aligned on FB_AD.
End of enumeration elements list.
WS : Wait States
bits : 10 - 15 (6 bit)
access : read-write
WRAH : Write Address Hold or Deselect
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
1 cycle (default for all but FB_CS0 )
#01 : 01
2 cycles
#10 : 10
3 cycles
#11 : 11
4 cycles (default for FB_CS0 )
End of enumeration elements list.
RDAH : Read Address Hold or Deselect
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
#01 : 01
When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
#10 : 10
When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
#11 : 11
When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
End of enumeration elements list.
ASET : Address Setup
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
#01 : 01
Assert FB_CSn on the second rising clock edge after the address is asserted.
#10 : 10
Assert FB_CSn on the third rising clock edge after the address is asserted.
#11 : 11
Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
End of enumeration elements list.
EXTS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
#1 : 1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
End of enumeration elements list.
SWSEN : Secondary Wait State Enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
#1 : 1
Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
End of enumeration elements list.
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
SWS : Secondary Wait States
bits : 26 - 31 (6 bit)
access : read-write
Chip Select Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only
BA : Base Address
bits : 16 - 31 (16 bit)
access : read-write
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