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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1D8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ID

HWTXBUF

CAPLENGTH

HCIVERSION

HCSPARAMS

HCCPARAMS

DCIVERSION

DCCPARAMS

HWRXBUF

USBCMD

USBSTS

USBINTR

FRINDEX

DEVICEADDR

PERIODICLISTBASE

ENDPTLISTADDR

ASYNCLISTADDR

BURSTSIZE

TXFILLTUNING

ENDPTNAK

ENDPTNAKEN

PORTSC1

OTGSC

USBMODE

ENDPTSETUPSTAT

ENDPTPRIME

ENDPTFLUSH

ENDPTSTAT

ENDPTCOMPLETE

ENDPTCTRL0

ENDPTCTRL1

HWGENERAL

ENDPTCTRL2

ENDPTCTRL3

HWHOST

GPTIMER0LD

GPTIMER0CTRL

GPTIMER1LD

GPTIMER1CTRL

ENDPTCTRL4

SBUSCFG

ENDPTCTRL5

HWDEVICE


ID

Identification register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ID ID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID RESERVED NID RESERVED REVISION RESERVED

ID : no description available
bits : 0 - 5 (6 bit)
access : read-only

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

NID : no description available
bits : 8 - 13 (6 bit)
access : read-only

RESERVED : no description available
bits : 14 - 15 (2 bit)
access : read-only

REVISION : no description available
bits : 16 - 23 (8 bit)
access : read-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


HWTXBUF

TX Buffer Hardware Parameters
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWTXBUF HWTXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXBURST RESERVED TXCHANADD RESERVED

TXBURST : no description available
bits : 0 - 7 (8 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXCHANADD : no description available
bits : 16 - 23 (8 bit)
access : read-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


CAPLENGTH

Capability Register Length
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPLENGTH CAPLENGTH read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CAPLENGTH

CAPLENGTH : no description available
bits : 0 - 7 (8 bit)
access : read-only


HCIVERSION

Host Controller Interface Version
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCIVERSION HCIVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCIVERSION

HCIVERSION : no description available
bits : 0 - 15 (16 bit)
access : read-only


HCSPARAMS

Host Controller Structural Parameters
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCSPARAMS HCSPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N_PORTS PPC RESERVED N_PCC N_CC PI RESERVED N_PTT N_TT RESERVED

N_PORTS : no description available
bits : 0 - 3 (4 bit)
access : read-only

PPC : no description available
bits : 4 - 4 (1 bit)
access : read-only

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

N_PCC : no description available
bits : 8 - 11 (4 bit)
access : read-only

N_CC : no description available
bits : 12 - 15 (4 bit)
access : read-only

Enumeration:

#0 : 0

There is no internal Companion Controller and port-ownership hand-off is not supported.

#1 : 1

There are internal companion controller(s) and port-ownership hand-offs is supported.

End of enumeration elements list.

PI : no description available
bits : 16 - 16 (1 bit)
access : read-only

RESERVED : no description available
bits : 17 - 19 (3 bit)
access : read-only

N_PTT : no description available
bits : 20 - 23 (4 bit)
access : read-only

N_TT : no description available
bits : 24 - 27 (4 bit)
access : read-only

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only


HCCPARAMS

Host Controller Capability Parameters
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCCPARAMS HCCPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC PFL ASP RESERVED IST EECP RESERVED

ADC : no description available
bits : 0 - 0 (1 bit)
access : read-only

PFL : no description available
bits : 1 - 1 (1 bit)
access : read-only

ASP : no description available
bits : 2 - 2 (1 bit)
access : read-only

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

IST : no description available
bits : 4 - 7 (4 bit)
access : read-only

EECP : no description available
bits : 8 - 15 (8 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


DCIVERSION

Device Controller Interface Version
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCIVERSION DCIVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCIVERSION

DCIVERSION : no description available
bits : 0 - 15 (16 bit)
access : read-only


DCCPARAMS

Device Controller Capability Parameters
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCCPARAMS DCCPARAMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEN RESERVED DC HC RESERVED

DEN : no description available
bits : 0 - 4 (5 bit)
access : read-only

RESERVED : no description available
bits : 5 - 6 (2 bit)
access : read-only

DC : no description available
bits : 7 - 7 (1 bit)
access : read-only

HC : no description available
bits : 8 - 8 (1 bit)
access : read-only

RESERVED : no description available
bits : 9 - 31 (23 bit)
access : read-only


HWRXBUF

RX Buffer Hardware Parameters
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWRXBUF HWRXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXBURST RXADD RESERVED

RXBURST : no description available
bits : 0 - 7 (8 bit)
access : read-only

RXADD : no description available
bits : 8 - 15 (8 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


USBCMD

USB Command Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCMD USBCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS RST FS1 PSE ASE IAA RESERVED ASP RESERVED ASPE RESERVED SUTW ATDTW FS2 ITC RESERVED

RS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RST : no description available
bits : 1 - 1 (1 bit)
access : read-write

FS1 : no description available
bits : 2 - 3 (2 bit)
access : read-write

PSE : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not process the Periodic Schedule

#1 : 1

Use the PERIODICLISTBASE register to access the Periodic Schedule.

End of enumeration elements list.

ASE : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not process the Asynchronous Schedule.

#1 : 1

Use the ASYNCLISTADDR register to access the Asynchronous Schedule.

End of enumeration elements list.

IAA : no description available
bits : 6 - 6 (1 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

ASP : no description available
bits : 8 - 9 (2 bit)
access : read-write

RESERVED : no description available
bits : 10 - 10 (1 bit)
access : read-only

ASPE : no description available
bits : 11 - 11 (1 bit)
access : read-write

RESERVED : no description available
bits : 12 - 12 (1 bit)
access : read-only

SUTW : no description available
bits : 13 - 13 (1 bit)
access : read-write

ATDTW : no description available
bits : 14 - 14 (1 bit)
access : read-write

FS2 : no description available
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#000 : 000

1024 elements (4096 bytes) Default value

#001 : 001

512 elements (2048 bytes)

End of enumeration elements list.

ITC : no description available
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

#0 : 0

Immediate (no threshold)

#1 : 1

1 micro-frame

#10 : 10

2 micro-frames

#100 : 100

4 micro-frames

#1000 : 1000

8 micro-frames

#10000 : 10000

16 micro-frames

#100000 : 100000

32 micro-frames

#1000000 : 1000000

64 micro-frames

End of enumeration elements list.

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


USBSTS

USB Status Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBSTS USBSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UI UEI PCI FRI SEI AAI URI SRI SLI RESERVED ULPII RESERVED HCH RCL PS AS NAKI RESERVED TI0 TI1 RESERVED

UI : no description available
bits : 0 - 0 (1 bit)
access : read-write

UEI : no description available
bits : 1 - 1 (1 bit)
access : read-write

PCI : no description available
bits : 2 - 2 (1 bit)
access : read-write

FRI : no description available
bits : 3 - 3 (1 bit)
access : read-write

SEI : no description available
bits : 4 - 4 (1 bit)
access : read-write

AAI : no description available
bits : 5 - 5 (1 bit)
access : read-write

URI : no description available
bits : 6 - 6 (1 bit)
access : read-write

SRI : no description available
bits : 7 - 7 (1 bit)
access : read-write

SLI : no description available
bits : 8 - 8 (1 bit)
access : read-write

RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only

ULPII : no description available
bits : 10 - 10 (1 bit)
access : read-write

RESERVED : no description available
bits : 11 - 11 (1 bit)
access : read-only

HCH : no description available
bits : 12 - 12 (1 bit)
access : read-write

RCL : no description available
bits : 13 - 13 (1 bit)
access : read-write

PS : no description available
bits : 14 - 14 (1 bit)
access : read-write

AS : no description available
bits : 15 - 15 (1 bit)
access : read-write

NAKI : no description available
bits : 16 - 16 (1 bit)
access : read-only

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

TI0 : no description available
bits : 24 - 24 (1 bit)
access : read-write

TI1 : no description available
bits : 25 - 25 (1 bit)
access : read-write

RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only


USBINTR

Interrupt Enable Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBINTR USBINTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UE UEE PCE FRE SEE AAE URE SRE SLE RESERVED ULPIE RESERVED NAKE RESERVED UAIE UPIE RESERVED TIE0 TIE1 RESERVED

UE : no description available
bits : 0 - 0 (1 bit)
access : read-write

UEE : no description available
bits : 1 - 1 (1 bit)
access : read-write

PCE : no description available
bits : 2 - 2 (1 bit)
access : read-write

FRE : no description available
bits : 3 - 3 (1 bit)
access : read-write

SEE : no description available
bits : 4 - 4 (1 bit)
access : read-write

AAE : no description available
bits : 5 - 5 (1 bit)
access : read-write

URE : no description available
bits : 6 - 6 (1 bit)
access : read-write

SRE : no description available
bits : 7 - 7 (1 bit)
access : read-write

SLE : no description available
bits : 8 - 8 (1 bit)
access : read-write

RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only

ULPIE : no description available
bits : 10 - 10 (1 bit)
access : read-write

RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-write

NAKE : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 17 (1 bit)
access : read-only

UAIE : no description available
bits : 18 - 18 (1 bit)
access : read-write

UPIE : no description available
bits : 19 - 19 (1 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

TIE0 : no description available
bits : 24 - 24 (1 bit)
access : read-write

TIE1 : no description available
bits : 25 - 25 (1 bit)
access : read-write

RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only


FRINDEX

USB Frame Index
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRINDEX FRINDEX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRINDEX RESERVED

FRINDEX : no description available
bits : 0 - 13 (14 bit)
access : read-write

Enumeration:

#000 : 000

(1024) 12

#001 : 001

(512) 11

#010 : 010

(256) 10

#011 : 011

(128) 9

#100 : 100

(64) 8

#101 : 101

(32) 7

#110 : 110

(16) 6

#111 : 111

(8) 5

End of enumeration elements list.

RESERVED : no description available
bits : 14 - 31 (18 bit)
access : read-only


DEVICEADDR

Device Address
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USB1
reset_Mask : 0x0

DEVICEADDR DEVICEADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED USBADRA USBADR

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only

USBADRA : no description available
bits : 24 - 24 (1 bit)
access : read-write

USBADR : no description available
bits : 25 - 31 (7 bit)
access : read-write


PERIODICLISTBASE

Frame List Base Address
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USB1
reset_Mask : 0x0

PERIODICLISTBASE PERIODICLISTBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED BASEADR

RESERVED : no description available
bits : 0 - 11 (12 bit)
access : read-only

BASEADR : no description available
bits : 12 - 31 (20 bit)
access : read-write


ENDPTLISTADDR

Endpoint List Address
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USB1
reset_Mask : 0x0

ENDPTLISTADDR ENDPTLISTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED EPBASE

RESERVED : no description available
bits : 0 - 10 (11 bit)
access : read-only

EPBASE : no description available
bits : 11 - 31 (21 bit)
access : read-write


ASYNCLISTADDR

Next Asynch. Address
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : USB1
reset_Mask : 0x0

ASYNCLISTADDR ASYNCLISTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ASYBASE

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

ASYBASE : no description available
bits : 5 - 31 (27 bit)
access : read-write


BURSTSIZE

Programmable Burst Size
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BURSTSIZE BURSTSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPBURST TXPBURST RESERVED

RXPBURST : no description available
bits : 0 - 7 (8 bit)
access : read-write

TXPBURST : no description available
bits : 8 - 16 (9 bit)
access : read-write

RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only


TXFILLTUNING

TX FIFO Fill Tuning
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFILLTUNING TXFILLTUNING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXSCHOH TXSCHHEALTH RESERVED TXFIFOTHRES RESERVED

TXSCHOH : no description available
bits : 0 - 7 (8 bit)
access : read-write

TXSCHHEALTH : no description available
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

TXFIFOTHRES : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


ENDPTNAK

Endpoint NAK
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTNAK ENDPTNAK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRN RESERVED EPTN RESERVED

EPRN : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

EPTN : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


ENDPTNAKEN

Endpoint NAK Enable
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTNAKEN ENDPTNAKEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPRNE RESERVED EPTNE RESERVED

EPRNE : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

EPTNE : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


PORTSC1

Port Status and Control
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORTSC1 PORTSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCS CSC PE PEC OCA OCC FPR SUSP PR HSP LS PP PO PIC PTC WKCN WKDC WKOC PHCD PFSC PTS1 PSPD PTW STS PTS2

CCS : no description available
bits : 0 - 0 (1 bit)
access : read-write

CSC : no description available
bits : 1 - 1 (1 bit)
access : read-write

PE : no description available
bits : 2 - 2 (1 bit)
access : read-write

PEC : no description available
bits : 3 - 3 (1 bit)
access : read-write

OCA : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#1 : 1

This port currently has an over-current condition

#0 : 0

This port does not have an over-current condition.

End of enumeration elements list.

OCC : no description available
bits : 5 - 5 (1 bit)
access : read-write

FPR : no description available
bits : 6 - 6 (1 bit)
access : read-write

SUSP : no description available
bits : 7 - 7 (1 bit)
access : read-write

PR : no description available
bits : 8 - 8 (1 bit)
access : read-write

HSP : no description available
bits : 9 - 9 (1 bit)
access : read-write

LS : no description available
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

SE0

#10 : 10

J-state

#01 : 01

K-state

#11 : 11

Undefined

End of enumeration elements list.

PP : no description available
bits : 12 - 12 (1 bit)
access : read-write

PO : no description available
bits : 13 - 13 (1 bit)
access : read-write

PIC : no description available
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

Port indicators are off

#01 : 01

Amber

#10 : 10

Green

#11 : 11

Undefined

End of enumeration elements list.

PTC : no description available
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

TEST_MODE_DISABLE

#0001 : 0001

J_STATE

#0010 : 0010

K_STATE

#0011 : 0011

SE0 (host) / NAK (device)

#0100 : 0100

Packet

#0101 : 0101

FORCE_ENABLE_HS

#0110 : 0110

FORCE_ENABLE_FS

#0111 : 0111

FORCE_ENABLE_LS

End of enumeration elements list.

WKCN : no description available
bits : 20 - 20 (1 bit)
access : read-write

WKDC : no description available
bits : 21 - 21 (1 bit)
access : read-write

WKOC : no description available
bits : 22 - 22 (1 bit)
access : read-write

PHCD : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

Disable PHY clock

#0 : 0

Enable PHY clock

End of enumeration elements list.

PFSC : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#1 : 1

Forced to full speed

#0 : 0

Normal operation

End of enumeration elements list.

PTS1 : no description available
bits : 25 - 25 (1 bit)
access : read-write

PSPD : no description available
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 00

Full Speed

#01 : 01

Low Speed

#10 : 10

High Speed

#11 : 11

Undefined

End of enumeration elements list.

PTW : no description available
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reserved

#1 : 1

Select the 16-bit UTMI interface [30 MHz]

End of enumeration elements list.

STS : no description available
bits : 29 - 29 (1 bit)
access : read-write

PTS2 : no description available
bits : 30 - 31 (2 bit)
access : read-write


OTGSC

On-The-Go Status and control
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTGSC OTGSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VD RESERVED RESERVED OT RESERVED IDPU RESERVED ID AVV ASV BSV BSE 1msT DPS RESERVED IDIS AVVIS ASVIS BSVIS BSEIS 1MSS DPIS RESERVED IDIE AVVIE ASVIE BSVIE BSEIE 1MSSE DPIE RESERVED

VD : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only

OT : no description available
bits : 3 - 3 (1 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

IDPU : no description available
bits : 5 - 5 (1 bit)
access : read-write

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

ID : no description available
bits : 8 - 8 (1 bit)
access : read-write

AVV : no description available
bits : 9 - 9 (1 bit)
access : read-write

ASV : no description available
bits : 10 - 10 (1 bit)
access : read-write

BSV : no description available
bits : 11 - 11 (1 bit)
access : read-write

BSE : no description available
bits : 12 - 12 (1 bit)
access : read-write

1msT : no description available
bits : 13 - 13 (1 bit)
access : read-write

DPS : no description available
bits : 14 - 14 (1 bit)
access : read-write

RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only

IDIS : no description available
bits : 16 - 16 (1 bit)
access : read-write

AVVIS : no description available
bits : 17 - 17 (1 bit)
access : read-write

ASVIS : no description available
bits : 18 - 18 (1 bit)
access : read-write

BSVIS : no description available
bits : 19 - 19 (1 bit)
access : read-write

BSEIS : no description available
bits : 20 - 20 (1 bit)
access : read-write

1MSS : no description available
bits : 21 - 21 (1 bit)
access : read-write

DPIS : no description available
bits : 22 - 22 (1 bit)
access : read-write

RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only

IDIE : no description available
bits : 24 - 24 (1 bit)
access : read-write

AVVIE : no description available
bits : 25 - 25 (1 bit)
access : read-write

ASVIE : no description available
bits : 26 - 26 (1 bit)
access : read-write

BSVIE : no description available
bits : 27 - 27 (1 bit)
access : read-write

BSEIE : no description available
bits : 28 - 28 (1 bit)
access : read-write

1MSSE : no description available
bits : 29 - 29 (1 bit)
access : read-write

DPIE : no description available
bits : 30 - 30 (1 bit)
access : read-write

RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only


USBMODE

USB Device Mode
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBMODE USBMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM ES SLOM SDIS RESERVED RESERVED RESERVED

CM : no description available
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Idle [Default for combination host/device]

#01 : 01

Reserved

#10 : 10

Device Controller [Default for device only controller]

#11 : 11

Host Controller [Default for host only controller]

End of enumeration elements list.

ES : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Little Endian [Default]

#1 : 1

Big Endian

End of enumeration elements list.

SLOM : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Setup Lockouts On (default);

#1 : 1

Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .

End of enumeration elements list.

SDIS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 14 (10 bit)
access : read-only

RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


ENDPTSETUPSTAT

Endpoint Setup Status
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTSETUPSTAT ENDPTSETUPSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDPTSETUPSTAT RESERVED

ENDPTSETUPSTAT : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


ENDPTPRIME

Endpoint Initialization
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTPRIME ENDPTPRIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERB RESERVED PETB RESERVED

PERB : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

PETB : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


ENDPTFLUSH

Endpoint De-Initialize
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTFLUSH ENDPTFLUSH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FERB RESERVED FETB RESERVED

FERB : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

FETB : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


ENDPTSTAT

Endpoint Status
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENDPTSTAT ENDPTSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERBR RESERVED ETBR RESERVED

ERBR : no description available
bits : 0 - 5 (6 bit)
access : read-only

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

ETBR : no description available
bits : 16 - 21 (6 bit)
access : read-only

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


ENDPTCOMPLETE

Endpoint Complete
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCOMPLETE ENDPTCOMPLETE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERCE RESERVED ETCE RESERVED

ERCE : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

ETCE : no description available
bits : 16 - 21 (6 bit)
access : read-write

RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only


ENDPTCTRL0

Endpoint Control0
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL0 ENDPTCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RESERVED RXT RESERVED RXE RESERVED TXS RESERVED TXT RESERVED TXE RESERVED

RXS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

RXT : no description available
bits : 2 - 3 (2 bit)
access : read-write

RESERVED : no description available
bits : 4 - 6 (3 bit)
access : read-only

RXE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXS : no description available
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : no description available
bits : 17 - 17 (1 bit)
access : read-only

TXT : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 22 (3 bit)
access : read-only

TXE : no description available
bits : 23 - 23 (1 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


ENDPTCTRL1

Endpoint Controln
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL1 ENDPTCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXD : no description available
bits : 1 - 1 (1 bit)
access : read-write

RXT : no description available
bits : 2 - 3 (2 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

RXI : no description available
bits : 5 - 5 (1 bit)
access : read-write

RXR : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXS : no description available
bits : 16 - 16 (1 bit)
access : read-write

TXD : no description available
bits : 17 - 17 (1 bit)
access : read-write

TXT : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

TXI : no description available
bits : 21 - 21 (1 bit)
access : read-write

TXR : no description available
bits : 22 - 22 (1 bit)
access : read-write

TXE : no description available
bits : 23 - 23 (1 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


HWGENERAL

Hardware General
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWGENERAL HWGENERAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED PHYW PHYM SM RESERVED

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only

PHYW : no description available
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

#00 : 00

Reserved

#01 : 01

16-bit wide data bus [30MHZ clock from the transciever]

#10 : 10

Reserved

#11 : 11

Reserved

End of enumeration elements list.

PHYM : no description available
bits : 6 - 8 (3 bit)
access : read-only

Enumeration:

#000 : 000

UTMI/UMTI+

#001 : 001

ULPI DDR

#010 : 010

ULPI

#011 : 011

Serial

End of enumeration elements list.

SM : no description available
bits : 9 - 10 (2 bit)
access : read-only

Enumeration:

#00 : 00

No Serial Engine, always use parallel signaling.

#01 : 01

Serial Engine present, always use serial signaling for FS/LS.

#10 : 10

Software programmable - Reset to use parallel signaling for FS/LS

#11 : 11

Software programmable - Reset to use serial signaling for FS/LS

End of enumeration elements list.

RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only


ENDPTCTRL2

Endpoint Controln
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL2 ENDPTCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXD : no description available
bits : 1 - 1 (1 bit)
access : read-write

RXT : no description available
bits : 2 - 3 (2 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

RXI : no description available
bits : 5 - 5 (1 bit)
access : read-write

RXR : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXS : no description available
bits : 16 - 16 (1 bit)
access : read-write

TXD : no description available
bits : 17 - 17 (1 bit)
access : read-write

TXT : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

TXI : no description available
bits : 21 - 21 (1 bit)
access : read-write

TXR : no description available
bits : 22 - 22 (1 bit)
access : read-write

TXE : no description available
bits : 23 - 23 (1 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


ENDPTCTRL3

Endpoint Controln
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL3 ENDPTCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXD : no description available
bits : 1 - 1 (1 bit)
access : read-write

RXT : no description available
bits : 2 - 3 (2 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

RXI : no description available
bits : 5 - 5 (1 bit)
access : read-write

RXR : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXS : no description available
bits : 16 - 16 (1 bit)
access : read-write

TXD : no description available
bits : 17 - 17 (1 bit)
access : read-write

TXT : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

TXI : no description available
bits : 21 - 21 (1 bit)
access : read-write

TXR : no description available
bits : 22 - 22 (1 bit)
access : read-write

TXE : no description available
bits : 23 - 23 (1 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


HWHOST

Host Hardware Parameters
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWHOST HWHOST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HC NPORT RESERVED

HC : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#1 : 1

Support host operation mode

#0 : 0

Not support

End of enumeration elements list.

NPORT : no description available
bits : 1 - 3 (3 bit)
access : read-only

RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only


GPTIMER0LD

General Purpose Timer #0 Load
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER0LD GPTIMER0LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD RESERVED

GPTLD : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


GPTIMER0CTRL

General Purpose Timer #0 Controller
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER0CTRL GPTIMER0CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTCNT GPTMODE RESERVED GPTRST GPTRUN

GPTCNT : no description available
bits : 0 - 23 (24 bit)
access : read-write

GPTMODE : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

One Shot Mode

#1 : 1

Repeat Mode

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 29 (5 bit)
access : read-only

GPTRST : no description available
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action

#1 : 1

Load counter value from GPTLD bits in n_GPTIMER0LD

End of enumeration elements list.

GPTRUN : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stop counting

#1 : 1

Run

End of enumeration elements list.


GPTIMER1LD

General Purpose Timer #1 Load
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER1LD GPTIMER1LD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD RESERVED

GPTLD : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


GPTIMER1CTRL

General Purpose Timer #1 Controller
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPTIMER1CTRL GPTIMER1CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPTCNT GPTMODE RESERVED GPTRST GPTRUN

GPTCNT : no description available
bits : 0 - 23 (24 bit)
access : read-write

GPTMODE : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

One Shot Mode

#1 : 1

Repeat Mode

End of enumeration elements list.

RESERVED : no description available
bits : 25 - 29 (5 bit)
access : read-only

GPTRST : no description available
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action

#1 : 1

Load counter value from GPTLD bits in UOG_GPTIMER0LD

End of enumeration elements list.

GPTRUN : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stop counting

#1 : 1

Run

End of enumeration elements list.


ENDPTCTRL4

Endpoint Controln
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL4 ENDPTCTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXD : no description available
bits : 1 - 1 (1 bit)
access : read-write

RXT : no description available
bits : 2 - 3 (2 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

RXI : no description available
bits : 5 - 5 (1 bit)
access : read-write

RXR : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXS : no description available
bits : 16 - 16 (1 bit)
access : read-write

TXD : no description available
bits : 17 - 17 (1 bit)
access : read-write

TXT : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

TXI : no description available
bits : 21 - 21 (1 bit)
access : read-write

TXR : no description available
bits : 22 - 22 (1 bit)
access : read-write

TXE : no description available
bits : 23 - 23 (1 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


SBUSCFG

System Bus Config
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBUSCFG SBUSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHBBRST RESERVED

AHBBRST : no description available
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Incremental burst of unspecified length only

#001 : 001

INCR4 burst, then single transfer

#010 : 010

INCR8 burst, INCR4 burst, then single transfer

#011 : 011

INCR16 burst, INCR8 burst, INCR4 burst, then single transfer

#100 : 100

Reserved, don't use

#101 : 101

INCR4 burst, then incremental burst of unspecified length

#110 : 110

INCR8 burst, INCR4 burst, then incremental burst of unspecified length

#111 : 111

INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only


ENDPTCTRL5

Endpoint Controln
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPTCTRL5 ENDPTCTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXS RXD RXT RESERVED RXI RXR RXE RESERVED TXS TXD TXT RESERVED TXI TXR TXE RESERVED

RXS : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXD : no description available
bits : 1 - 1 (1 bit)
access : read-write

RXT : no description available
bits : 2 - 3 (2 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only

RXI : no description available
bits : 5 - 5 (1 bit)
access : read-write

RXR : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

TXS : no description available
bits : 16 - 16 (1 bit)
access : read-write

TXD : no description available
bits : 17 - 17 (1 bit)
access : read-write

TXT : no description available
bits : 18 - 19 (2 bit)
access : read-write

RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only

TXI : no description available
bits : 21 - 21 (1 bit)
access : read-write

TXR : no description available
bits : 22 - 22 (1 bit)
access : read-write

TXE : no description available
bits : 23 - 23 (1 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


HWDEVICE

Device Hardware Parameters
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWDEVICE HWDEVICE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC DEVEP RESERVED

DC : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#1 : 1

support device operation mode

#0 : 0

not support

End of enumeration elements list.

DEVEP : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only



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