Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDZST : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue timer operation (Default).
#1 : 1
Suspend the watchdog timer.
End of enumeration elements list.
WDBG : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue WDOG timer operation (Default).
#1 : 1
Suspend the watchdog timer.
End of enumeration elements list.
WDE : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Watchdog (Default).
#1 : 1
Enable the Watchdog.
End of enumeration elements list.
WDT : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect on WDOG_B (Default).
#1 : 1
Assert WDOG_B upon a Watchdog Time-out event.
End of enumeration elements list.
SRS : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Assert system reset signal.
#1 : 1
No effect on the system (Default).
End of enumeration elements list.
WDA : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Assert WDOG_B output.
#1 : 1
No effect on system (Default).
End of enumeration elements list.
SRE : software reset extension, an option way to generate software reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
using original way to generate software reset (default)
#1 : 1
using new way to generate software reset.
End of enumeration elements list.
WDW : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continue WDOG timer operation (Default).
#1 : 1
Suspend WDOG timer operation.
End of enumeration elements list.
WT : no description available
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
#0 : 0
- 0.5 Seconds (Default).
#1 : 1
- 1.0 Seconds.
#10 : 10
- 1.5 Seconds.
#11 : 11
- 2.0 Seconds.
#11111111 : 11111111
- 128 Seconds.
End of enumeration elements list.
Watchdog Service Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WSR : no description available
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
#101010101010101 : 101010101010101
Write to the Watchdog Service Register (WDOG_WSR).
#1010101010101010 : 1010101010101010
Write to the Watchdog Service Register (WDOG_WSR).
End of enumeration elements list.
Watchdog Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SFTW : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not the result of a software reset.
#1 : 1
Reset is the result of a software reset.
End of enumeration elements list.
TOUT : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not the result of a WDOG timeout.
#1 : 1
Reset is the result of a WDOG timeout.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only
POR : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not the result of a power on reset.
#1 : 1
Reset is the result of a power on reset.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-only
Watchdog Interrupt Control Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WICT : no description available
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
#1 : 1
WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
#100 : 100
WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
#11111111 : 11111111
WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 13 (6 bit)
access : read-only
WTIS : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt has occurred (Default).
#1 : 1
Interrupt has occurred
End of enumeration elements list.
WIE : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Interrupt (Default).
#1 : 1
Enable Interrupt.
End of enumeration elements list.
Watchdog Miscellaneous Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDE : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power Down Counter of WDOG is disabled.
#1 : 1
Power Down Counter of WDOG is enabled (Default).
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 15 (15 bit)
access : read-only
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