Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x11E4 byte (0x0)
mem_usage : registers
protection : not protected
Control Descriptor Cursor 1 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the cursor in pixels.
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the cursor in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
DCU4 Mode Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCU_MODE : DCU operating mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
DCU off (pixel clock active if enabled by I/O).
#01 : 01
Normal mode. Panel content controlled by layer configuration.
#10 : 10
Test mode. DCU disables all DMA fetches and all the pixels of an enabled layer take the value in the CLUT RAM selected by the respective LUOFFS field of control descriptor 4.
#11 : 11
Color Bar Generation. Panel content controlled by color bar registers.
End of enumeration elements list.
EN_GAMMA : Enables/Disables the Gamma Correction.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Gamma correction is disabled
#1 : 1
Gamma Correction is enabled
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External Synchronization. The PDI receives the SYNC (HSYNC, VSYNC) signals from external source.
#1 : 1
Internal Synchronization. PDI extracts the SYNC information from the digital RGB data. YCbCr Mode supports Internal Sync only. Therefore, when PDI_ MODE = 3, PDI_SYNC must be set to 0.
End of enumeration elements list.
SIG_EN : Enables the signature calculator block.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Signature calculator is disabled
#1 : 1
Signature calculator is enabled
End of enumeration elements list.
TAG_EN : Enables the calculation of CRC only on the safety layers.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC calculated over the whole area of interest (area of interest given by SIG_DESC registers)
#1 : 1
Calculates CRC only on safety enabled layers
End of enumeration elements list.
PDI_SLAVE_MODE : Enables PDI slave Mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PDI_MODE : Defines the different modes in which PDI is operating.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
8-bit monochrome data input
#01 : 01
16-bit RGB 565 format
#10 : 10
18-bit RGB 666 data format
#11 : 11
YCbCr data in 4:2:2 format
End of enumeration elements list.
PDI_NARROW_MODE : Enables the PDI Narrow Mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Narrow Mode is Disabled
#1 : 1
Narrow Mode is Enabled
End of enumeration elements list.
PDI_DE_MODE : Enables the PDI data Enable Mode. Here Data Enable is treated as an input.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Value on data Enable signal is ignored
#1 : 1
Data enable controls the write to the PDI FIFO
End of enumeration elements list.
PDI_BYTE_REV : Controls the byte ordering in Narrow Mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB is followed by MSB data
#1 : 1
MSB is followed by LSB data
End of enumeration elements list.
PDI_EN : Enables the PDI.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
RASTER_EN : Enables raster scanning of pixel data including the VSYNC and HSYNC signals and the pixel data. This bit takes effect immediately and does not require a transfer to the frame timing logic.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PDI_INTERPOL_EN : Control Bit to decide whether the conversion from YCbCr 4:2:2 to 4:4:4 needs to be done using interpolation or Chroma value is same for two pixels.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chroma value is same for two pixels
#1 : 1
Interpolation is enabled
End of enumeration elements list.
PDI_SYNC_LOCK : no description available
bits : 16 - 19 (4 bit)
access : read-write
BLEND_ITER : Defines the maximum number of pixels which are blended in the pixel blend stack.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
Reserved
#001 : 001
Reserved
#010 : 010
Two pixel blending (default)
#011 : 011
Three pixel blending
#100 : 100
Four pixel blending
#101 : 101
Five pixel blending
#110 : 110
Six plane blending
#111 : 111
Reserved
End of enumeration elements list.
DDR_MODE : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Off
#1 : 1
On
End of enumeration elements list.
ADDR : Two-bit value to be added to pixel red component for dithering.
bits : 24 - 25 (2 bit)
access : read-write
ADDG : Two bit Value to be added with pixel green component for dithering.
bits : 26 - 27 (2 bit)
access : read-write
ADDB : Two-bit value to be added to pixel blue component for dithering.
bits : 28 - 29 (2 bit)
access : read-write
EN_DITHER : Enable dithering mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DCU_SW_RESET : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action
#1 : 1
All DCU4 internal registers are forced into their reset state. User registers are not affected
End of enumeration elements list.
Global Protection Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 30 (31 bit)
access : read-only
HLB : Hard Lock Bit. This bit cannot be cleared once it is set by software. It can only be cleared by a system reset.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
All SLB's are write protected and cannot be modified
#1 : 1
All SLB's are accessible and can be modified
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x10030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x100CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x10168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x10204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x102A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Soft Lock Bit Layer 0 Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 16 (17 bit)
access : read-only
SLB_L0_7 : Soft Lock Bit for Control Desc L0_7 Register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L0_6 : Soft Lock Bit for Control Desc L0_6 Register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L0_5 : Soft Lock Bit for Control Desc L0_5 Register.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only
WEN_LO_7 : Write Enable for Soft Lock Bit SLB_L0_7.
bits : 21 - 21 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_LO_6 : Write Enable for Soft Lock Bit SLB_L0_6.
bits : 22 - 22 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_LO_5 : Write Enable for Soft Lock Bit SLB_L0_5.
bits : 23 - 23 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
SLB_L0_4 : Soft Lock Bit for Control Desc L0_4 Register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L0_3 : Soft Lock Bit for Control Desc L0_3 Register.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L0_2 : Soft Lock Bit for Control Desc L0_2 Register.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L0_1 : Soft Lock Bit for Control Desc L0_1 Register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
WEN_LO_4 : Write Enable for Soft Lock Bit SLB_L0_4.
bits : 28 - 28 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_LO_3 : Write Enable for Soft Lock Bit SLB_L0_3.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_LO_2 : Write Enable for Soft Lock Bit SLB_L0_2.
bits : 30 - 30 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_LO_1 : Write Enable for Soft Lock Bit SLB_L0_1.
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Soft Lock Bit Layer 1 Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 16 (17 bit)
access : read-only
SLB_L1_7 : Soft Lock Bit for Control Desc L1_7 Register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L1_6 : Soft Lock Bit for Control Desc L1_6 Register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L1_5 : Soft Lock Bit for Control Desc L1_5 Register.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only
WEN_L1_7 : Write Enable for Soft Lock Bit SLB_L1_7.
bits : 21 - 21 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L1_6 : Write Enable for Soft Lock Bit SLB_L1_6.
bits : 22 - 22 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L1_5 : Write Enable for Soft Lock Bit SLB_L1_5.
bits : 23 - 23 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
SLB_L1_4 : Soft Lock Bit for Control Desc L1_4 Register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L1_3 : Soft Lock Bit for Control Desc L1_3 Register.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L1_2 : Soft Lock Bit for Control Desc L1_2 Register.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L1_1 : Soft Lock Bit for Control Desc L1_1 Register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
WEN_L1_4 : Write Enable for Soft Lock Bit SLB_L1_4.
bits : 28 - 28 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L1_3 : Write Enable for Soft Lock Bit SLB_L1_3.
bits : 29 - 29 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L1_2 : Write Enable for Soft Lock Bit SLB_L1_2.
bits : 30 - 30 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L1_1 : Write Enable for Soft Lock Bit SLB_L1_1.
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Control Descriptor Ln_0 Register
address_offset : 0x10940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x109E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x10A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x10B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x10BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Soft Lock Display Size Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 26 (27 bit)
access : read-only
SLB_DISP : Soft Lock Bit for DISP_SIZE Register. This bit cannot be cleared once set by software. Can only be cleared by system reset.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 28 - 30 (3 bit)
access : read-only
WEN_DISP : Write Enable for Soft Lock Bit SLB_DISP.
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Control Descriptor Ln_5 Register
address_offset : 0x10C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x10D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x10DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x10E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Soft Lock Hsync/Vsync Parameter Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 25 (26 bit)
access : read-only
SLB_VSYNC : Soft Lock Bit for VSYNC Register.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_HSYNC : Soft Lock Bit for HSYNC Register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 28 - 29 (2 bit)
access : read-only
WEN_VSYNC : Write Enable for Soft Lock Bit SLB_VSYNC
bits : 30 - 30 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_HSYNC : Write Enable for Soft Lock Bit SLB_HSYNC.
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Soft Lock POL Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 26 (27 bit)
access : read-only
SLB_POL : Soft Lock Bit for SYN_POL Register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 28 - 30 (3 bit)
access : read-only
WEN_POL : Write Enable for Soft Lock Bit SLB_POL
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Control Descriptor Ln_0 Register
address_offset : 0x11500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x115A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x11648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x116EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x11790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Soft Lock L0 Transparency Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 25 (26 bit)
access : read-only
SLB_L0_BCOLOR : Soft Lock Bit for L0_BCOLOR Register.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L0_FCOLOR : Soft Lock Bit for L0_FCOLOR Register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 28 - 29 (2 bit)
access : read-only
WEN_L0_BCOLOR : Write Enable for Soft Lock Bit SLB_L0_BCOLOR
bits : 30 - 30 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L0_FCOLOR : Write Enable for Soft Lock Bit SLB_L0_FCOLOR
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Control Descriptor Ln_5 Register
address_offset : 0x11834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x118D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1197C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x11A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Soft Lock L1 Transparency Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 25 (26 bit)
access : read-only
SLB_L1_BCOLOR : Soft Lock Bit for L1_BCOLOR Register.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
SLB_L1_FCOLOR : Soft Lock Bit for L1_FCOLOR Register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Associated protected register is not locked and writeable
#1 : 1
Associated protected register is locked for write access
End of enumeration elements list.
RESERVED : no description available
bits : 28 - 29 (2 bit)
access : read-only
WEN_L1_BCOLOR : Write Enable for Soft Lock Bit SLB_L1_BCOLOR
bits : 30 - 30 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
WEN_L1_FCOLOR : Write Enable for Soft Lock Bit SLB_L1_FCOLOR
bits : 31 - 31 (1 bit)
access : write-only
Enumeration:
#0 : 0
SLB is not modified
#1 : 1
Value is written to SLB
End of enumeration elements list.
Control Descriptor Ln_0 Register
address_offset : 0x11C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x11DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_0 Register
address_offset : 0x12100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x1214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_1 Register
address_offset : 0x121A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x12250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x122F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x123A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x12448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x124C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x124F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x12598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x12640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x12A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x12D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x12DEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x12E98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x12F44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x12FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1309C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x13148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x131F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x132A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x139C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x13A70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x13B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x13BD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x13C80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x13D30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x13DE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x13E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x13F40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Background Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGND_B : Blue component of the default color displayed in the sectors where no layer is active.
bits : 0 - 7 (8 bit)
access : read-write
BGND_G : Green component of the default color displayed in the sectors where no layer is active.
bits : 8 - 15 (8 bit)
access : read-write
BGND_R : Red component of the default color displayed in the sectors where no layer is active.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x14680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x14734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x147E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1489C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x14950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x14A04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x14AB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x14B6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x14C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x15380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x15438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x154F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x155A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_1 Register
address_offset : 0x1560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x15660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x15718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x157D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_7 Register
address_offset : 0x15888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x15940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x15A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x15C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x15E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x160C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1617C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x16238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x162F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x163B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1646C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x16528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x165E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x166A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x16E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x16F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x16FC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x17080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x17140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x17200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x172C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x17380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x17440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x17C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x17CC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x17D88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x17E4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x17F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x17FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Display Size Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELTA_X : Sets the display size horizontal resolution (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
DELTA_Y : Sets the display size vertical resolution (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x18098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1815C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x18220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x18A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x18AC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x18B90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x18C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x18D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x18DE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x18EB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x18F78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x19040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1924 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x196C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_0 Register
address_offset : 0x19840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x1990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1990C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x199D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x19AA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_5 Register
address_offset : 0x19B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x19B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x19C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x19D08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x19D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x19DD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x19EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x19FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1A6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1A790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1A860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1A930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1AA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1AAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1ABA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1AC70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1AD40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1B580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1B654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1B728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1B7FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1B8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1B9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1BA78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1BB4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1BC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Horizontal Sync Parameter Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FP_H : HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
bits : 0 - 8 (9 bit)
access : read-write
RESERVED : no description available
bits : 9 - 10 (2 bit)
access : read-only
PW_H : HSYNC active pulse width (in pixel clock cycles).
bits : 11 - 19 (9 bit)
access : read-write
RESERVED : no description available
bits : 20 - 21 (2 bit)
access : read-only
BP_H : HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
bits : 22 - 30 (9 bit)
access : read-write
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1C480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1C558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1C630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1C708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1C7E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1C8B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1C990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1CA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1CB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1D00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1D28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1D3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1D49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1D50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_2 Register
address_offset : 0x1D578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1D654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1D730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x1D78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_5 Register
address_offset : 0x1D80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1D8E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1D9C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x1DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1DAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1DC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1DF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1E18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1E340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1E420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1E500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1E5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1E6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1E7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1E880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1E960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1EA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x1F300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x1F3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x1F4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x1F5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x1F690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x1F774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x1F858 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x1F93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x1FA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Vertical Sync Parameter Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FP_V : VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
bits : 0 - 8 (9 bit)
access : read-write
RESERVED : no description available
bits : 9 - 10 (2 bit)
access : read-only
PW_V : VSYNC active pulse width (in horizontal line cycles).
bits : 11 - 19 (9 bit)
access : read-write
RESERVED : no description available
bits : 20 - 21 (2 bit)
access : read-only
BP_V : VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
bits : 22 - 30 (9 bit)
access : read-write
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x20300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x203E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x204D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x205B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x206A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x20788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x20870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x20958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x20A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x21340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x2140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x2142C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x21518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x21604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_1 Register
address_offset : 0x216C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x216F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x217DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x218C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x2198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_7 Register
address_offset : 0x219B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x21AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x21C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x21F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x221C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x223C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x2248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x224B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x225A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x22690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_7 Register
address_offset : 0x2274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x22780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x22870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x22960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x22A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x22A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x22B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x23480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x23574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x23668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x2375C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x23850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x23944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x23A38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x23B2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x23C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Synchronize Polarity Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV_HS : Invert Horizontal synchronization signal.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSYNC signal not inverted (active HIGH).
#1 : 1
Invert HSYNC signal (active LOW).
End of enumeration elements list.
INV_VS : Invert Vertical synchronization signal.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
VSYNC signal not inverted (active HIGH).
#1 : 1
Invert VSYNC signal (active LOW).
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-write
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-write
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-write
NEG : Indicates if value at the output (pixel data output) needs to be negated.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output is to remain same
#1 : 1
Output to be negated
End of enumeration elements list.
INV_PXCK : Polarity change of Pixel Clock.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Display samples data on the falling edge
#1 : 1
Display samples data on the rising edge
End of enumeration elements list.
INV_PDI_CLK : Polarity of PDI input Clock.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCU4 samples data on the rising edge
#1 : 1
DCU4 samples data on the falling edge
End of enumeration elements list.
INV_PDI_VS : Polarity of PDI input VSYNC.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
VSYNC is active low
#1 : 1
VSYNC is active high
End of enumeration elements list.
INV_PDI_HS : Polarity of PDI input HSYNC.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSYNC is active low
#1 : 1
HSYNC is active high
End of enumeration elements list.
INV_PDI_DE : Polarity of PDI input data Enable.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
DE is active low
#1 : 1
DE is active high
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x24580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x24678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x24770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x24868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x24960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x24A58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x24B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x24C48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x24D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x256C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x257BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x258B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x259B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x25AB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x25BAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x25C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x25CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x25DA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x25EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x25F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x2620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x2650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x2680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x26840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x26940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x26A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_5 Register
address_offset : 0x26B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x26B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x26C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x26D40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x26E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x26E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x26F40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x27040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x2710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x2740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x27A00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x27B04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x27C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x27D0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x27E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x27F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Threshold Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT_BUF_LOW : Output buffer filling low Threshold (in pixels).This value is used to generate the underrun exception (UNDRUN in INT_STATUS).
bits : 0 - 7 (8 bit)
access : read-write
OUT_BUF_HIGH : Output buffer high threshold (in pixels). When the output buffer exceeds this value the datapath clock is suspended.
bits : 8 - 15 (8 bit)
access : read-write
LS_BF_VS : Lines before VS_BLANK threshold value. The LS_BF_VS status flag (in INT_STATUS) is set this number of lines before the VS_BLANK signal is asserted.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x28018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x2811C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x28220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x2A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x2AB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x2AE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x2B1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x2B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x2B84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x2BB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x2BEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VSYNC : Interrupt flag to indicate that the vertical synchronization phase has begun. If enabled, an interrupt is generated at the beginning of a frame.
bits : 0 - 0 (1 bit)
access : read-write
UNDRUN : Interrupt flag to indicate the output buffer underrun condition. Asserted when the panel needs data and the output buffer level is lower than or equal to the OUT_BUF_LOW threshold. Flag is cleared when the data in the output buffer is greater than threshold and CPU writes 1 to this bit.
bits : 1 - 1 (1 bit)
access : read-write
LS_BF_VS : Interrupt flag to indicate the Lines Before VS_BLANK event has been reached. The LS_BF_VS field in the Threshold register defines the timing of the event.
bits : 2 - 2 (1 bit)
access : read-write
VS_BLANK : Interrupt signal to indicate vertical blanking period. This is the period in which all the registers that affect the visible state of the layers need to be latched. This is needed so that CPU writes to the register while the display is being updated does not cause any errors. Interrupt can be cleared by writing 1 to this bit..
bits : 3 - 3 (1 bit)
access : read-write
CRC_READY : Interrupt flag to indicate CRC calculation is done and ready to be compared with precomputed CRC value by the software.
bits : 4 - 4 (1 bit)
access : read-write
CRC_OVERFLOW : Interrupt signal to indicate that CRC_ready has not been serviced and CRC has been calculated for the next frame
bits : 5 - 5 (1 bit)
access : read-write
P1_FIFO_LO_FLAG : Interrupt flag to indicate that the low threshold has been reached in the FIFO in position 1 (lowest) in the pixel blend stack.
bits : 6 - 6 (1 bit)
access : read-write
P1_FIFO_HI_FLAG : Interrupt flag to indicate that the high threshold has been reached in the FIFO in position 1 (lowest) in the pixel blend stack.
bits : 7 - 7 (1 bit)
access : read-write
P2_FIFO_LO_FLAG : Interrupt flag to indicate that the low threshold has been reached in the FIFO in position 2 in the pixel blend stack.
bits : 8 - 8 (1 bit)
access : read-write
P2_FIFO_HI_FLAG : Interrupt flag to indicate that the high threshold has been reached in the FIFO in position 2 in the pixel blend stack.
bits : 9 - 9 (1 bit)
access : read-write
PROG_END : Interrupt flag which indicates that the DCU4 has begun to transfer layer configuration from the layer control descriptor registers into the DCU4 functional block. Any register modification after this time and before LYR_TRANS_FINISH is asserted may or may not be included in this transfer.
bits : 10 - 10 (1 bit)
access : read-write
IPM_ERROR : Interrupt flag, which indicates that an error has occured in the Magenta line transaction.
bits : 11 - 11 (1 bit)
access : read-write
LYR_TRANS_FINISH : Interrupt flag to indicate that the transfer is complete of layer configuration from the layer control descriptor registers into the DCU4 functional block
bits : 12 - 12 (1 bit)
access : read-write
RESERVED : no description available
bits : 13 - 13 (1 bit)
access : read-only
DMA_TRANS_FINISH : Interrupt flag, which indicates that the DCU4 DMA has fetched the last pixel of data from the memory.
bits : 14 - 14 (1 bit)
access : read-write
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
P3_FIFO_LO_FLAG : Interrupt flag to indicate that the low threshold has been reached in the FIFO in position 3 in the pixel blend stack.
bits : 16 - 16 (1 bit)
access : read-write
P3_FIFO_HI_FLAG : Interrupt flag to indicate that the high threshold has been reached in the FIFO in position 3 in the pixel blend stack.
bits : 17 - 17 (1 bit)
access : read-write
P4_FIFO_LO_FLAG : Interrupt flag to indicate that the low threshold has been reached in the FIFO in position 4 in the pixel blend stack.
bits : 18 - 18 (1 bit)
access : read-write
P4_FIFO_HI_FLAG : Interrupt flag to indicate that the high threshold has been reached in the FIFO in position 4 in the pixel blend stack.
bits : 19 - 19 (1 bit)
access : read-write
P5_FIFO_LO_FLAG : Interrupt flag to indicate that the low threshold has been reached in the FIFO in position 5 in the pixel blend stack.
bits : 20 - 20 (1 bit)
access : read-write
P5_FIFO_HI_FLAG : Interrupt flag to indicate that the high threshold has been reached in the FIFO in position 5 in the pixel blend stack.
bits : 21 - 21 (1 bit)
access : read-write
P6_FIFO_LO_FLAG : Interrupt flag to indicate that the low threshold has been reached in the FIFO in position 6 in the pixel blend stack.
bits : 22 - 22 (1 bit)
access : read-write
P6_FIFO_HI_FLAG : Interrupt flag to indicate that the high threshold has been reached in the FIFO in position 6 in the pixel blend stack.
bits : 23 - 23 (1 bit)
access : read-write
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
P1_EMPTY : Interrupt flag to indicate that the FIFO in position 1 (lowest) in the pixel blend stack underflowed.
bits : 26 - 26 (1 bit)
access : read-write
P2_EMPTY : Interrupt flag to indicate that the FIFO in position 2 in the pixel blend stack underflowed.
bits : 27 - 27 (1 bit)
access : read-write
P3_EMPTY : Interrupt flag to indicate that the FIFO in position 3 in the pixel blend stack underflowed.
bits : 28 - 28 (1 bit)
access : read-write
P4_EMPTY : Interrupt flag to indicate that the FIFO in position 4 in the pixel blend stack underflowed.
bits : 29 - 29 (1 bit)
access : read-write
P5_EMPTY : Interrupt flag to indicate that the FIFO in position 5 in the pixel blend stack underflowed.
bits : 30 - 30 (1 bit)
access : read-write
P6_EMPTY : Interrupt flag to indicate that the FIFO in position 6 in the pixel blend stack underflowed.
bits : 31 - 31 (1 bit)
access : read-write
Control Descriptor Ln_8 Register
address_offset : 0x2C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x2F80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x2FB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x2FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_VSYNC : Mask for VSYNC interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
M_UNDRUN : Mask for M_UNDRUN interrupt flag.
bits : 1 - 1 (1 bit)
access : read-write
M_LS_BF_VS : Mask for LS_BF_VS interrupt flag.
bits : 2 - 2 (1 bit)
access : read-write
M_VS_BLANK : Mask for VS_BLANK interrupt flag.rupt can be cleared by writing 1 to this bit..
bits : 3 - 3 (1 bit)
access : read-write
M_CRC_READY : Mask for CRC_READY interrupt flag.
bits : 4 - 4 (1 bit)
access : read-write
M_CRC_OVERFLOW : Mask for CRC_OVERFLOW interrupt flag.
bits : 5 - 5 (1 bit)
access : read-write
M_P1_FIFO_LO_FLAG : Mask for P1_FIFO_LO_FLAG interrupt flag.
bits : 6 - 6 (1 bit)
access : read-write
M_P1_FIFO_HI_FLAG : Mask for P1_FIFO_HI_FLAG interrupt flag.
bits : 7 - 7 (1 bit)
access : read-write
M_P2_FIFO_LO_FLAG : Mask for P2_FIFO_LO_FLAG interrupt flag.
bits : 8 - 8 (1 bit)
access : read-write
M_P2_FIFO_HI_FLAG : Mask for P2_FIFO_HI_FLAG interrupt flag.
bits : 9 - 9 (1 bit)
access : read-write
M_PROG_END : Mask for PROG_END interrupt flag.
bits : 10 - 10 (1 bit)
access : read-write
M_IPM_ERROR : Mask for IPM_ERROR interrupt flag.
bits : 11 - 11 (1 bit)
access : read-write
M_LYR_TRANS_FINISH : Mask for SHDW_CMPLT interrupt flag.
bits : 12 - 12 (1 bit)
access : read-write
RESERVED : no description available
bits : 13 - 13 (1 bit)
access : read-only
M_DMA_TRANS_FINISH : Mask for DMA_TRANS_FINISH interrupt flag.
bits : 14 - 14 (1 bit)
access : read-write
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
M_P3_FIFO_LO_FLAG : Mask for P6_FIFO_LO_FLAG interrupt flag.
bits : 16 - 16 (1 bit)
access : read-write
M_P3_FIFO_HI_FLAG : Mask for P3_FIFO_HI_FLAG interrupt flag.
bits : 17 - 17 (1 bit)
access : read-write
M_P4_FIFO_LO_FLAG : Mask for P4_FIFO_LO_FLAG interrupt flag.
bits : 18 - 18 (1 bit)
access : read-write
M_P4_FIFO_HI_FLAG : Mask for P4_FIFO_HI_FLAG interrupt flag.
bits : 19 - 19 (1 bit)
access : read-write
M_P5_FIFO_LO_FLAG : Mask for P5_FIFO_LO_FLAG interrupt flag.
bits : 20 - 20 (1 bit)
access : read-write
M_P5_FIFO_HI_FLAG : Mask for P5_FIFO_HI_FLAG interrupt flag.
bits : 21 - 21 (1 bit)
access : read-write
M_P6_FIFO_LO_FLAG : Mask for P6_FIFO_LO_FLAG interrupt flag.
bits : 22 - 22 (1 bit)
access : read-write
M_P6_FIFO_HI_FLAG : Mask for P6_FIFO_HI_FLAG interrupt flag.
bits : 23 - 23 (1 bit)
access : read-write
RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only
M_P1_EMPTY : Mask for P1_EMPTY interrupt flag.
bits : 26 - 26 (1 bit)
access : read-write
M_P2_EMPTY : Mask for P2_EMPTY interrupt flag.
bits : 27 - 27 (1 bit)
access : read-write
M_P3_EMPTY : Mask for P3_EMPTY interrupt flag.
bits : 28 - 28 (1 bit)
access : read-write
M_P4_EMPTY : Mask for P4_EMPTY interrupt flag.
bits : 29 - 29 (1 bit)
access : read-write
M_P5_EMPTY : Mask for P5_EMPTY interrupt flag.
bits : 30 - 30 (1 bit)
access : read-write
M_P6_EMPTY : Mask for P6_EMPTY interrupt flag.
bits : 31 - 31 (1 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x3028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x3060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x3098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x30D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x3108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x3140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
COLBAR_1 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_1_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_1_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_1_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x34C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x34FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x3538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x3574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x35B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x35EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x3628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x3664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x36A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
COLBAR_2 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_2_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_2_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_2_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x3A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x3A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x3AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x3B00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x3B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x3B80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x3BC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
COLBAR_3 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_3_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_3_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_3_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x3C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x3C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Cursor 2 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : X position of the cursor in pixels
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
POSY : Y position of the cursor in pixels
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
COLBAR_4 Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_4_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_4_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_4_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x4000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x4044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x4088 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x40CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_2 Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_4 Register
address_offset : 0x4110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x4154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_6 Register
address_offset : 0x4198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x41DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x4220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
COLBAR_5 Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_5_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_5_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_5_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x4600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x4648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x4690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x46D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x4720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x4768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x47B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x47F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
COLBAR_6 Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_6_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_6_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_6_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x4840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
COLBAR_7 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_7_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_7_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_7_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x4C40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x4C8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x4CD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x4D24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x4D70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x4DBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x4E08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x4E54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x4EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
COLBAR_8 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COLBAR_8_B : Blue component value.
bits : 0 - 7 (8 bit)
access : read-write
COLBAR_8_G : Green component value.
bits : 8 - 15 (8 bit)
access : read-write
COLBAR_8_R : Red component value.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x52C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x5310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x5360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x53B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Divide Ratio Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_RATIO : Specifies the divide value for the input clock. Used to generate the pixel clock to support different types of displays. To divide by N, set the DIV_RATIO to (N - 1).
bits : 0 - 7 (8 bit)
access : read-write
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x5400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x5450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x54A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x54F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x5540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Sign Calculation 1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_HOR_SIZE : Horizontal size of window of interest of pixels for CRC calculations (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
SIG_VER_SIZE : Vertical size of the window of interest of pixels for CRC calculation (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x5980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x59D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x5A28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x5A7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x5AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x5B24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x5B78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x5BCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Sign Calculation 2 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIG_HOR_POS : Horizontal position of window of interest of pixels for CRC calculation (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
SIG_VER_POS : Vertical position of the window of interest of pixels for CRC calculation (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x5C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
CRC Value Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_VAL : The result of the CRC calculation for the value of the pixels on the safety layers
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_0 Register
address_offset : 0x6080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x60D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x6130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x6188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x61E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x6238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x6290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x62E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x6340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
PDI Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDI_CLK_DET : Status bit to inform the software that clock for the camera data has been detected.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
pdi_clk not detected
#1 : 1
pdi_clk is detected
End of enumeration elements list.
PDI_CLK_LOST : Status bit to inform the software that pdi_clk is lost.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
pdi_clk is present
#1 : 1
pdi_clk is lost
End of enumeration elements list.
PDI_DE_DET : Status bit to inform the software that data Enable for the camera data has been detected.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
pdi_de not detected
#1 : 1
pdi_de is detected
End of enumeration elements list.
PDI_HSYNC_DET : Status bit to inform the software that hsync for the camera data has been detected.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
pdi_hsync not detected
#1 : 1
pdi_hsync is detected
End of enumeration elements list.
PDI_VSYNC_DET : Status bit to inform the software that vsync for the camera data has been detected.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
pdi_vsync not detected
#1 : 1
pdi_vsync is detected
End of enumeration elements list.
PDI_LOCK_DET : Status bit to inform the software PDI is frame locked to the camera interface.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Waiting for frame to lock
#1 : 1
Frame lock is detected
End of enumeration elements list.
PDI_LOCK_LOST : Status bit to inform the software that frame lock is lost.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame is locked
#1 : 1
Frame lock is lost
End of enumeration elements list.
PDI_ECC_ERR1 : Status bit to inform the software about one bit error is detected.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
One bit ECC error is not detected.
#1 : 1
One bit ECC error detected
End of enumeration elements list.
PDI_ECC_ERR2 : Status bit to inform the software about multibit bit error that is detected.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multibit ECC error is not detected
#1 : 1
Multibit ECC error detected
End of enumeration elements list.
PDI_BLANKING_ERR : Status bit to inform the software that 80h,10h sequence is not present during the blanking period in internal sync mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Correct data sequence present in blanking period.
#1 : 1
Correct data sequence not present in blanking period.
End of enumeration elements list.
RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x67C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x67C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
PDI Status Mask Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_PDI_CLK_DET : Mask for PDI_CLK_DET interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
M_PDI_CLK_LOST : Mask for PDI_CLK_LOST interrupt flag.
bits : 1 - 1 (1 bit)
access : read-write
M_PDI_DE_DET : Mask for PDI_DE_DET interrupt flag.
bits : 2 - 2 (1 bit)
access : read-write
M_PDI_HSYNC_DET : Mask for PDI_HSYNC_DET interrupt flag.
bits : 3 - 3 (1 bit)
access : read-write
M_PDI_VSYNC_DET : Mask for PDI_VSYNC_DET interrupt flag.
bits : 4 - 4 (1 bit)
access : read-write
M_PDI_LOCK_DET : Mask for PDI_LOCK_DET interrupt flag.
bits : 5 - 5 (1 bit)
access : read-write
M_PDI_LOCK_LOST : Mask for PDI_LOCK_LOST interrupt flag.
bits : 6 - 6 (1 bit)
access : read-write
M_PDI_ECC_ERR1 : Mask for PDI_ECC_ERR1 interrupt flag.
bits : 7 - 7 (1 bit)
access : read-write
M_PDI_ECC_ERR2 : Mask for PDI_ECC_ERR2 interrupt flag.
bits : 8 - 8 (1 bit)
access : read-write
M_PDI_BLANKING_ERR : Mask for PDI_BLANKING_ERR interrupt flag.
bits : 9 - 9 (1 bit)
access : read-write
RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x681C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x6878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_6 Register
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x68D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x6930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x698C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x69E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x6A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x6AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Parameter Error Status 1 Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L : no description available
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_0 Register
address_offset : 0x6F40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x6FA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Parameter Error Status 2 Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L : no description available
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_2 Register
address_offset : 0x7000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x7060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x70C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x7120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x7180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x71E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x7240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x7700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x7764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x77C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x782C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x7890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x78F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x7958 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x79BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x7A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Parameter Error Status 3 Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISP_ERR : Interrupt occurs whenever width and height of display, pulse width (both vertical and horizontal sync) value is 0.
bits : 0 - 0 (1 bit)
access : read-write
SIG_ERR : Interrupt occurs whenever the area of interest specified by SIG_CALC register is outside the display size.
bits : 1 - 1 (1 bit)
access : read-write
HWC_ERR : Interrupt signal to indicate HWC error. This can occur if HWC position is out of display area or cursor memory is bigger than the HWC size. When this occurs, the HWC is disabled.
bits : 2 - 2 (1 bit)
access : read-write
RLE_ERR : Error signal to indicate that more than one layer has RLE mode enabled.
bits : 3 - 3 (1 bit)
access : read-write
RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x7F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x7F68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x7FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Cursor 3 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEFAULT_CURSOR_COLOR : Default pixel color value for the cursor. In the DCU4, the pixel value for the cursor is fixed for a particular frame.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 30 (7 bit)
access : read-only
CUR_EN : Cursor Enable signal.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cursor is disabled
#1 : 1
Enable the cursor
End of enumeration elements list.
Mask Parameter Error Status 1 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_L_PARR_ERR : Mask for L[31:0] interrupt flag.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x8038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x80A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x8108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x8170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x81D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x8240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Mask Parameter Error Status 2 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_L_PARR_ERR : Mask for L[63:32] interrupt flag.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_0 Register
address_offset : 0x8740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x87AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x8818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x8884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x88F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x895C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x89C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x8A34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x8AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_0 Register
address_offset : 0x8FC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Mask Parameter Error Status 3 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_DISP_ERR : Mask for DISP_ERR interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write
M_SIG_ERR : Mask for SIG_ERR interrupt flag.
bits : 1 - 1 (1 bit)
access : read-write
M_HWC_ERR : Mask for HWC_ERR interrupt flag.
bits : 2 - 2 (1 bit)
access : read-write
M_RLE_ERR : Mask for RLE_ERR interrupt flag.
bits : 3 - 3 (1 bit)
access : read-write
RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x9030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x90A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_5 Register
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0x9110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x9180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x91F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x9260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x92D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x9340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Threshold Input 1 Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_BUF_P1_LO : Low threshold for the FIFO in position 1 (lowest) in the pixel blend stack.
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-write
INP_BUF_P1_HI : High threshold for the FIFO in position 1 (lowest) in the pixel blend stack.
bits : 8 - 14 (7 bit)
access : read-write
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
INP_BUF_P2_LO : Low threshold for the FIFO in position 2 in the pixel blend stack.
bits : 16 - 22 (7 bit)
access : read-write
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only
INP_BUF_P2_HI : High threshold for the FIFO in position 2 in the pixel blend stack.
bits : 24 - 30 (7 bit)
access : read-write
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Threshold Input 2 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_BUF_P3_LO : Low threshold for the FIFO in position 3 in the pixel blend stack.
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-write
INP_BUF_P3_HI : High threshold for the FIFO in position 3 in the pixel blend stack.
bits : 8 - 14 (7 bit)
access : read-write
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
INP_BUF_P4_LO : Low threshold for the FIFO in position 4 in the pixel blend stack.
bits : 16 - 22 (7 bit)
access : read-write
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only
INP_BUF_P4_HI : High threshold for the FIFO in position 4 in the pixel blend stack.
bits : 24 - 30 (7 bit)
access : read-write
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0x9880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0x98F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0x9968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0x99DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0x9A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0x9AC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0x9B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0x9BAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Threshold Input 3 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INP_BUF_P5_LO : Low threshold for the FIFO in position 5 in the pixel blend stack.
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-write
INP_BUF_P5_HI : High threshold for the FIFO in position 5 in the pixel blend stack.
bits : 8 - 14 (7 bit)
access : read-write
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
INP_BUF_P6_LO : Low threshold for the FIFO in position 6 in the pixel blend stack.
bits : 16 - 22 (7 bit)
access : read-write
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only
INP_BUF_P6_HI : High threshold for the FIFO in position 6 in the pixel blend stack.
bits : 24 - 30 (7 bit)
access : read-write
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0x9C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
LUMA Component Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y_BLUE : Luminance coefficient for blue component.
bits : 0 - 9 (10 bit)
access : read-write
RESERVED : no description available
bits : 10 - 10 (1 bit)
access : read-only
Y_GREEN : Luminance coefficient for green component.
bits : 11 - 20 (10 bit)
access : read-write
RESERVED : no description available
bits : 21 - 21 (1 bit)
access : read-only
Y_RED : Luminance coefficient for red component.
bits : 22 - 31 (10 bit)
access : read-write
Control Descriptor Ln_0 Register
address_offset : 0xA180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xA1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xA270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xA2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xA360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xA3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Red Chroma Components Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CB_RED : Cb coefficient for calculation of red component.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
CR_RED : Cr coefficient for calculation of red component.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xA450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xA4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xA540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Green Chroma Components Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CB_GREEN : Cb coefficient for calculation of green component.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
CR_GREEN : Cr coefficient for calculation of green component.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xAAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xAB3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xABB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Blue Chroma Components Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CB_BLUE : Cb coefficient for calculation of blue component.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
CR_BLUE : Cr coefficient for calculation of blue component.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0xAC34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xACB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xAD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xADA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xAE24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xAEA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
CRC Position Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_POS : The result of the CRC calculation for the position of the pixels on the safety layers.
bits : 0 - 31 (32 bit)
access : read-write
Layer Interpolation Enable Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 30 (31 bit)
access : read-only
EN : Interpolation Enable bit for DCU3 Layer coded in YCbCr422 format.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chroma value is same for two pixels
#1 : 1
Interpolation is enabled
End of enumeration elements list.
Control Descriptor Ln_0 Register
address_offset : 0xB440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xB4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xB540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xB5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xB640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xB6C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xB740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xB7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Layer Luminance Component Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y_BLUE : Luminance coefficient for blue component.
bits : 0 - 9 (10 bit)
access : read-write
RESERVED : no description available
bits : 10 - 10 (1 bit)
access : read-only
Y_GREEN : Luminance coefficient for green component.
bits : 11 - 20 (10 bit)
access : read-write
RESERVED : no description available
bits : 21 - 21 (1 bit)
access : read-only
Y_RED : Luminance coefficient for red component.
bits : 22 - 31 (10 bit)
access : read-write
Control Descriptor Ln_0 Register
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xB840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xBBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Layer Chroma Red Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Cb_RED : Cb coefficient for calculation of red component.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
Cr_RED : Cr coefficient for calculation of red component.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xBE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xBE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xBF08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_6 Register
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0xBF8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Cursor 4 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWC_BLINK_ON : HWC blink register. Loads the counter value (number of frames) for which the cursor will remain turned ON.
bits : 0 - 7 (8 bit)
access : read-write
EN_BLINK : Enable the cursor blink mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the blink mode
#1 : 1
Enable the blink mode
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 15 (7 bit)
access : read-only
HWC_BLINK_OFF : HWC blink register. Loads the counter value (number of frames) for which the cursor will remain turned OFF.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Layer Chroma Green Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Cb_GREEN : Cr coefficient for calculation of green component.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
Cr_GREEN : Cr coefficient for calculation of green component.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0xC010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xC094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xC118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xC19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xC220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Layer Chroma Blue Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Cb_BLUE : Cb coefficient for calculation of blue component.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
Cr_BLUE : Cr coefficient for calculation of blue component.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Compression Image Size Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP_IMSIZE : Compressed Image size in bytes for RLE coded layer.
bits : 0 - 21 (22 bit)
access : read-write
RESERVED : no description available
bits : 22 - 31 (10 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xC800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xC888 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xC910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xC998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xCA20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xCAA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xCB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xCBB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Update Mode Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 29 (30 bit)
access : read-only
READREG : When the MODE bit is clear this bit is a control bit which can be written to initiate a transfer of register value during the next vertical blanking period. 1'b1: (MODE=0) Transfer register values on next vertical blanking period.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
(MODE=0) No transfer scheduled. When the MODE bit is set, this bit is a status bit which indicates when a register transfer is underway. (MODE=1) No transfer is underway.
#1 : 1
(MODE=0) Transfer register values on next vertical blanking period. (MODE=1) Register value transfer is underway.
End of enumeration elements list.
MODE : Do not set the MODE bit while the READREG is also set as this will block automatic updates. Do not set the MODE bit and the READREG register in the same write operation.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer of register values during vertical blanking period only when READREG is set
#1 : 1
Automatic transfer of register values during vertical blanking period
End of enumeration elements list.
Control Descriptor Ln_8 Register
address_offset : 0xCC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Underrun Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIXEL : Pixel number where the under run occured.
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
LINE : Line number where the underrun occured.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xD240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xD2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xD358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xD3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xD470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xD4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xD588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xD614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xD6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xDCC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xDD50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xDDE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xDE70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xDF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xDF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xE020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xE0B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xE140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xE780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xE814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xE8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xE93C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_1 Register
address_offset : 0xE98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_4 Register
address_offset : 0xE9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xEA64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xEAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xEB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_7 Register
address_offset : 0xEB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xEC20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0xEC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xEE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xF10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xF280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xF318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xF3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_8 Register
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_3 Register
address_offset : 0xF448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
Control Descriptor Ln_4 Register
address_offset : 0xF4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMAX_B : Chroma Keying Max Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMAX_G : Chroma Keying Max Green Component
bits : 8 - 15 (8 bit)
access : read-write
CKMAX_R : Chroma Keying Max Red Component.
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_5 Register
address_offset : 0xF578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMIN_B : Chroma Keying Minimum Blue Component.
bits : 0 - 7 (8 bit)
access : read-write
CKMIN_G : Chroma Keying Minimum Green Component.
bits : 8 - 15 (8 bit)
access : read-write
CKMIN_R : Chroma Keying Minimum Red Component
bits : 16 - 23 (8 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_6 Register
address_offset : 0xF610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TILE_HOR_SIZE : Width of the TILE (in multiples of 16 pixels).
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-only
TILE_VER_SIZE : Height of the TILE (in pixels).
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_7 Register
address_offset : 0xF6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_FCOLOR : Foreground color to use when the layer is configured to use a transparency mode.
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_8 Register
address_offset : 0xF740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FGn_BCOLOR : Background color to use when the layer is configured to use a transparency mode
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
Control Descriptor Ln_0 Register
address_offset : 0xFDC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of the layer (in pixels).
bits : 0 - 10 (11 bit)
access : read-write
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
HEIGHT : Height of the layer in pixels.
bits : 16 - 26 (11 bit)
access : read-write
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
Control Descriptor Ln_1 Register
address_offset : 0xFE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSX : Two's complement signed value setting the horizontal position of left hand column of the layer, where 0 is the left-hand column of the panel. Positive values are to the right and negative values are to the left the left-hand column of the panel.
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 15 (4 bit)
access : read-only
POSY : Two's complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. Positive values are below and negative values are above the top row of the panel.
bits : 16 - 27 (12 bit)
access : read-write
RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only
Control Descriptor Ln_2 Register
address_offset : 0xFEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address of layer data in the memory. The address programmed should be 64-bit aligned.
bits : 0 - 31 (32 bit)
access : read-write
Control Descriptor Ln_3 Register
address_offset : 0xFF94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AB : Alpha Blending.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No alpha Blending
#01 : 01
Blend only the pixels selected by chroma keying in case BB=1'b1
#10 : 10
Blend the whole frame
#11 : 11
Same functionality as 2'b00
End of enumeration elements list.
BB : Chroma Keying.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
LUOFFS : Look Up Table offset.
bits : 4 - 14 (11 bit)
access : read-write
RLE_EN : Enable RLE mode for layer.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
BPP : Layer encoding format (bit per pixel)
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
1 bpp
#0001 : 0001
2 bpp
#0010 : 0010
4 bpp
#0011 : 0011
8 bpp
#100 : 100
16 bpp (RGB565)
#0101 : 0101
24 bpp
#0110 : 0110
32 bpp (ARGB8888)
#0111 : 0111
Transparency mode 4 bpp
#1000 : 1000
Transparency mode 8bpp
#1001 : 1001
Luminance offset mode 4 bpp
#1010 : 1010
Luminance offset mode 8 bpp
#1011 : 1011
16 bpp (ARGB1555)
#1100 : 1100
16 bpp (ARGB4444)
#1101 : 1101
16 bpp (APAL8 mode)
#1110 : 1110
YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
#1111 : 1111
Reserved
End of enumeration elements list.
TRANS : Transparency Level. Specifies the alpha value for the layer. This value may be used by the blending engine to blend pixels on this layer. Value can vary between 0-255 iwhere 0 is completely transparent adn 255 is completely opaque.
bits : 20 - 27 (8 bit)
access : read-write
SAFETY_EN : Safety Mode Enable Bit. Valid only for layer 0 and layer 1. For registers of all other layers, this should be set to 0.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Safety Mode is disabled
#1 : 1
Safety Mode is enabled for this layer
End of enumeration elements list.
DATA_SEL : Selects the Tile data either from MCU memory or CLUT.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tile Mode data resides in the MCU memory
#1 : 1
Tile mode data resides in the CLUT
End of enumeration elements list.
TILE_EN : Enable the Tile Mode.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
EN : Enable the layer.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
OFF
#1 : 1
ON
End of enumeration elements list.
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