\n

CMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CSR

ISR

MDR

FDR

HFREFR

LFREFR


CSR

CMU Control Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CME RCDIV RESERVED CKSEL1 RESERVED SFM RESERVED

CME : CLKMN1 monitor enable.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CLKMN1 monitor is disabled

#1 : 1

CLKMN1 monitor is enabled

End of enumeration elements list.

RCDIV : CLKMT0_RMN division factor.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

CLKMT0_RMN * 1 (No division)

#01 : 01

CLKMT0_RMN * 2

#10 : 10

CLKMT0_RMN * 4

#11 : 11

CLKMT0_RMN * 8

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

CKSEL1 : Frequency measure clock selection bit.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

CLKMT0_RMN is selected

#01 : 01

Reserved

#10 : 10

Reserved

#11 : 11

CLKMT0_RMN is selected

End of enumeration elements list.

RESERVED : no description available
bits : 10 - 22 (13 bit)
access : read-only

SFM : Start frequency measure.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frequency measurement is completed or not yet started

#1 : 1

Frequency measurement is not completed

End of enumeration elements list.

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


ISR

CMU Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OLRI FLLI FHHI RESERVED RESERVED

OLRI : Oscillator frequency less than f CLKMT0_RMN * 2RCDIVevent status.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No OLR event

#1 : 1

OLR event occurred

End of enumeration elements list.

FLLI : CLKMN1 frequency less than low reference event status.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FLL event

#1 : 1

FLL event occurred

End of enumeration elements list.

FHHI : CLKMN1 frequency higher than high reference event status.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FHH event

#1 : 1

FHH event occurred

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only


MDR

CMU Measurement Duration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDR MDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MD RESERVED

MD : Measurement duration bits
bits : 0 - 19 (20 bit)
access : read-write

RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only


FDR

CMU Frequency Display Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDR FDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FD RESERVED

FD : Measured frequency bits.
bits : 0 - 19 (20 bit)
access : read-only

RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only


HFREFR

CMU High Frequency Reference Register CLKMN1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFREFR HFREFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFREF RESERVED

HFREF : High Frequency reference value.
bits : 0 - 11 (12 bit)
access : read-write

RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only


LFREFR

CMU Low Frequency Reference Register CLKMN1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFREFR LFREFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFREF RESERVED

LFREF : Low Frequency reference value.
bits : 0 - 11 (12 bit)
access : read-write

RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.