\n
address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected
ASRC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASRCEN : no description available
bits : 0 - 0 (1 bit)
access : read-write
ASREA : no description available
bits : 1 - 1 (1 bit)
access : read-write
ASREB : no description available
bits : 2 - 2 (1 bit)
access : read-write
ASREC : no description available
bits : 3 - 3 (1 bit)
access : read-write
SRST : no description available
bits : 4 - 4 (1 bit)
access : write-only
RESERVED : no description available
bits : 5 - 12 (8 bit)
access : read-only
IDRA : no description available
bits : 13 - 13 (1 bit)
access : read-write
USRA : no description available
bits : 14 - 14 (1 bit)
access : read-write
IDRB : no description available
bits : 15 - 15 (1 bit)
access : read-write
USRB : no description available
bits : 16 - 16 (1 bit)
access : read-write
IDRC : no description available
bits : 17 - 17 (1 bit)
access : read-write
USRC : no description available
bits : 18 - 18 (1 bit)
access : read-write
RESERVED : no description available
bits : 19 - 19 (1 bit)
access : read-only
ATSA : no description available
bits : 20 - 20 (1 bit)
access : read-write
ATSB : no description available
bits : 21 - 21 (1 bit)
access : read-write
ATSC : no description available
bits : 22 - 22 (1 bit)
access : read-write
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Filter Configuration Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 5 (6 bit)
access : read-only
PREMODA : no description available
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Select Upsampling-by-2
#01 : 01
Select Direct-Connection
#10 : 10
Select Downsampling-by-2
#11 : 11
Select passthrough mode. In this case, POSTMODA[1-0] have no use.
End of enumeration elements list.
POSTMODA : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Select Upsampling-by-2
#01 : 01
Select Direct-Connection
#10 : 10
Select Downsampling-by-2
End of enumeration elements list.
PREMODB : no description available
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
Select Upsampling-by-2
#01 : 01
Select Direct-Connection
#10 : 10
Select Downsampling-by-2
#11 : 11
Select passthrough mode. In this case, POSTMODB[1-0] have no use.
End of enumeration elements list.
POSTMODB : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
Select Upsampling-by-2
#01 : 01
Select Direct-Connection
#10 : 10
Select Downsampling-by-2
End of enumeration elements list.
PREMODC : no description available
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
Select Upsampling-by-2
#01 : 01
Select Direct-Connection
#10 : 10
Select Downsampling-by-2
#11 : 11
Select passthrough mode. In this case, POSTMODC[1-0] have no use.
End of enumeration elements list.
POSTMODC : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Select Upsampling-by-2 as defined in Signal Processing Flow.
#01 : 01
Select Direct-Connection as defined in Signal Processing Flow.
#10 : 10
Select Downsampling-by-2 as defined in Signal Processing Flow.
End of enumeration elements list.
NDPRA : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
#1 : 1
Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
End of enumeration elements list.
NDPRB : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
#1 : 1
Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
End of enumeration elements list.
NDPRC : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
#1 : 1
Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
End of enumeration elements list.
INIRQA : no description available
bits : 21 - 21 (1 bit)
access : read-only
INIRQB : no description available
bits : 22 - 22 (1 bit)
access : read-only
INIRQC : no description available
bits : 23 - 23 (1 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Parameter Register n
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Data Input Register for Pair x
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 23 (24 bit)
access : write-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Data Output Register for Pair x
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 23 (24 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Clock Source Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AICSA : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
bit clock 0
#0001 : 0001
bit clock 1
#0010 : 0010
bit clock 2
#0011 : 0011
bit clock 3
#0100 : 0100
bit clock 4
#0101 : 0101
bit clock 5
#0110 : 0110
bit clock 6
#0111 : 0111
bit clock 7
#1000 : 1000
bit clock 8
#1001 : 1001
bit clock 9
#1010 : 1010
bit clock A
#1011 : 1011
bit clock B
#1100 : 1100
bit clock C
#1101 : 1101
bit clock D
#1111 : 1111
clock disabled, connected to zero
End of enumeration elements list.
AICSB : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
bit clock 0
#0001 : 0001
bit clock 1
#0010 : 0010
bit clock 2
#0011 : 0011
bit clock 3
#0100 : 0100
bit clock 4
#0101 : 0101
bit clock 5
#0110 : 0110
bit clock 6
#0111 : 0111
bit clock 7
#1000 : 1000
bit clock 8
#1001 : 1001
bit clock 9
#1010 : 1010
bit clock A
#1011 : 1011
bit clock B
#1100 : 1100
bit clock C
#1101 : 1101
bit clock D
#1111 : 1111
clock disabled, connected to zero
End of enumeration elements list.
AICSC : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
bit clock 0
#0001 : 0001
bit clock 1
#0010 : 0010
bit clock 2
#0011 : 0011
bit clock 3
#0100 : 0100
bit clock 4
#0101 : 0101
bit clock 5
#0110 : 0110
bit clock 6
#0111 : 0111
bit clock 7
#1000 : 1000
bit clock 8
#1001 : 1001
bit clock 9
#1010 : 1010
bit clock A
#1011 : 1011
bit clock B
#1100 : 1100
bit clock C
#1101 : 1101
bit clock D
#1111 : 1111
clock disabled, connected to zero
End of enumeration elements list.
AOCSA : no description available
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
bit clock 0
#0001 : 0001
bit clock 1
#0010 : 0010
bit clock 2
#0011 : 0011
bit clock 3
#0100 : 0100
bit clock 4
#0101 : 0101
bit clock 5
#0110 : 0110
bit clock 6
#0111 : 0111
bit clock 7
#1000 : 1000
bit clock 8
#1001 : 1001
bit clock 9
#1010 : 1010
bit clock A
#1011 : 1011
bit clock B
#1100 : 1100
bit clock C
#1101 : 1101
bit clock D
#1111 : 1111
clock disabled, connected to zero
End of enumeration elements list.
AOCSB : no description available
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
bit clock 0
#0001 : 0001
bit clock 1
#0010 : 0010
bit clock 2
#0011 : 0011
bit clock 3
#0100 : 0100
bit clock 4
#0101 : 0101
bit clock 5
#0110 : 0110
bit clock 6
#0111 : 0111
bit clock 7
#1000 : 1000
bit clock 8
#1001 : 1001
bit clock 9
#1010 : 1010
bit clock A
#1011 : 1011
bit clock B
#1100 : 1100
bit clock C
#1101 : 1101
bit clock D
#1111 : 1111
clock disabled, connected to zero
End of enumeration elements list.
AOCSC : no description available
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
bit clock 0
#0001 : 0001
bit clock 1
#0010 : 0010
bit clock 2
#0011 : 0011
bit clock 3
#0100 : 0100
bit clock 4
#0101 : 0101
bit clock 5
#0110 : 0110
bit clock 6
#0111 : 0111
bit clock 7
#1000 : 1000
bit clock 8
#1001 : 1001
bit clock 9
#1010 : 1010
bit clock A
#1011 : 1011
bit clock B
#1100 : 1100
bit clock C
#1101 : 1101
bit clock D
#1111 : 1111
clock disabled, connected to zero
End of enumeration elements list.
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Parameter Register n
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Clock Divider Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AICPA : no description available
bits : 0 - 2 (3 bit)
access : read-write
AICDA : no description available
bits : 3 - 5 (3 bit)
access : read-write
AICPB : no description available
bits : 6 - 8 (3 bit)
access : read-write
AICDB : no description available
bits : 9 - 11 (3 bit)
access : read-write
AOCPA : no description available
bits : 12 - 14 (3 bit)
access : read-write
AOCDA : no description available
bits : 15 - 17 (3 bit)
access : read-write
AOCPB : no description available
bits : 18 - 20 (3 bit)
access : read-write
AOCDB : no description available
bits : 21 - 23 (3 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Misc Control Register 1 for Pair X
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OW16 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
16-bit output data
#0 : 0
24-bit output data.
End of enumeration elements list.
OSGN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
Sign extension.
#0 : 0
No sign extension.
End of enumeration elements list.
OMSB : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#1 : 1
MSB aligned.
#0 : 0
LSB aligned.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only
IMSB : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#1 : 1
MSB aligned.
#0 : 0
LSB aligned.
End of enumeration elements list.
IWD : no description available
bits : 9 - 11 (3 bit)
access : read-write
RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Data Input Register for Pair x
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 23 (24 bit)
access : write-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Parameter Register n
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Data Output Register for Pair x
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 23 (24 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Clock Divider Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AICPC : no description available
bits : 0 - 2 (3 bit)
access : read-write
AICDC : no description available
bits : 3 - 5 (3 bit)
access : read-write
AOCPC : no description available
bits : 6 - 8 (3 bit)
access : read-write
AOCDC : no description available
bits : 9 - 11 (3 bit)
access : read-write
RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AIDEA : no description available
bits : 0 - 0 (1 bit)
access : read-only
AIDEB : no description available
bits : 1 - 1 (1 bit)
access : read-only
AIDEC : no description available
bits : 2 - 2 (1 bit)
access : read-only
AODFA : no description available
bits : 3 - 3 (1 bit)
access : read-only
AODFB : no description available
bits : 4 - 4 (1 bit)
access : read-only
AODFC : no description available
bits : 5 - 5 (1 bit)
access : read-only
AOLE : no description available
bits : 6 - 6 (1 bit)
access : read-only
FPWT : no description available
bits : 7 - 7 (1 bit)
access : read-only
AIDUA : no description available
bits : 8 - 8 (1 bit)
access : read-only
AIDUB : no description available
bits : 9 - 9 (1 bit)
access : read-only
AIDUC : no description available
bits : 10 - 10 (1 bit)
access : read-only
AODOA : no description available
bits : 11 - 11 (1 bit)
access : read-only
AODOB : no description available
bits : 12 - 12 (1 bit)
access : read-only
AODOC : no description available
bits : 13 - 13 (1 bit)
access : read-only
AIOLA : no description available
bits : 14 - 14 (1 bit)
access : read-only
AIOLB : no description available
bits : 15 - 15 (1 bit)
access : read-only
AIOLC : no description available
bits : 16 - 16 (1 bit)
access : read-only
AOOLA : no description available
bits : 17 - 17 (1 bit)
access : read-only
AOOLB : no description available
bits : 18 - 18 (1 bit)
access : read-only
AOOLC : no description available
bits : 19 - 19 (1 bit)
access : read-only
ATQOL : no description available
bits : 20 - 20 (1 bit)
access : read-only
DSLCNT : no description available
bits : 21 - 21 (1 bit)
access : read-only
RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Misc Control Register 1 for Pair X
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OW16 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
16-bit output data
#0 : 0
24-bit output data.
End of enumeration elements list.
OSGN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
Sign extension.
#0 : 0
No sign extension.
End of enumeration elements list.
OMSB : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#1 : 1
MSB aligned.
#0 : 0
LSB aligned.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only
IMSB : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#1 : 1
MSB aligned.
#0 : 0
LSB aligned.
End of enumeration elements list.
IWD : no description available
bits : 9 - 11 (3 bit)
access : read-write
RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Misc Control Register 1 for Pair X
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OW16 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
16-bit output data
#0 : 0
24-bit output data.
End of enumeration elements list.
OSGN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
Sign extension.
#0 : 0
No sign extension.
End of enumeration elements list.
OMSB : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#1 : 1
MSB aligned.
#0 : 0
LSB aligned.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only
IMSB : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#1 : 1
MSB aligned.
#0 : 0
LSB aligned.
End of enumeration elements list.
IWD : no description available
bits : 9 - 11 (3 bit)
access : read-write
RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADIEA : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
ADIEB : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
ADIEC : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
ADOEA : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
ADOEB : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
ADOEC : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
AOLIE : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
AFPWE : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#1 : 1
interrupt enabled
#0 : 0
interrupt disabled
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC ASRC Task Queue FIFO Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 5 (6 bit)
access : read-only
TF_BASE : no description available
bits : 6 - 12 (7 bit)
access : read-write
TF_FILL : no description available
bits : 13 - 19 (7 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Channel Counter Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACIA : no description available
bits : 0 - 3 (4 bit)
access : read-write
ACIB : no description available
bits : 4 - 7 (4 bit)
access : read-write
ACIC : no description available
bits : 8 - 11 (4 bit)
access : read-write
ACOA : no description available
bits : 12 - 15 (4 bit)
access : read-write
ACOB : no description available
bits : 16 - 19 (4 bit)
access : read-write
ACOC : no description available
bits : 20 - 23 (4 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Parameter Register n
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Ideal Ratio for Pair A-High Part
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDRATIOA : no description available
bits : 0 - 7 (8 bit)
access : read-write
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Ideal Ratio for Pair A -Low Part
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDRATIOA : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Ideal Ratio for Pair B-High Part
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDRATIOB : no description available
bits : 0 - 7 (8 bit)
access : read-write
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Ideal Ratio for Pair B-Low Part
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDRATIOB : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Ideal Ratio for Pair C-High Part
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDRATIOC : no description available
bits : 0 - 7 (8 bit)
access : read-write
RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Ideal Ratio for Pair C-Low Part
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDRATIOC : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC 76kHz Period in terms of ASRC processing clock
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASR76K : no description available
bits : 0 - 16 (17 bit)
access : read-write
RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC 56kHz Period in terms of ASRC processing clock
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASR56K : no description available
bits : 0 - 16 (17 bit)
access : read-write
RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Misc Control Register for Pair A
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFIFO_THRESHOLDA : no description available
bits : 0 - 5 (6 bit)
access : read-write
RESERVED : no description available
bits : 6 - 9 (4 bit)
access : read-only
RSYNOFA : no description available
bits : 10 - 10 (1 bit)
access : read-write
RSYNIFA : no description available
bits : 11 - 11 (1 bit)
access : read-write
OUTFIFO_THRESHOLDA : no description available
bits : 12 - 17 (6 bit)
access : read-write
RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only
BYPASSPOLYA : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#1 : 1
Bypass polyphase filtering.
#0 : 0
Don't bypass polyphase filtering.
End of enumeration elements list.
BUFSTALLA : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#1 : 1
Stall Pair A conversion in case of near empty/full FIFO conditions.
#0 : 0
Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
End of enumeration elements list.
EXTTHRSHA : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#1 : 1
Use external defined thresholds.
#0 : 0
Use default thresholds.
End of enumeration elements list.
ZEROBUFA : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
Don't zeroize the buffer
#0 : 0
Zeroize the buffer
End of enumeration elements list.
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC FIFO Status Register for Pair A
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INFIFO_FILLA : no description available
bits : 0 - 6 (7 bit)
access : read-only
RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only
IAEA : no description available
bits : 11 - 11 (1 bit)
access : read-only
OUTFIFO_FILLA : no description available
bits : 12 - 18 (7 bit)
access : read-only
RESERVED : no description available
bits : 19 - 22 (4 bit)
access : read-only
OAFA : no description available
bits : 23 - 23 (1 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Misc Control Register for Pair B
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFIFO_THRESHOLDB : no description available
bits : 0 - 5 (6 bit)
access : read-write
RESERVED : no description available
bits : 6 - 9 (4 bit)
access : read-only
RSYNOFB : no description available
bits : 10 - 10 (1 bit)
access : read-write
RSYNIFB : no description available
bits : 11 - 11 (1 bit)
access : read-write
OUTFIFO_THRESHOLDB : no description available
bits : 12 - 17 (6 bit)
access : read-write
RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only
BYPASSPOLYB : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#1 : 1
Bypass polyphase filtering.
#0 : 0
Don't bypass polyphase filtering.
End of enumeration elements list.
BUFSTALLB : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#1 : 1
Stall Pair B conversion in case of near empty/full FIFO conditions.
#0 : 0
Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
End of enumeration elements list.
EXTTHRSHB : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#1 : 1
Use external defined thresholds.
#0 : 0
Use default thresholds.
End of enumeration elements list.
ZEROBUFB : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
Don't zeroize the buffer
#0 : 0
Zeroize the buffer
End of enumeration elements list.
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC FIFO Status Register for Pair B
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INFIFO_FILLB : no description available
bits : 0 - 6 (7 bit)
access : read-only
RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only
IAEB : no description available
bits : 11 - 11 (1 bit)
access : read-only
OUTFIFO_FILLB : no description available
bits : 12 - 18 (7 bit)
access : read-only
RESERVED : no description available
bits : 19 - 22 (4 bit)
access : read-only
OAFB : no description available
bits : 23 - 23 (1 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Misc Control Register for Pair C
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFIFO_THRESHOLDC : no description available
bits : 0 - 5 (6 bit)
access : read-write
RESERVED : no description available
bits : 6 - 9 (4 bit)
access : read-only
RSYNOFC : no description available
bits : 10 - 10 (1 bit)
access : read-write
RSYNIFC : no description available
bits : 11 - 11 (1 bit)
access : read-write
OUTFIFO_THRESHOLDC : no description available
bits : 12 - 17 (6 bit)
access : read-write
RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only
BYPASSPOLYC : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#1 : 1
Bypass polyphase filtering.
#0 : 0
Don't bypass polyphase filtering.
End of enumeration elements list.
BUFSTALLC : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#1 : 1
Stall Pair C conversion in case of near empty/full FIFO conditions.
#0 : 0
Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
End of enumeration elements list.
EXTTHRSHC : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#1 : 1
Use external defined thresholds.
#0 : 0
Use default thresholds.
End of enumeration elements list.
ZEROBUFC : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
Don't zeroize the buffer
#0 : 0
Zeroize the buffer
End of enumeration elements list.
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC FIFO Status Register for Pair C
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INFIFO_FILLC : no description available
bits : 0 - 6 (7 bit)
access : read-only
RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only
IAEC : no description available
bits : 11 - 11 (1 bit)
access : read-only
OUTFIFO_FILLC : no description available
bits : 12 - 18 (7 bit)
access : read-only
RESERVED : no description available
bits : 19 - 22 (4 bit)
access : read-only
OAFC : no description available
bits : 23 - 23 (1 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Channel Number Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ANCA : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 channels in A (Pair A is disabled)
#0001 : 0001
1 channel in A
#0010 : 0010
2 channels in A
#0011 : 0011
3 channels in A
#0100 : 0100
4 channels in A
#0101 : 0101
5 channels in A
#0110 : 0110
6 channels in A
#0111 : 0111
7 channels in A
#1000 : 1000
8 channels in A
#1001 : 1001
9 channels in A
#1010 : 1010
10 channels in A
End of enumeration elements list.
ANCB : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 channels in B (Pair B is disabled)
#0001 : 0001
1 channel in B
#0010 : 0010
2 channels in B
#0011 : 0011
3 channels in B
#0100 : 0100
4 channels in B
#0101 : 0101
5 channels in B
#0110 : 0110
6 channels in B
#0111 : 0111
7 channels in B
#1000 : 1000
8 channels in B
#1001 : 1001
9 channels in B
#1010 : 1010
10 channels in B
End of enumeration elements list.
ANCC : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
0 channels in C (Pair C is disabled)
#0001 : 0001
1 channel in C
#0010 : 0010
2 channels in C
#0011 : 0011
3 channels in C
#0100 : 0100
4 channels in C
#0101 : 0101
5 channels in C
#0110 : 0110
6 channels in C
#0111 : 0111
7 channels in C
#1000 : 1000
8 channels in C
#1001 : 1001
9 channels in C
#1010 : 1010
10 channels in C
End of enumeration elements list.
RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Data Input Register for Pair x
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 23 (24 bit)
access : write-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Parameter Register n
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
ASRC Data Output Register for Pair x
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 23 (24 bit)
access : read-only
RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only
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