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ASRC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected

Registers

ASRCTR

ASRCFG

ASRPMn3

ASRDIB

ASRDOB

ASRCSR

ASRPMn4

ASRCDR1

ASRMCR1A

ASRDIC

ASRPMn5

ASRDOC

ASRCDR2

ASRSTR

ASRMCR1B

ASRMCR1C

ASRIER

ASRTFR1

ASRCCR

ASRPMn1

ASRIDRHA

ASRIDRLA

ASRIDRHB

ASRIDRLB

ASRIDRHC

ASRIDRLC

ASR76K

ASR56K

ASRMCRA

ASRFSTA

ASRMCRB

ASRFSTB

ASRMCRC

ASRFSTC

ASRCNCR

ASRDIA

ASRPMn2

ASRDOA


ASRCTR

ASRC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCTR ASRCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASRCEN ASREA ASREB ASREC SRST RESERVED IDRA USRA IDRB USRB IDRC USRC RESERVED ATSA ATSB ATSC RESERVED RESERVED

ASRCEN : no description available
bits : 0 - 0 (1 bit)
access : read-write

ASREA : no description available
bits : 1 - 1 (1 bit)
access : read-write

ASREB : no description available
bits : 2 - 2 (1 bit)
access : read-write

ASREC : no description available
bits : 3 - 3 (1 bit)
access : read-write

SRST : no description available
bits : 4 - 4 (1 bit)
access : write-only

RESERVED : no description available
bits : 5 - 12 (8 bit)
access : read-only

IDRA : no description available
bits : 13 - 13 (1 bit)
access : read-write

USRA : no description available
bits : 14 - 14 (1 bit)
access : read-write

IDRB : no description available
bits : 15 - 15 (1 bit)
access : read-write

USRB : no description available
bits : 16 - 16 (1 bit)
access : read-write

IDRC : no description available
bits : 17 - 17 (1 bit)
access : read-write

USRC : no description available
bits : 18 - 18 (1 bit)
access : read-write

RESERVED : no description available
bits : 19 - 19 (1 bit)
access : read-only

ATSA : no description available
bits : 20 - 20 (1 bit)
access : read-write

ATSB : no description available
bits : 21 - 21 (1 bit)
access : read-write

ATSC : no description available
bits : 22 - 22 (1 bit)
access : read-write

RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRCFG

ASRC Filter Configuration Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCFG ASRCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED PREMODA POSTMODA PREMODB POSTMODB PREMODC POSTMODC NDPRA NDPRB NDPRC INIRQA INIRQB INIRQC RESERVED

RESERVED : no description available
bits : 0 - 5 (6 bit)
access : read-only

PREMODA : no description available
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

Select Upsampling-by-2

#01 : 01

Select Direct-Connection

#10 : 10

Select Downsampling-by-2

#11 : 11

Select passthrough mode. In this case, POSTMODA[1-0] have no use.

End of enumeration elements list.

POSTMODA : no description available
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 00

Select Upsampling-by-2

#01 : 01

Select Direct-Connection

#10 : 10

Select Downsampling-by-2

End of enumeration elements list.

PREMODB : no description available
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

Select Upsampling-by-2

#01 : 01

Select Direct-Connection

#10 : 10

Select Downsampling-by-2

#11 : 11

Select passthrough mode. In this case, POSTMODB[1-0] have no use.

End of enumeration elements list.

POSTMODB : no description available
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

Select Upsampling-by-2

#01 : 01

Select Direct-Connection

#10 : 10

Select Downsampling-by-2

End of enumeration elements list.

PREMODC : no description available
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 00

Select Upsampling-by-2

#01 : 01

Select Direct-Connection

#10 : 10

Select Downsampling-by-2

#11 : 11

Select passthrough mode. In this case, POSTMODC[1-0] have no use.

End of enumeration elements list.

POSTMODC : no description available
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Select Upsampling-by-2 as defined in Signal Processing Flow.

#01 : 01

Select Direct-Connection as defined in Signal Processing Flow.

#10 : 10

Select Downsampling-by-2 as defined in Signal Processing Flow.

End of enumeration elements list.

NDPRA : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use default parameters for RAM-stored parameters. Override any parameters already in RAM.

#1 : 1

Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.

End of enumeration elements list.

NDPRB : no description available
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use default parameters for RAM-stored parameters. Override any parameters already in RAM.

#1 : 1

Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.

End of enumeration elements list.

NDPRC : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Use default parameters for RAM-stored parameters. Override any parameters already in RAM.

#1 : 1

Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.

End of enumeration elements list.

INIRQA : no description available
bits : 21 - 21 (1 bit)
access : read-only

INIRQB : no description available
bits : 22 - 22 (1 bit)
access : read-only

INIRQC : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRPMn3

ASRC Parameter Register n
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRPMn3 ASRPMn3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMETER_VALUE RESERVED

PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRDIB

ASRC Data Input Register for Pair x
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRDIB ASRDIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA RESERVED

DATA : no description available
bits : 0 - 23 (24 bit)
access : write-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRDOB

ASRC Data Output Register for Pair x
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRDOB ASRDOB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA RESERVED

DATA : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRCSR

ASRC Clock Source Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCSR ASRCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AICSA AICSB AICSC AOCSA AOCSB AOCSC RESERVED

AICSA : no description available
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

bit clock 0

#0001 : 0001

bit clock 1

#0010 : 0010

bit clock 2

#0011 : 0011

bit clock 3

#0100 : 0100

bit clock 4

#0101 : 0101

bit clock 5

#0110 : 0110

bit clock 6

#0111 : 0111

bit clock 7

#1000 : 1000

bit clock 8

#1001 : 1001

bit clock 9

#1010 : 1010

bit clock A

#1011 : 1011

bit clock B

#1100 : 1100

bit clock C

#1101 : 1101

bit clock D

#1111 : 1111

clock disabled, connected to zero

End of enumeration elements list.

AICSB : no description available
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

bit clock 0

#0001 : 0001

bit clock 1

#0010 : 0010

bit clock 2

#0011 : 0011

bit clock 3

#0100 : 0100

bit clock 4

#0101 : 0101

bit clock 5

#0110 : 0110

bit clock 6

#0111 : 0111

bit clock 7

#1000 : 1000

bit clock 8

#1001 : 1001

bit clock 9

#1010 : 1010

bit clock A

#1011 : 1011

bit clock B

#1100 : 1100

bit clock C

#1101 : 1101

bit clock D

#1111 : 1111

clock disabled, connected to zero

End of enumeration elements list.

AICSC : no description available
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

bit clock 0

#0001 : 0001

bit clock 1

#0010 : 0010

bit clock 2

#0011 : 0011

bit clock 3

#0100 : 0100

bit clock 4

#0101 : 0101

bit clock 5

#0110 : 0110

bit clock 6

#0111 : 0111

bit clock 7

#1000 : 1000

bit clock 8

#1001 : 1001

bit clock 9

#1010 : 1010

bit clock A

#1011 : 1011

bit clock B

#1100 : 1100

bit clock C

#1101 : 1101

bit clock D

#1111 : 1111

clock disabled, connected to zero

End of enumeration elements list.

AOCSA : no description available
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

bit clock 0

#0001 : 0001

bit clock 1

#0010 : 0010

bit clock 2

#0011 : 0011

bit clock 3

#0100 : 0100

bit clock 4

#0101 : 0101

bit clock 5

#0110 : 0110

bit clock 6

#0111 : 0111

bit clock 7

#1000 : 1000

bit clock 8

#1001 : 1001

bit clock 9

#1010 : 1010

bit clock A

#1011 : 1011

bit clock B

#1100 : 1100

bit clock C

#1101 : 1101

bit clock D

#1111 : 1111

clock disabled, connected to zero

End of enumeration elements list.

AOCSB : no description available
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

bit clock 0

#0001 : 0001

bit clock 1

#0010 : 0010

bit clock 2

#0011 : 0011

bit clock 3

#0100 : 0100

bit clock 4

#0101 : 0101

bit clock 5

#0110 : 0110

bit clock 6

#0111 : 0111

bit clock 7

#1000 : 1000

bit clock 8

#1001 : 1001

bit clock 9

#1010 : 1010

bit clock A

#1011 : 1011

bit clock B

#1100 : 1100

bit clock C

#1101 : 1101

bit clock D

#1111 : 1111

clock disabled, connected to zero

End of enumeration elements list.

AOCSC : no description available
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

bit clock 0

#0001 : 0001

bit clock 1

#0010 : 0010

bit clock 2

#0011 : 0011

bit clock 3

#0100 : 0100

bit clock 4

#0101 : 0101

bit clock 5

#0110 : 0110

bit clock 6

#0111 : 0111

bit clock 7

#1000 : 1000

bit clock 8

#1001 : 1001

bit clock 9

#1010 : 1010

bit clock A

#1011 : 1011

bit clock B

#1100 : 1100

bit clock C

#1101 : 1101

bit clock D

#1111 : 1111

clock disabled, connected to zero

End of enumeration elements list.

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRPMn4

ASRC Parameter Register n
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRPMn4 ASRPMn4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMETER_VALUE RESERVED

PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRCDR1

ASRC Clock Divider Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCDR1 ASRCDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AICPA AICDA AICPB AICDB AOCPA AOCDA AOCPB AOCDB RESERVED

AICPA : no description available
bits : 0 - 2 (3 bit)
access : read-write

AICDA : no description available
bits : 3 - 5 (3 bit)
access : read-write

AICPB : no description available
bits : 6 - 8 (3 bit)
access : read-write

AICDB : no description available
bits : 9 - 11 (3 bit)
access : read-write

AOCPA : no description available
bits : 12 - 14 (3 bit)
access : read-write

AOCDA : no description available
bits : 15 - 17 (3 bit)
access : read-write

AOCPB : no description available
bits : 18 - 20 (3 bit)
access : read-write

AOCDB : no description available
bits : 21 - 23 (3 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRMCR1A

ASRC Misc Control Register 1 for Pair X
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRMCR1A ASRMCR1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OW16 OSGN OMSB RESERVED IMSB IWD RESERVED RESERVED

OW16 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

16-bit output data

#0 : 0

24-bit output data.

End of enumeration elements list.

OSGN : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#1 : 1

Sign extension.

#0 : 0

No sign extension.

End of enumeration elements list.

OMSB : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#1 : 1

MSB aligned.

#0 : 0

LSB aligned.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

IMSB : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#1 : 1

MSB aligned.

#0 : 0

LSB aligned.

End of enumeration elements list.

IWD : no description available
bits : 9 - 11 (3 bit)
access : read-write

RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRDIC

ASRC Data Input Register for Pair x
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRDIC ASRDIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA RESERVED

DATA : no description available
bits : 0 - 23 (24 bit)
access : write-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRPMn5

ASRC Parameter Register n
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRPMn5 ASRPMn5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMETER_VALUE RESERVED

PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRDOC

ASRC Data Output Register for Pair x
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRDOC ASRDOC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA RESERVED

DATA : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRCDR2

ASRC Clock Divider Register 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCDR2 ASRCDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AICPC AICDC AOCPC AOCDC RESERVED RESERVED

AICPC : no description available
bits : 0 - 2 (3 bit)
access : read-write

AICDC : no description available
bits : 3 - 5 (3 bit)
access : read-write

AOCPC : no description available
bits : 6 - 8 (3 bit)
access : read-write

AOCDC : no description available
bits : 9 - 11 (3 bit)
access : read-write

RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRSTR

ASRC Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRSTR ASRSTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIDEA AIDEB AIDEC AODFA AODFB AODFC AOLE FPWT AIDUA AIDUB AIDUC AODOA AODOB AODOC AIOLA AIOLB AIOLC AOOLA AOOLB AOOLC ATQOL DSLCNT RESERVED RESERVED

AIDEA : no description available
bits : 0 - 0 (1 bit)
access : read-only

AIDEB : no description available
bits : 1 - 1 (1 bit)
access : read-only

AIDEC : no description available
bits : 2 - 2 (1 bit)
access : read-only

AODFA : no description available
bits : 3 - 3 (1 bit)
access : read-only

AODFB : no description available
bits : 4 - 4 (1 bit)
access : read-only

AODFC : no description available
bits : 5 - 5 (1 bit)
access : read-only

AOLE : no description available
bits : 6 - 6 (1 bit)
access : read-only

FPWT : no description available
bits : 7 - 7 (1 bit)
access : read-only

AIDUA : no description available
bits : 8 - 8 (1 bit)
access : read-only

AIDUB : no description available
bits : 9 - 9 (1 bit)
access : read-only

AIDUC : no description available
bits : 10 - 10 (1 bit)
access : read-only

AODOA : no description available
bits : 11 - 11 (1 bit)
access : read-only

AODOB : no description available
bits : 12 - 12 (1 bit)
access : read-only

AODOC : no description available
bits : 13 - 13 (1 bit)
access : read-only

AIOLA : no description available
bits : 14 - 14 (1 bit)
access : read-only

AIOLB : no description available
bits : 15 - 15 (1 bit)
access : read-only

AIOLC : no description available
bits : 16 - 16 (1 bit)
access : read-only

AOOLA : no description available
bits : 17 - 17 (1 bit)
access : read-only

AOOLB : no description available
bits : 18 - 18 (1 bit)
access : read-only

AOOLC : no description available
bits : 19 - 19 (1 bit)
access : read-only

ATQOL : no description available
bits : 20 - 20 (1 bit)
access : read-only

DSLCNT : no description available
bits : 21 - 21 (1 bit)
access : read-only

RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRMCR1B

ASRC Misc Control Register 1 for Pair X
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRMCR1B ASRMCR1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OW16 OSGN OMSB RESERVED IMSB IWD RESERVED RESERVED

OW16 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

16-bit output data

#0 : 0

24-bit output data.

End of enumeration elements list.

OSGN : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#1 : 1

Sign extension.

#0 : 0

No sign extension.

End of enumeration elements list.

OMSB : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#1 : 1

MSB aligned.

#0 : 0

LSB aligned.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

IMSB : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#1 : 1

MSB aligned.

#0 : 0

LSB aligned.

End of enumeration elements list.

IWD : no description available
bits : 9 - 11 (3 bit)
access : read-write

RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRMCR1C

ASRC Misc Control Register 1 for Pair X
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRMCR1C ASRMCR1C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OW16 OSGN OMSB RESERVED IMSB IWD RESERVED RESERVED

OW16 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

16-bit output data

#0 : 0

24-bit output data.

End of enumeration elements list.

OSGN : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#1 : 1

Sign extension.

#0 : 0

No sign extension.

End of enumeration elements list.

OMSB : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#1 : 1

MSB aligned.

#0 : 0

LSB aligned.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

IMSB : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#1 : 1

MSB aligned.

#0 : 0

LSB aligned.

End of enumeration elements list.

IWD : no description available
bits : 9 - 11 (3 bit)
access : read-write

RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIER

ASRC Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIER ASRIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADIEA ADIEB ADIEC ADOEA ADOEB ADOEC AOLIE AFPWE RESERVED RESERVED

ADIEA : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

ADIEB : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

ADIEC : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

ADOEA : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

ADOEB : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

ADOEC : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

AOLIE : no description available
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

AFPWE : no description available
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#1 : 1

interrupt enabled

#0 : 0

interrupt disabled

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRTFR1

ASRC ASRC Task Queue FIFO Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRTFR1 ASRTFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED TF_BASE TF_FILL RESERVED RESERVED

RESERVED : no description available
bits : 0 - 5 (6 bit)
access : read-only

TF_BASE : no description available
bits : 6 - 12 (7 bit)
access : read-write

TF_FILL : no description available
bits : 13 - 19 (7 bit)
access : read-only

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRCCR

ASRC Channel Counter Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCCR ASRCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACIA ACIB ACIC ACOA ACOB ACOC RESERVED

ACIA : no description available
bits : 0 - 3 (4 bit)
access : read-write

ACIB : no description available
bits : 4 - 7 (4 bit)
access : read-write

ACIC : no description available
bits : 8 - 11 (4 bit)
access : read-write

ACOA : no description available
bits : 12 - 15 (4 bit)
access : read-write

ACOB : no description available
bits : 16 - 19 (4 bit)
access : read-write

ACOC : no description available
bits : 20 - 23 (4 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRPMn1

ASRC Parameter Register n
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRPMn1 ASRPMn1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMETER_VALUE RESERVED

PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIDRHA

ASRC Ideal Ratio for Pair A-High Part
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIDRHA ASRIDRHA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDRATIOA RESERVED RESERVED

IDRATIOA : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIDRLA

ASRC Ideal Ratio for Pair A -Low Part
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIDRLA ASRIDRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDRATIOA RESERVED

IDRATIOA : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIDRHB

ASRC Ideal Ratio for Pair B-High Part
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIDRHB ASRIDRHB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDRATIOB RESERVED RESERVED

IDRATIOB : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIDRLB

ASRC Ideal Ratio for Pair B-Low Part
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIDRLB ASRIDRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDRATIOB RESERVED

IDRATIOB : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIDRHC

ASRC Ideal Ratio for Pair C-High Part
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIDRHC ASRIDRHC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDRATIOC RESERVED RESERVED

IDRATIOC : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRIDRLC

ASRC Ideal Ratio for Pair C-Low Part
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRIDRLC ASRIDRLC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDRATIOC RESERVED

IDRATIOC : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASR76K

ASRC 76kHz Period in terms of ASRC processing clock
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASR76K ASR76K read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASR76K RESERVED RESERVED

ASR76K : no description available
bits : 0 - 16 (17 bit)
access : read-write

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASR56K

ASRC 56kHz Period in terms of ASRC processing clock
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASR56K ASR56K read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASR56K RESERVED RESERVED

ASR56K : no description available
bits : 0 - 16 (17 bit)
access : read-write

RESERVED : no description available
bits : 17 - 23 (7 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRMCRA

ASRC Misc Control Register for Pair A
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRMCRA ASRMCRA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFIFO_THRESHOLDA RESERVED RSYNOFA RSYNIFA OUTFIFO_THRESHOLDA RESERVED BYPASSPOLYA BUFSTALLA EXTTHRSHA ZEROBUFA RESERVED

INFIFO_THRESHOLDA : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 9 (4 bit)
access : read-only

RSYNOFA : no description available
bits : 10 - 10 (1 bit)
access : read-write

RSYNIFA : no description available
bits : 11 - 11 (1 bit)
access : read-write

OUTFIFO_THRESHOLDA : no description available
bits : 12 - 17 (6 bit)
access : read-write

RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only

BYPASSPOLYA : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#1 : 1

Bypass polyphase filtering.

#0 : 0

Don't bypass polyphase filtering.

End of enumeration elements list.

BUFSTALLA : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#1 : 1

Stall Pair A conversion in case of near empty/full FIFO conditions.

#0 : 0

Don't stall Pair A conversion even in case of near empty/full FIFO conditions.

End of enumeration elements list.

EXTTHRSHA : no description available
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#1 : 1

Use external defined thresholds.

#0 : 0

Use default thresholds.

End of enumeration elements list.

ZEROBUFA : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

Don't zeroize the buffer

#0 : 0

Zeroize the buffer

End of enumeration elements list.

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRFSTA

ASRC FIFO Status Register for Pair A
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRFSTA ASRFSTA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFIFO_FILLA RESERVED IAEA OUTFIFO_FILLA RESERVED OAFA RESERVED

INFIFO_FILLA : no description available
bits : 0 - 6 (7 bit)
access : read-only

RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only

IAEA : no description available
bits : 11 - 11 (1 bit)
access : read-only

OUTFIFO_FILLA : no description available
bits : 12 - 18 (7 bit)
access : read-only

RESERVED : no description available
bits : 19 - 22 (4 bit)
access : read-only

OAFA : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRMCRB

ASRC Misc Control Register for Pair B
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRMCRB ASRMCRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFIFO_THRESHOLDB RESERVED RSYNOFB RSYNIFB OUTFIFO_THRESHOLDB RESERVED BYPASSPOLYB BUFSTALLB EXTTHRSHB ZEROBUFB RESERVED

INFIFO_THRESHOLDB : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 9 (4 bit)
access : read-only

RSYNOFB : no description available
bits : 10 - 10 (1 bit)
access : read-write

RSYNIFB : no description available
bits : 11 - 11 (1 bit)
access : read-write

OUTFIFO_THRESHOLDB : no description available
bits : 12 - 17 (6 bit)
access : read-write

RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only

BYPASSPOLYB : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#1 : 1

Bypass polyphase filtering.

#0 : 0

Don't bypass polyphase filtering.

End of enumeration elements list.

BUFSTALLB : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#1 : 1

Stall Pair B conversion in case of near empty/full FIFO conditions.

#0 : 0

Don't stall Pair B conversion even in case of near empty/full FIFO conditions.

End of enumeration elements list.

EXTTHRSHB : no description available
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#1 : 1

Use external defined thresholds.

#0 : 0

Use default thresholds.

End of enumeration elements list.

ZEROBUFB : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

Don't zeroize the buffer

#0 : 0

Zeroize the buffer

End of enumeration elements list.

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRFSTB

ASRC FIFO Status Register for Pair B
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRFSTB ASRFSTB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFIFO_FILLB RESERVED IAEB OUTFIFO_FILLB RESERVED OAFB RESERVED

INFIFO_FILLB : no description available
bits : 0 - 6 (7 bit)
access : read-only

RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only

IAEB : no description available
bits : 11 - 11 (1 bit)
access : read-only

OUTFIFO_FILLB : no description available
bits : 12 - 18 (7 bit)
access : read-only

RESERVED : no description available
bits : 19 - 22 (4 bit)
access : read-only

OAFB : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRMCRC

ASRC Misc Control Register for Pair C
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRMCRC ASRMCRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFIFO_THRESHOLDC RESERVED RSYNOFC RSYNIFC OUTFIFO_THRESHOLDC RESERVED BYPASSPOLYC BUFSTALLC EXTTHRSHC ZEROBUFC RESERVED

INFIFO_THRESHOLDC : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 9 (4 bit)
access : read-only

RSYNOFC : no description available
bits : 10 - 10 (1 bit)
access : read-write

RSYNIFC : no description available
bits : 11 - 11 (1 bit)
access : read-write

OUTFIFO_THRESHOLDC : no description available
bits : 12 - 17 (6 bit)
access : read-write

RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only

BYPASSPOLYC : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#1 : 1

Bypass polyphase filtering.

#0 : 0

Don't bypass polyphase filtering.

End of enumeration elements list.

BUFSTALLC : no description available
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#1 : 1

Stall Pair C conversion in case of near empty/full FIFO conditions.

#0 : 0

Don't stall Pair C conversion even in case of near empty/full FIFO conditions.

End of enumeration elements list.

EXTTHRSHC : no description available
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#1 : 1

Use external defined thresholds.

#0 : 0

Use default thresholds.

End of enumeration elements list.

ZEROBUFC : no description available
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#1 : 1

Don't zeroize the buffer

#0 : 0

Zeroize the buffer

End of enumeration elements list.

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRFSTC

ASRC FIFO Status Register for Pair C
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRFSTC ASRFSTC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INFIFO_FILLC RESERVED IAEC OUTFIFO_FILLC RESERVED OAFC RESERVED

INFIFO_FILLC : no description available
bits : 0 - 6 (7 bit)
access : read-only

RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only

IAEC : no description available
bits : 11 - 11 (1 bit)
access : read-only

OUTFIFO_FILLC : no description available
bits : 12 - 18 (7 bit)
access : read-only

RESERVED : no description available
bits : 19 - 22 (4 bit)
access : read-only

OAFC : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRCNCR

ASRC Channel Number Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRCNCR ASRCNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANCA ANCB ANCC RESERVED RESERVED

ANCA : no description available
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

0 channels in A (Pair A is disabled)

#0001 : 0001

1 channel in A

#0010 : 0010

2 channels in A

#0011 : 0011

3 channels in A

#0100 : 0100

4 channels in A

#0101 : 0101

5 channels in A

#0110 : 0110

6 channels in A

#0111 : 0111

7 channels in A

#1000 : 1000

8 channels in A

#1001 : 1001

9 channels in A

#1010 : 1010

10 channels in A

End of enumeration elements list.

ANCB : no description available
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

0 channels in B (Pair B is disabled)

#0001 : 0001

1 channel in B

#0010 : 0010

2 channels in B

#0011 : 0011

3 channels in B

#0100 : 0100

4 channels in B

#0101 : 0101

5 channels in B

#0110 : 0110

6 channels in B

#0111 : 0111

7 channels in B

#1000 : 1000

8 channels in B

#1001 : 1001

9 channels in B

#1010 : 1010

10 channels in B

End of enumeration elements list.

ANCC : no description available
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

0 channels in C (Pair C is disabled)

#0001 : 0001

1 channel in C

#0010 : 0010

2 channels in C

#0011 : 0011

3 channels in C

#0100 : 0100

4 channels in C

#0101 : 0101

5 channels in C

#0110 : 0110

6 channels in C

#0111 : 0111

7 channels in C

#1000 : 1000

8 channels in C

#1001 : 1001

9 channels in C

#1010 : 1010

10 channels in C

End of enumeration elements list.

RESERVED : no description available
bits : 12 - 23 (12 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRDIA

ASRC Data Input Register for Pair x
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRDIA ASRDIA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA RESERVED

DATA : no description available
bits : 0 - 23 (24 bit)
access : write-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRPMn2

ASRC Parameter Register n
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASRPMn2 ASRPMn2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMETER_VALUE RESERVED

PARAMETER_VALUE : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


ASRDOA

ASRC Data Output Register for Pair x
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASRDOA ASRDOA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA RESERVED

DATA : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only



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