Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x64 byte (0x0)
mem_usage : registers
protection : not protected
Power Gating Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG_PD1 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not switch off power to power domain1.
#1 : 1
Switch off power domain 1 (LPSTOP mode).
End of enumeration elements list.
PG_16K : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not switch off 16K RAM Power Switch during LPSTOP3 and LPSTOP2 mode
#1 : 1
Switch off 16K RAM Power Switch during LPSTOP1 mode.
End of enumeration elements list.
PG_48K : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not switch off 64K RAM (16K and 48K RAM Power Switch) during LPSTOP3 mode.
#1 : 1
Switch off 48K RAM Power Switch during LPSTOP2 or LPSTOP1 mode.
End of enumeration elements list.
HP_OFF : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
HPREG ON in STOP mode.
#1 : 1
HPREG OFF in STOP mode.
End of enumeration elements list.
WB_STOP : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Well Bias disabled in STOP mode.
#1 : 1
Well Bias enabled in STOP mode.
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only
DS_LPSTOP : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Deep Sleep signal to memories is not asserted in LPSTOP mode.
#1 : 1
Deep Sleep signal to memories is asserted in LPSTOP mode.
End of enumeration elements list.
DS_STOP : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Deep Sleep signal to memories is not asserted in STOP mode.
#1 : 1
Deep Sleep signal to memories is asserted in STOP mode.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
Low Power Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLPCR : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
RUN
#01 : 01
WAIT
#10 : 10
STOP
#11 : 11
RSVD
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 31 (30 bit)
access : read-only
Interrupt Mask Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 19 (20 bit)
access : read-only
WDOGA5 : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable WDOGA5 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from WDOGA5 as source of wake-up from STOP mode.
End of enumeration elements list.
WDOGM4 : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable WDOGM4 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from WDOGM4 as source of wake-up from STOP mode.nable
End of enumeration elements list.
WDOGSNVS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable WDOGSNVS interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from WDOGSNVS as source of wake-up from STOP mode.
End of enumeration elements list.
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-write
QSPI0 : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable QSPI0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from QSPI0 as source of wake-up from STOP mode.
End of enumeration elements list.
QSPI1 : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable QSPI1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from QSPI1 as source of wake-up from STOP mode.
End of enumeration elements list.
DRAMC : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DRAMCinterrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DRAMC as source of wake-up from STOP mode.
End of enumeration elements list.
SDHC0 : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable SDHC0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from SDHC0 as source of wake-up from STOP mode.
End of enumeration elements list.
SDHC1 : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable SDHC1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from SDHC1 as source of wake-up from STOP mode.
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only
DCU0 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DCU0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DCU0 as source of wake-up from STOP mode.
End of enumeration elements list.
DCU1 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DCU1 interrupt as source of wake-up from STOP mode.
#1 : 1
Ignore interrupt from DCU1 as source of wake-up from STOP mode.
End of enumeration elements list.
Interrupt Mask Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIU : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable VIU interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from VIU as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only
GPU : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable GPU interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from GPU as source of wake-up from STOP mode
End of enumeration elements list.
RLE : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable RLE interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from RLE as source of wake-up from STOP mode
End of enumeration elements list.
LCD : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable SEG LCD interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from SEG LCD as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 6 (2 bit)
access : read-only
PIT : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable PIT interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from PIT as source of wake-up from STOP mode
End of enumeration elements list.
LPTMR : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable LPTMR interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from LPTMR as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only
FTM0 : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable FTM0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from FTM0 as source of wake-up from STOP mode
End of enumeration elements list.
FTM1 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable FTM1 interrupt as source of wake-up from STOP
#1 : 1
Ignore interrupt from FTM1 as source of wake-up from STOP mode
End of enumeration elements list.
FTM2 : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable FTM2 interrupt as source of wake-up from STOP
#1 : 1
Ignore interrupt from FTM2 as source of wake-up from STOP mode
End of enumeration elements list.
FTM3 : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable FTM3 interrupt as source of wake-up from STOP
#1 : 1
Ignore interrupt from FTM3 as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 14 - 17 (4 bit)
access : read-only
ANADIGB : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ANADIGB interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ANADIGB as source of wake-up from STOP mode
End of enumeration elements list.
ANADIGA : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ANADIGA interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ANADIGA as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only
ADC0 : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ADC0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ADC0 as source of wake-up from STOP mode
End of enumeration elements list.
ADC1 : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ADC1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ADC1 as source of wake-up from STOP mode
End of enumeration elements list.
DAC0 : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DAC0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DAC0 as source of wake-up from STOP mode
End of enumeration elements list.
DAC1 : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DAC1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DAC1 as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-only
FLEXCAN0 : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable FLEXCAN0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from FLEXCAN0 as source of wake-up from STOP mode
End of enumeration elements list.
FLEXCAN1 : Masks FLEXCAN1 interrupt
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable FLEXCAN1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from FLEXCAN1 as source of wake-up from STOP mode
End of enumeration elements list.
MLB : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable MLB interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from MLB as source of wake-up from STOP mode
End of enumeration elements list.
UART0 : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable UART0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from UART0 as source of wake-up from STOP mode
End of enumeration elements list.
UART1 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable UART1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from UART1 as source of wake-up from STOP mode
End of enumeration elements list.
UART2 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable UART2 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from UART2 as source of wake-up from STOP mode
End of enumeration elements list.
Interrupt Mask Register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART3 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable UART3 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from UART3 as source of wake-up from STOP mode
End of enumeration elements list.
UART4 : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable UART4 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from UART4 as source of wake-up from STOP mode
End of enumeration elements list.
UART5 : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable UART5 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from UART5 as source of wake-up from STOP mode
End of enumeration elements list.
DSPI0 : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DSPI0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interruptfrom DSPI0 as source of wake-up from STOP mode
End of enumeration elements list.
DSPI1 : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DSPI1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DSPI1 as source of wake-up from STOP mode
End of enumeration elements list.
DSPI2 : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DSPI2 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DSPI2 as source of wake-up from STOP mode
End of enumeration elements list.
DSPI3 : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable DSPI3 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from DSPI3 as source of wake-up from STOP mode
End of enumeration elements list.
I2C0 : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable I2C0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from I2C0 as source of wake-up from STOP mode
End of enumeration elements list.
I2C1 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable I2C1interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from I2C1 as source of wake-up from STOP mode
End of enumeration elements list.
I2C2 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable I2C2 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from I2C2 as source of wake-up from STOP mode
End of enumeration elements list.
I2C3 : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable I2C3 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from I2C3 as source of wake-up from STOP mode
End of enumeration elements list.
USBC0 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable USBC0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from USBC0 as source of wake-up from STOP mode
End of enumeration elements list.
USBC1 : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable USBC1interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from USBC1as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 13 (1 bit)
access : read-only
ENET0 : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ENET0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ENET0 as source of wake-up from STOP mode
End of enumeration elements list.
ENET1 : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ENET1interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ENET0 as source of wake-up from STOP mode
End of enumeration elements list.
1588T0 : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable 1588T0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from 1588T0 as source of wake-up from STOP mode
End of enumeration elements list.
1588T1 : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable 1588T1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from 1588T1as source of wake-up from STOP mode
End of enumeration elements list.
ESW : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ESW interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ESW as source of wake-up from STOP mode
End of enumeration elements list.
NFC : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable NFC interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from NFC as source of wake-up from STOP mode
End of enumeration elements list.
UNIMPLEMENTED : no description available
bits : 20 - 23 (4 bit)
access : read-write
ESAI : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ESAI interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ESAI as source of wake-up from STOP mode
End of enumeration elements list.
SPDIF : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable SPDIF interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from SPDIFas source of wake-up from STOP mode
End of enumeration elements list.
ASRC : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable ASRC interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from ASRC as source of wake-up from STOP mode
End of enumeration elements list.
CMU : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable CMU interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from CMU as source of wake-up from STOP mode
End of enumeration elements list.
WKPU0 : Masks WKPU0 interrupt
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable WKPU0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from WKPU0 as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only
CCM_A : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable CCM_A interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from CCM_A as source of wake-up from STOP mode
End of enumeration elements list.
CCM_B : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable CCM_B interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from CCM_B as source of wake-up from STOP mode
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : Configuring this bit will not guarantee chip functionality.
bits : 0 - 0 (1 bit)
access : read-write
PDB : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable PDB interrupt as source of wake-up from STOP mode
#1 : 1
Mask interrupt from PDB as source of wake-up from STOP
End of enumeration elements list.
EWM : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable EWM interrupt as source of wake-up from STOP mode
#1 : 1
Mask interrupt from EWM as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
SNVS_A : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable SNVS interrupt as source of wake-up from STOP mode
#1 : 1
Mask interrupt from SNVS as source of wake-up from STOP mode
End of enumeration elements list.
SNVS_B : no description available
bits : 5 - 5 (1 bit)
access : read-write
CAAM : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable CAAM interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from CAAM as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only
GPIO0 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable GPIO0 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from GPIO0 as source of wake-up from STOP mode
End of enumeration elements list.
GPIO1 : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable GPIO1 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from GPIO1 as source of wake-up from STOP mode
End of enumeration elements list.
GPIO2 : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable GPIO2 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from GPIO2 as source of wake-up from STOP mode
End of enumeration elements list.
GPIO3 : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable GPIO3 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from GPIO3 as source of wake-up from STOP mode
End of enumeration elements list.
GPIO4 : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable GPIO4 interrupt as source of wake-up from STOP mode
#1 : 1
Ignore interrupt from GPIO4 as source of wake-up from STOP mode
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Interrupt Status Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 19 (20 bit)
access : read-only
WDOGA5 : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ADOGA5
#1 : 1
Interrupt generated from WDOGA5
End of enumeration elements list.
WDOGM4 : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from WDOGM4
#1 : 1
Interrupt generated from WDOGM4
End of enumeration elements list.
WDOGSNVS : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from WDOGSNVS
#1 : 1
Interrupt generated from WDOGSNVS
End of enumeration elements list.
RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-write
QSPI0 : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from QSPI0
#1 : 1
Interrupt generated from QSPI0
End of enumeration elements list.
QSPI1 : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from QSPI1
#1 : 1
Interrupt generated from QSPI1
End of enumeration elements list.
DRAMC : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DRAMC
#1 : 1
Interrupt generated from DRAMC
End of enumeration elements list.
SDHC0 : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from SDHC0
#1 : 1
Interrupt generated from SDHC0
End of enumeration elements list.
SDHC1 : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from SDHC1
#1 : 1
Interrupt generated from SDHC1
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only
DCU0 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DCU0
#1 : 1
Interrupt generated from DCU0
End of enumeration elements list.
DCU1 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DCU1
#1 : 1
Interrupt generated from DCU1
End of enumeration elements list.
Interrupt Status Register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VIU : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from VIU
#1 : 1
Interrupt generated from VIU
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only
GPU : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from GPU
#1 : 1
Interrupt generated from GPU
End of enumeration elements list.
RLE : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from RLE
#1 : 1
Interrupt generated from RLE
End of enumeration elements list.
LCD : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from LCD
#1 : 1
Interrupt generated from LCD
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 6 (2 bit)
access : read-only
PIT : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from PIT
#1 : 1
Interrupt generated from PIT
End of enumeration elements list.
LPTMR : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from LPTMR
#1 : 1
Interrupt generated from LPTMR
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only
FTM : no description available
bits : 10 - 13 (4 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from FTM
#1 : 1
Interrupt generated from FTM
End of enumeration elements list.
RESERVED : no description available
bits : 14 - 17 (4 bit)
access : read-only
ANADIGB : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ANADIGB
#1 : 1
Interrupt generated from ANADIGB
End of enumeration elements list.
ANADIGA : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ANADIGA
#1 : 1
Interrupt generated from ANADIGA
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 20 (1 bit)
access : read-only
ADC0 : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ADC0
#1 : 1
Interrupt generated from ADC0
End of enumeration elements list.
ADC1 : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ADC1
#1 : 1
Interrupt generated from ADC1
End of enumeration elements list.
DAC0 : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DAC0
#1 : 1
Interrupt generated from DAC0
End of enumeration elements list.
DAC1 : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DAC1
#1 : 1
Interrupt generated from DAC1
End of enumeration elements list.
RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-only
Flex : no description available
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from Flex
#1 : 1
Interrupt generated from Flex
End of enumeration elements list.
MLB : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from MLB
#1 : 1
Interrupt generated from MLB
End of enumeration elements list.
UART0 : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from UART0
#1 : 1
Interrupt generated from UART0
End of enumeration elements list.
UART1 : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from UART1
#1 : 1
Interrupt generated from UART1
End of enumeration elements list.
UART2 : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from UART2
#1 : 1
Interrupt generated from UART2
End of enumeration elements list.
Interrupt Status Register 3
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART3 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from UART3
#1 : 1
Interrupt generated from UART3
End of enumeration elements list.
UART4 : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from UART4
#1 : 1
Interrupt generated from UART4
End of enumeration elements list.
UART5 : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from UART5
#1 : 1
Interrupt generated from UART5
End of enumeration elements list.
DSPI0 : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DSPI0
#1 : 1
Interrupt generated from DSPI0
End of enumeration elements list.
DSPI1 : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DSPI1
#1 : 1
Interrupt generated from DSPI1
End of enumeration elements list.
DSPI2 : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DSPI2
#1 : 1
Interrupt generated from DSPI2
End of enumeration elements list.
DSPI3 : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from DSPI3
#1 : 1
Interrupt generated from DSPI3
End of enumeration elements list.
I2C0 : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from I2C0
#1 : 1
Interrupt generated from I2C0
End of enumeration elements list.
I2C1 : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from I2C1
#1 : 1
Interrupt generated from I2C1
End of enumeration elements list.
I2C2 : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from I2C2
#1 : 1
Interrupt generated from I2C2
End of enumeration elements list.
I2C3 : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from I2C3
#1 : 1
Interrupt generated from I2C3
End of enumeration elements list.
USBC0 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from USBC0
#1 : 1
Interrupt generated from USBC0
End of enumeration elements list.
USBC1 : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from USBC1
#1 : 1
Interrupt generated from USBC1
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 13 (1 bit)
access : read-only
ENET0 : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ENET0
#1 : 1
Interrupt generated from ENET0
End of enumeration elements list.
ENET1 : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ENET1
#1 : 1
Interrupt generated from ENET1
End of enumeration elements list.
1588T0 : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from 1588T0
#1 : 1
Interrupt generated from 1588T0
End of enumeration elements list.
1588T1 : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from 1588T1
#1 : 1
Interrupt generated from 1588T1
End of enumeration elements list.
ESW : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ESW
#1 : 1
Interrupt generated from ESW
End of enumeration elements list.
NFC : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from NFC
#1 : 1
Interrupt generated from NFC
End of enumeration elements list.
UNIMPLEMENTED : no description available
bits : 20 - 23 (4 bit)
access : read-write
ESAI : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ESAI
#1 : 1
Interrupt generated from ESAI
End of enumeration elements list.
SPDIF : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from SPDIF
#1 : 1
Interrupt generated from SPDIF
End of enumeration elements list.
ASRC : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from ASRC
#1 : 1
Interrupt generated from ASRC
End of enumeration elements list.
CMU : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from CMU
#1 : 1
Interrupt generated from CMU
End of enumeration elements list.
WKPU0 : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from WKPU0
#1 : 1
Interrupt generated from WKPU0
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 29 (1 bit)
access : read-only
CCM_A : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from CCM_A
#1 : 1
Interrupt generated from CCM_A
End of enumeration elements list.
CCM_B : no description available
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from CCM_A
#1 : 1
Interrupt generated from CCM_A
End of enumeration elements list.
Interrupt Status Register 4
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-write
PDB : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from PDB
#1 : 1
Interrupt generated from PDB
End of enumeration elements list.
EWM : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from EWM
#1 : 1
Interrupt generated from EWM
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
SNVS_A : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from SNVS_A
#1 : 1
Interrupt generated from SNVS_A
End of enumeration elements list.
SNVS_B : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from SNVS_B
#1 : 1
Interrupt generated from SNVS_B
End of enumeration elements list.
CAAM : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from CAAM
#1 : 1
Interrupt generated from CAAM
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 10 (4 bit)
access : read-only
GPIO0 : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from GPIO0
#1 : 1
Interrupt generated from GPIO)
End of enumeration elements list.
GPIO1 : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from GPIO1
#1 : 1
Interrupt generated from GPIO1
End of enumeration elements list.
GPIO2 : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from GPIO2
#1 : 1
Interrupt generated from GPIO2
End of enumeration elements list.
GPIO3 : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from GPIO3
#1 : 1
Interrupt generated from GPIO3
End of enumeration elements list.
GPIO4 : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt from GPIO4
#1 : 1
Interrupt generated from GPIO4
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
Power Gating Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSR : no description available
bits : 0 - 0 (1 bit)
access : read-write
CUR_LPM : Current Low Power Mode
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
#00 : 00
RUN mode
#01 : 01
WAIT mode
#10 : 10
STOP mode
#11 : 11
LPSTOPn mode
End of enumeration elements list.
PREV_LPM : no description available
bits : 3 - 4 (2 bit)
access : read-only
Enumeration:
#00 : 00
RUN mode
#01 : 01
WAIT mode
#10 : 10
STOP mode
#11 : 11
LPSTOPn mode
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only
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