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OCOTP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xCF4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TIMING

DATA

READ_CTRL

CTRL_SET

READ_FUSE_DATA

LOCK

CFG0

CFG1

CFG4

CFG5

ANA2

OTPMK0

OTPMK1

OTPMK2

OTPMK3

OTPMK4

OTPMK5

OTPMK6

OTPMK7

SRK0

SRK1

SRK2

SRK3

SRK4

SRK5

SRK6

SRK7

SCS

RESP0

HSJC_RESP1

MAC0

MAC1

SCS_SET

MAC2

MAC3

GP1

GP2

SCS_CLR

CSU_ALARM

SCS_TOG

SRK_REVOKE

CRC_ADDR

CTRL_CLR

CRC_VALUE

TFUSE0

TFUSE1

VDD_TRIM

PMUR

PMU

RNG

VTD_TRIM

VTMON

VERSION

CTRL_TOG

CRC0

CRC1

CRC2

CRC3

CRC4

CRC5

CRC6

CRC7


CTRL

OTP Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RESERVED BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RESERVED WR_UNLOCK

ADDR : no description available
bits : 0 - 6 (7 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

BUSY : no description available
bits : 8 - 8 (1 bit)
access : read-only

ERROR : no description available
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : no description available
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : no description available
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : no description available
bits : 12 - 12 (1 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : no description available
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

#11111001110111 : 11111001110111

Key needed to unlock OCOTP_DATA register.

End of enumeration elements list.


TIMING

OTP Controller Timing Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STROBE_PROG RELAX STROBE_READ WAIT RESERVED

STROBE_PROG : no description available
bits : 0 - 11 (12 bit)
access : read-write

RELAX : no description available
bits : 12 - 15 (4 bit)
access : read-write

STROBE_READ : no description available
bits : 16 - 21 (6 bit)
access : read-write

WAIT : no description available
bits : 22 - 27 (6 bit)
access : read-write

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only


DATA

OTP Controller Write Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : no description available
bits : 0 - 31 (32 bit)
access : read-write


READ_CTRL

OTP Controller Read Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_CTRL READ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_FUSE RESERVED

READ_FUSE : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only


CTRL_SET

OTP Controller Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_SET CTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RESERVED BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RESERVED WR_UNLOCK

ADDR : no description available
bits : 0 - 6 (7 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

BUSY : no description available
bits : 8 - 8 (1 bit)
access : read-only

ERROR : no description available
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : no description available
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : no description available
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : no description available
bits : 12 - 12 (1 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : no description available
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

#11111001110111 : 11111001110111

Key needed to unlock OCOTP_DATA register.

End of enumeration elements list.


READ_FUSE_DATA

OTP Controller Read Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_FUSE_DATA READ_FUSE_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : no description available
bits : 0 - 31 (32 bit)
access : read-write


LOCK

Value of OTP Bank0 Word0 (Lock controls)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED BOOT_CFG_LOCK RESERVED SJC_RESP_LOCK RESERVED MAC_ADDR_LOCK GP1_LOCK GP2_LOCK SRK_LOCK RESERVED RESERVED ANALOG_LOCK PMU_LOCK MISC_CONF_LOCK RESERVED CRC_GP_LO_LOCK CRC_GP_HI_LOCK RESERVED

RESERVED : no description available
bits : 0 - 1 (2 bit)
access : read-only

BOOT_CFG_LOCK : Perform lock on BOOT related fuses.
bits : 2 - 3 (2 bit)
access : read-only

RESERVED : no description available
bits : 4 - 5 (2 bit)
access : read-only

SJC_RESP_LOCK : no description available
bits : 6 - 6 (1 bit)
access : read-only

RESERVED : Reserved.
bits : 7 - 7 (1 bit)
access : read-only

MAC_ADDR_LOCK : Lock MAC_ADDR fuses.
bits : 8 - 9 (2 bit)
access : read-only

GP1_LOCK : Lock for General Purpose fuse register #1 (GP1)
bits : 10 - 11 (2 bit)
access : read-only

GP2_LOCK : Lock for General Purpose fuse register #2 (GP2)
bits : 12 - 13 (2 bit)
access : read-only

SRK_LOCK : no description available
bits : 14 - 14 (1 bit)
access : read-only

RESERVED : no description available
bits : 15 - 16 (2 bit)
access : read-only

RESERVED : no description available
bits : 17 - 17 (1 bit)
access : read-only

ANALOG_LOCK : no description available
bits : 18 - 19 (2 bit)
access : read-only

PMU_LOCK : no description available
bits : 20 - 21 (2 bit)
access : read-only

MISC_CONF_LOCK : no description available
bits : 22 - 22 (1 bit)
access : read-only

RESERVED : no description available
bits : 23 - 25 (3 bit)
access : read-only

CRC_GP_LO_LOCK : no description available
bits : 26 - 27 (2 bit)
access : read-only

CRC_GP_HI_LOCK : no description available
bits : 28 - 29 (2 bit)
access : read-only

RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only


CFG0

Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SJC_CHALL

SJC_CHALL : no description available
bits : 0 - 31 (32 bit)
access : read-write


CFG1

Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SJC_CHALL

SJC_CHALL : no description available
bits : 0 - 31 (32 bit)
access : read-write


CFG4

Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG4 CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOOT_CFG1 BOOT_CFG2 BOOT_CFG3 BOOT_CFG4

BOOT_CFG1 : no description available
bits : 0 - 7 (8 bit)
access : read-write

BOOT_CFG2 : no description available
bits : 8 - 15 (8 bit)
access : read-write

BOOT_CFG3 : no description available
bits : 16 - 23 (8 bit)
access : read-write

BOOT_CFG4 : no description available
bits : 24 - 31 (8 bit)
access : read-write


CFG5

Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG5 CFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SEC_CONFIG RESERVED DIR_BT_DIS BT_FUSE_SEL RESERVED RESERVED CSU_ALARM_DISABLE SJC_DISABLE WDOG_ENABLE JTAG_SMODE RESERVED KTE JTAG_HEO RESERVED

RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-write

SEC_CONFIG : Security Configuration (with SEC_CONFIG[0]).
bits : 1 - 1 (1 bit)
access : read-write

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-write

DIR_BT_DIS : Direct Boot Disable.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable

#1 : 1

Disable

End of enumeration elements list.

BT_FUSE_SEL : Determines, whether using fuses for boot configuration, or GPIO /Serial loader.
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 17 (13 bit)
access : read-only

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write

CSU_ALARM_DISABLE : CSU Alarm disable bit.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

CSU alarms are enabled

#1 : 1

CSU alarams are disabled

End of enumeration elements list.

SJC_DISABLE : Secure JTAG Controller module.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Secure JTAG Controller is enabled

#1 : 1

Secure JTAG Controller is disabled

End of enumeration elements list.

WDOG_ENABLE : Watchdog Enable.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watch-Dog is disabled.

#1 : 1

Watch-Dog is enabled.

End of enumeration elements list.

JTAG_SMODE : JTAG Security Mode.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 00

JTAG enable mode

#01 : 01

Secure JTAG mode

#11 : 11

No debug mode

End of enumeration elements list.

RESERVED : no description available
bits : 24 - 25 (2 bit)
access : read-only

KTE : Kill Trace Enable.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bus tracing is allowed

#1 : 1

Bus tracing is allowed in case security state as defined by Secure JTAG allows it (for example, JTAG_ENABLE or NO_DEBUG)

End of enumeration elements list.

JTAG_HEO : JTAG HAB Enable Override.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

HAB may enable JTAG debug access

#1 : 1

HAB JTAG enable is overridden (HAB may not enable JTAG debug access)

End of enumeration elements list.

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only


ANA2

Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANA2 ANA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VID USB0_PID

USB_VID : USB Vendor ID.
bits : 0 - 15 (16 bit)
access : read-write

USB0_PID : USB Product ID.
bits : 16 - 31 (16 bit)
access : read-write


OTPMK0

Shadow Register for OTP Bank2 Word0 (OTPMK and CRYPTO Key)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK0 OTPMK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK1

Shadow Register for OTP Bank2 Word1 (OTPMK and CRYPTO Key)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK1 OTPMK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK2

Shadow Register for OTP Bank2 Word2 (OTPMK and CRYPTO Key)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK2 OTPMK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK3

Shadow Register for OTP Bank2 Word3 (OTPMK and CRYPTO Key)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK3 OTPMK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK4

Shadow Register for OTP Bank2 Word4 (OTPMK Key)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK4 OTPMK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK5

Shadow Register for OTP Bank2 Word5 (OTPMK Key)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK5 OTPMK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK6

Shadow Register for OTP Bank2 Word6 (OTPMK Key)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK6 OTPMK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


OTPMK7

Shadow Register for OTP Bank2 Word7 (OTPMK Key)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTPMK7 OTPMK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTPMK

OTPMK : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK0

Shadow Register for OTP Bank3 Word0 (SRK Hash)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK0 SRK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK1

Shadow Register for OTP Bank3 Word1 (SRK Hash)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK1 SRK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK2

Shadow Register for OTP Bank3 Word2 (SRK Hash)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK2 SRK2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK3

Shadow Register for OTP Bank3 Word3 (SRK Hash)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK3 SRK3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK4

Shadow Register for OTP Bank3 Word4 (SRK Hash)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK4 SRK4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK5

Shadow Register for OTP Bank3 Word5 (SRK Hash)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK5 SRK5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK6

Shadow Register for OTP Bank3 Word6 (SRK Hash)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK6 SRK6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SRK7

Shadow Register for OTP Bank3 Word7 (SRK Hash)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK7 SRK7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SCS

Software Controllable Set Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS SCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

JTAG debugging is enabled by the HAB (though this signal may be gated off)

End of enumeration elements list.

SPARE : no description available
bits : 1 - 30 (30 bit)
access : read-write

LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-write


RESP0

Value of OTP Bank4 Word0 (Secure JTAG Response Field)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP0 RESP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


HSJC_RESP1

Value of OTP Bank4 Word1 (Secure JTAG Response Field)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSJC_RESP1 HSJC_RESP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


MAC0

Value of OTP Bank4 Word2 (MAC Address)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC0 MAC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


MAC1

Value of OTP Bank4 Word3 (MAC Address)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC1 MAC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SCS_SET

Software Controllable Set Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_SET SCS_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

JTAG debugging is enabled by the HAB (though this signal may be gated off)

End of enumeration elements list.

SPARE : no description available
bits : 1 - 30 (30 bit)
access : read-write

LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-write


MAC2

Value of OTP Bank4 Word4 (MAC Address)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC2 MAC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


MAC3

Value of OTP Bank4 Word5 (MAC Address)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAC3 MAC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


GP1

Value of OTP Bank4 Word6 (HW Capabilities)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP1 GP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


GP2

Value of OTP Bank4 Word7 (HW Capabilities)
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP2 GP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS

BITS : no description available
bits : 0 - 31 (32 bit)
access : read-write


SCS_CLR

Software Controllable Set Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_CLR SCS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

JTAG debugging is enabled by the HAB (though this signal may be gated off)

End of enumeration elements list.

SPARE : no description available
bits : 1 - 30 (30 bit)
access : read-write

LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-write


CSU_ALARM

Value of OTP Bank5 Word0
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSU_ALARM CSU_ALARM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALARM_DIS ALARM_OUT COUNTER_ALARM RESERVED

ALARM_DIS : no description available
bits : 0 - 1 (2 bit)
access : read-write

ALARM_OUT : no description available
bits : 2 - 3 (2 bit)
access : read-write

COUNTER_ALARM : CSU Fuse force counter alarm.
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only


SCS_TOG

Software Controllable Set Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCS_TOG SCS_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAB_JDE SPARE LOCK

HAB_JDE : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#1 : 1

JTAG debugging is enabled by the HAB (though this signal may be gated off)

End of enumeration elements list.

SPARE : no description available
bits : 1 - 30 (30 bit)
access : read-write

LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-write


SRK_REVOKE

Value of OTP Bank5 Word7 (HW Capabilities)
address_offset : 0x6F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRK_REVOKE SRK_REVOKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED MC_ERA AP_BI_VER

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

MC_ERA : no description available
bits : 8 - 15 (8 bit)
access : read-write

AP_BI_VER : no description available
bits : 16 - 31 (16 bit)
access : read-write


CRC_ADDR

OTP Controller CRC address
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_ADDR CRC_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_START_ADDR DATA_END_ADDR CRC_ADDR RESERVED

DATA_START_ADDR : no description available
bits : 0 - 7 (8 bit)
access : read-write

DATA_END_ADDR : no description available
bits : 8 - 15 (8 bit)
access : read-write

CRC_ADDR : no description available
bits : 16 - 18 (3 bit)
access : read-write

RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-only


CTRL_CLR

OTP Controller Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_CLR CTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RESERVED BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RESERVED WR_UNLOCK

ADDR : no description available
bits : 0 - 6 (7 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

BUSY : no description available
bits : 8 - 8 (1 bit)
access : read-only

ERROR : no description available
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : no description available
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : no description available
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : no description available
bits : 12 - 12 (1 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : no description available
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

#11111001110111 : 11111001110111

Key needed to unlock OCOTP_DATA register.

End of enumeration elements list.


CRC_VALUE

OTP Controller CRC Value Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC_VALUE CRC_VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : no description available
bits : 0 - 31 (32 bit)
access : read-write


TFUSE0

Value of OTP Bank7 Word0 (Configuration and Manufacturing Info.)
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TFUSE0 TFUSE0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


TFUSE1

Value of OTP Bank7 Word1 (Configuration and Manufacturing Info.)
address_offset : 0x890 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TFUSE1 TFUSE1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED

RESERVED : no description available
bits : 0 - 7 (8 bit)
access : read-only

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


VDD_TRIM

Value of OTP Bank7 Word2 (Configuration and Manufacturing Info.)
address_offset : 0x8A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VDD_TRIM VDD_TRIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

RESERVED : no description available
bits : 4 - 6 (3 bit)
access : read-only

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

RESERVED : no description available
bits : 8 - 10 (3 bit)
access : read-only

RESERVED : no description available
bits : 11 - 11 (1 bit)
access : read-only

RESERVED : no description available
bits : 12 - 13 (2 bit)
access : read-only

RESERVED : no description available
bits : 14 - 31 (18 bit)
access : read-only


PMUR

Value of OTP Bank7 Word3 (Configuration and Manufacturing Info.)
address_offset : 0x8B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PMUR PMUR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED RESERVED RESERVED

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only

RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only

RESERVED : no description available
bits : 16 - 23 (8 bit)
access : read-only

RESERVED : no description available
bits : 24 - 27 (4 bit)
access : read-only

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only


PMU

Value of OTP Bank7 Word4 (Configuration and Manufacturing Info.)
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PMU PMU read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED

RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only


RNG

Value of OTP Bank7 Word5 (Memory Related Info.)
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNG RNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADC_BANDGAP RESERVED ADC0_CAL ADC1_CAL RESERVED RNG_TRIM

VADC_BANDGAP : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

ADC0_CAL : no description available
bits : 8 - 11 (4 bit)
access : read-write

ADC1_CAL : no description available
bits : 12 - 15 (4 bit)
access : read-write

RESERVED : no description available
bits : 16 - 23 (8 bit)
access : read-write

RNG_TRIM : no description available
bits : 24 - 31 (8 bit)
access : read-write


VTD_TRIM

Value of OTP Bank7 Word6 (Memory Related Info.)
address_offset : 0x8E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTD_TRIM VTD_TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOLTAGE_MON_TRIM TEMP_MON_TRIM RESERVED VOLT_TEMP_TAMPER_BGR_TRIM VOLT_MON_DIS TEMP_MON_DIS

VOLTAGE_MON_TRIM : no description available
bits : 0 - 9 (10 bit)
access : read-write

TEMP_MON_TRIM : no description available
bits : 10 - 19 (10 bit)
access : read-write

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

VOLT_TEMP_TAMPER_BGR_TRIM : The tamper detect BGR Trim.
bits : 24 - 29 (6 bit)
access : read-write

VOLT_MON_DIS : Voltage mointor enable.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable

#1 : 1

Disable

End of enumeration elements list.

TEMP_MON_DIS : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable

#1 : 1

Disable

End of enumeration elements list.


VTMON

Value of OTP Bank7 Word7 (Memory Related Info.)
address_offset : 0x8F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTMON VTMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOLT_TEMP_TAMPER_PROG RESERVED USB1_PID

VOLT_TEMP_TAMPER_PROG : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 15 (10 bit)
access : read-only

USB1_PID : no description available
bits : 16 - 31 (16 bit)
access : read-write


VERSION

OTP Controller Version Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : no description available
bits : 0 - 15 (16 bit)
access : read-only

MINOR : no description available
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : no description available
bits : 24 - 31 (8 bit)
access : read-only


CTRL_TOG

OTP Controller Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_TOG CTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR RESERVED BUSY ERROR RELOAD_SHADOWS CRC_TEST CRC_FAIL RESERVED WR_UNLOCK

ADDR : no description available
bits : 0 - 6 (7 bit)
access : read-write

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

BUSY : no description available
bits : 8 - 8 (1 bit)
access : read-only

ERROR : no description available
bits : 9 - 9 (1 bit)
access : read-write

RELOAD_SHADOWS : no description available
bits : 10 - 10 (1 bit)
access : read-write

CRC_TEST : no description available
bits : 11 - 11 (1 bit)
access : read-write

CRC_FAIL : no description available
bits : 12 - 12 (1 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only

WR_UNLOCK : no description available
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

#11111001110111 : 11111001110111

Key needed to unlock OCOTP_DATA register.

End of enumeration elements list.


CRC0

Value of OTP Bank15 Word0
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC0 CRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC1

Value of OTP Bank15 Word1
address_offset : 0xC90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC1 CRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC2

Value of OTP Bank15 Word2
address_offset : 0xCA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC2 CRC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC3

Value of OTP Bank15 Word3
address_offset : 0xCB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC3 CRC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC4

Value of OTP Bank15 Word4
address_offset : 0xCC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC4 CRC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC5

Value of OTP Bank15 Word5
address_offset : 0xCD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC5 CRC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC6

Value of OTP Bank15 Word6
address_offset : 0xCE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC6 CRC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write


CRC7

Value of OTP Bank15 Word7
address_offset : 0xCF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC7 CRC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC32

CRC32 : no description available
bits : 0 - 31 (32 bit)
access : read-write



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