\n

ESW

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50C byte (0x0)
mem_usage : registers
protection : not protected

Registers

REV

VLANV

P0VRES

P1VRES

P2VRES

DBCR

IPRES

DMCR

P0RES

P1RES

P2RES

BKLR

BMPC

P0ID

P1ID

P2ID

MODE

VIMSEL

VRES0

VRES1

VRES2

VRES3

VRES4

VRES5

VRES6

VRES7

VRES8

VRES9

VRES10

VRES11

VRES12

VRES13

VRES14

VRES15

VOMSEL

VRES16

VRES17

VRES18

VRES19

VRES20

VRES21

VRES22

VRES23

VRES24

VRES25

VRES26

VRES27

VRES28

VRES29

VRES30

VRES31

VIMEN

DISCN

DISCB

NDISCN

NDISCB

P0OQC

P0MVID

P0MVTAG

P0BL

P1OQC

P1MVID

P1MVTAG

P1BL

P2OQC

P2MVID

P2MVTAG

P2BL

VID

SCR

MCR

ISR

IMR

RDSR

TDSR

MRBR

RDAR

TDAR

EGMAP

INGMAP

INGSAL

INGSAH

LREC0

LREC1

LSR

INGDAL

INGDAH

EGSAL

EGSAH

EGDAL

EGDAH

MCVAL

PER

MMSR

LMT

LFC

PCSR

IOSR

QWT

P0BCT

FFEN

PSNP1

PSNP2

PSNP3

PSNP4

PSNP5

PSNP6

PSNP7

PSNP8

IPSNP1

IPSNP2

IPSNP3

IPSNP4

IPSNP5

IPSNP6

IPSNP7

IPSNP8


REV

Revision
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REV REV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORREV CSTREV

CORREV : no description available
bits : 0 - 15 (16 bit)
access : read-only

CSTREV : no description available
bits : 16 - 31 (16 bit)
access : read-only


VLANV

VLAN verify
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLANV VLANV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VV0 VV1 VV2 RESERVED DU0 DU1 DU2 RESERVED

VV0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frames are routed to the output port without VLAN domain checking

#1 : 1

A frame is accepted from the port as valid only when the input and output ports are members of the VLAN domain of the frame.

End of enumeration elements list.

VV1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frames are routed to the output port without VLAN domain checking

#1 : 1

A frame is accepted from the port as valid only when the input and output ports are members of the VLAN domain of the frame.

End of enumeration elements list.

VV2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frames are routed to the output port without VLAN domain checking

#1 : 1

A frame is accepted from the port as valid only when the input and output ports are members of the VLAN domain of the frame.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 15 (13 bit)
access : read-write

DU0 : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Received frames with unknown VLAN IDs are not discarded

#1 : 1

Received frames with an unknown VLAN ID or no VLAN tag are discarded and not forwarded (i.e. the default bcast is ignored)

End of enumeration elements list.

DU1 : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Received frames with unknown VLAN IDs are not discarded

#1 : 1

Received frames with an unknown VLAN ID or no VLAN tag are discarded and not forwarded (i.e. the default bcast is ignored)

End of enumeration elements list.

DU2 : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Received frames with unknown VLAN IDs are not discarded

#1 : 1

Received frames with an unknown VLAN ID or no VLAN tag are discarded and not forwarded (i.e. the default bcast is ignored)

End of enumeration elements list.

RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-write


P0VRES

Port 0 VLAN priority resolution map
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0VRES P0VRES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3 PRI4 PRI5 PRI6 PRI7 RESERVED

PRI0 : no description available
bits : 0 - 2 (3 bit)
access : read-write

PRI1 : no description available
bits : 3 - 5 (3 bit)
access : read-write

PRI2 : no description available
bits : 6 - 8 (3 bit)
access : read-write

PRI3 : no description available
bits : 9 - 11 (3 bit)
access : read-write

PRI4 : no description available
bits : 12 - 14 (3 bit)
access : read-write

PRI5 : no description available
bits : 15 - 17 (3 bit)
access : read-write

PRI6 : no description available
bits : 18 - 20 (3 bit)
access : read-write

PRI7 : no description available
bits : 21 - 23 (3 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write


P1VRES

Port 1 VLAN priority resolution map
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1VRES P1VRES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3 PRI4 PRI5 PRI6 PRI7 RESERVED

PRI0 : no description available
bits : 0 - 2 (3 bit)
access : read-write

PRI1 : no description available
bits : 3 - 5 (3 bit)
access : read-write

PRI2 : no description available
bits : 6 - 8 (3 bit)
access : read-write

PRI3 : no description available
bits : 9 - 11 (3 bit)
access : read-write

PRI4 : no description available
bits : 12 - 14 (3 bit)
access : read-write

PRI5 : no description available
bits : 15 - 17 (3 bit)
access : read-write

PRI6 : no description available
bits : 18 - 20 (3 bit)
access : read-write

PRI7 : no description available
bits : 21 - 23 (3 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write


P2VRES

Port 2 VLAN priority resolution map
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2VRES P2VRES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3 PRI4 PRI5 PRI6 PRI7 RESERVED

PRI0 : no description available
bits : 0 - 2 (3 bit)
access : read-write

PRI1 : no description available
bits : 3 - 5 (3 bit)
access : read-write

PRI2 : no description available
bits : 6 - 8 (3 bit)
access : read-write

PRI3 : no description available
bits : 9 - 11 (3 bit)
access : read-write

PRI4 : no description available
bits : 12 - 14 (3 bit)
access : read-write

PRI5 : no description available
bits : 15 - 17 (3 bit)
access : read-write

PRI6 : no description available
bits : 18 - 20 (3 bit)
access : read-write

PRI7 : no description available
bits : 21 - 23 (3 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write


DBCR

Default broadcast resolution
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCR DBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

A frame with the corresponding VLAN ID is not switched to that port

#1 : 1

Indicates that each port is a member of the VLAN and frames with the corresponding VLAN ID can be switched to the port

End of enumeration elements list.

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

A frame with the corresponding VLAN ID is not switched to that port

#1 : 1

Indicates that each port is a member of the VLAN and frames with the corresponding VLAN ID can be switched to the port

End of enumeration elements list.

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

A frame with the corresponding VLAN ID is not switched to that port

#1 : 1

Indicates that each port is a member of the VLAN and frames with the corresponding VLAN ID can be switched to the port

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-write


IPRES

IPv4/v6 priority resolution table
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRES IPRES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS IPV4SEL PRI0 PRI1 PRI2 RESERVED READ

ADDRESS : no description available
bits : 0 - 7 (8 bit)
access : read-write

IPV4SEL : no description available
bits : 8 - 8 (1 bit)
access : read-write

PRI0 : no description available
bits : 9 - 10 (2 bit)
access : read-write

PRI1 : no description available
bits : 11 - 12 (2 bit)
access : read-write

PRI2 : no description available
bits : 13 - 14 (2 bit)
access : read-write

RESERVED : no description available
bits : 15 - 30 (16 bit)
access : read-write

READ : no description available
bits : 31 - 31 (1 bit)
access : read-write


DMCR

Default multicast resolution
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMCR DMCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-write


P0RES

Port 0 priority resolution configuration
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0RES P0RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLAN IP MAC RESERVED DFLT_PRI RESERVED

VLAN : no description available
bits : 0 - 0 (1 bit)
access : read-write

IP : no description available
bits : 1 - 1 (1 bit)
access : read-write

MAC : no description available
bits : 2 - 2 (1 bit)
access : read-write

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-write

DFLT_PRI : no description available
bits : 4 - 6 (3 bit)
access : read-write

RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-write


P1RES

Port 1 priority resolution configuration
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1RES P1RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLAN IP MAC RESERVED DFLT_PRI RESERVED

VLAN : no description available
bits : 0 - 0 (1 bit)
access : read-write

IP : no description available
bits : 1 - 1 (1 bit)
access : read-write

MAC : no description available
bits : 2 - 2 (1 bit)
access : read-write

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-write

DFLT_PRI : no description available
bits : 4 - 6 (3 bit)
access : read-write

RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-write


P2RES

Port 2 priority resolution configuration
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2RES P2RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLAN IP MAC RESERVED DFLT_PRI RESERVED

VLAN : no description available
bits : 0 - 0 (1 bit)
access : read-write

IP : no description available
bits : 1 - 1 (1 bit)
access : read-write

MAC : no description available
bits : 2 - 2 (1 bit)
access : read-write

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-write

DFLT_PRI : no description available
bits : 4 - 6 (3 bit)
access : read-write

RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-write


BKLR

Blocking and learning enable
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BKLR BKLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BE0 BE1 BE2 RESERVED LD0 LD1 LD2 RESERVED

BE0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable.

#1 : 1

Enable. Only bridge protocol data units are accepted on that input, all other frames are discarded.

End of enumeration elements list.

BE1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable.

#1 : 1

Enable. Only bridge protocol data units are accepted on that input, all other frames are discarded.

End of enumeration elements list.

BE2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable.

#1 : 1

Enable. Only bridge protocol data units are accepted on that input, all other frames are discarded.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 15 (13 bit)
access : read-write

LD0 : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable.

#1 : 1

Disable. Only bridge protocol data unit frames are learned. Other frames are ignored for learning.

End of enumeration elements list.

LD1 : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable.

#1 : 1

Disable. Only bridge protocol data unit frames are learned. Other frames are ignored for learning.

End of enumeration elements list.

LD2 : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable.

#1 : 1

Disable. Only bridge protocol data unit frames are learned. Other frames are ignored for learning.

End of enumeration elements list.

RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-write


BMPC

Bridge management port configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BMPC BMPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT RESERVED MSGTX EN DIS RESERVED PRIORITY PORTMASK RESERVED

PORT : no description available
bits : 0 - 3 (4 bit)
access : read-write

RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-write

MSGTX : no description available
bits : 5 - 5 (1 bit)
access : read-write

EN : no description available
bits : 6 - 6 (1 bit)
access : read-write

DIS : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 12 (5 bit)
access : read-write

PRIORITY : no description available
bits : 13 - 15 (3 bit)
access : read-write

PORTMASK : no description available
bits : 16 - 18 (3 bit)
access : read-write

RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-write


P0ID

Port 0 VLAN ID
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0ID P0ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLANID RESERVED

VLANID : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


P1ID

Port 1 VLAN ID
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1ID P1ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLANID RESERVED

VLANID : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


P2ID

Port 2 VLAN ID
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2ID P2ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLANID RESERVED

VLANID : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


MODE

Mode configuration
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST SWEN RESERVED STOP CRCTRAN P0CT RESERVED STATRST

SWRST : no description available
bits : 0 - 0 (1 bit)
access : read-write

SWEN : no description available
bits : 1 - 1 (1 bit)
access : read-write

RESERVED : no description available
bits : 2 - 6 (5 bit)
access : read-write

STOP : no description available
bits : 7 - 7 (1 bit)
access : read-write

CRCTRAN : no description available
bits : 8 - 8 (1 bit)
access : read-write

P0CT : no description available
bits : 9 - 9 (1 bit)
access : read-write

RESERVED : no description available
bits : 10 - 30 (21 bit)
access : read-write

STATRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


VIMSEL

VLAN input manipulation select
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VIMSEL VIMSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 RESERVED

IM0 : no description available
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Mode 1, single tag passthrough

#01 : 01

Mode 2, single tag overwrite

#10 : 10

Mode 3, double tag passthrough

#11 : 11

Mode 4, double tag overwrite

End of enumeration elements list.

IM1 : no description available
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Mode 1, single tag passthrough

#01 : 01

Mode 2, single tag overwrite

#10 : 10

Mode 3, double tag passthrough

#11 : 11

Mode 4, double tag overwrite

End of enumeration elements list.

IM2 : no description available
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Mode 1, single tag passthrough

#01 : 01

Mode 2, single tag overwrite

#10 : 10

Mode 3, double tag passthrough

#11 : 11

Mode 4, double tag overwrite

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-write


VRES0

VLAN domain resolution entry 0
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES0 VRES0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES1

VLAN domain resolution entry 1
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES1 VRES1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES2

VLAN domain resolution entry 2
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES2 VRES2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES3

VLAN domain resolution entry 4
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES3 VRES3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES4

VLAN domain resolution entry 4
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES4 VRES4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES5

VLAN domain resolution entry 5
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES5 VRES5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES6

VLAN domain resolution entry 6
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES6 VRES6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES7

VLAN domain resolution entry 7
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES7 VRES7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES8

VLAN domain resolution entry 8
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES8 VRES8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES9

VLAN domain resolution entry 9
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES9 VRES9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES10

VLAN domain resolution entry 10
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES10 VRES10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES11

VLAN domain resolution entry 11
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES11 VRES11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES12

VLAN domain resolution entry 12
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES12 VRES12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES13

VLAN domain resolution entry 13
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES13 VRES13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES14

VLAN domain resolution entry 14
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES14 VRES14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES15

VLAN domain resolution entry 15
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES15 VRES15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VOMSEL

VLAN output manipulation select
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VOMSEL VOMSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OM0 OM1 OM2 RESERVED

OM0 : no description available
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

No output manipulation

#01 : 01

Mode 1, strip mode

#10 : 10

Mode 2, tag through

#11 : 11

Mode 3, transparent

End of enumeration elements list.

OM1 : no description available
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

No output manipulation

#01 : 01

Mode 1, strip mode

#10 : 10

Mode 2, tag through

#11 : 11

Mode 3, transparent

End of enumeration elements list.

OM2 : no description available
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

No output manipulation

#01 : 01

Mode 1, strip mode

#10 : 10

Mode 2, tag through

#11 : 11

Mode 3, transparent

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-write


VRES16

VLAN domain resolution entry 16
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES16 VRES16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES17

VLAN domain resolution entry 17
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES17 VRES17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES18

VLAN domain resolution entry 18
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES18 VRES18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES19

VLAN domain resolution entry 19
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES19 VRES19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES20

VLAN domain resolution entry 20
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES20 VRES20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES21

VLAN domain resolution entry 21
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES21 VRES21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES22

VLAN domain resolution entry 22
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES22 VRES22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES23

VLAN domain resolution entry 23
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES23 VRES23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES24

VLAN domain resolution entry 24
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES24 VRES24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES25

VLAN domain resolution entry 25
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES25 VRES25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES26

VLAN domain resolution entry 26
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES26 VRES26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES27

VLAN domain resolution entry 27
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES27 VRES27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES28

VLAN domain resolution entry 28
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES28 VRES28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES29

VLAN domain resolution entry 29
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES29 VRES29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES30

VLAN domain resolution entry 30
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES30 VRES30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VRES31

VLAN domain resolution entry 31
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VRES31 VRES31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0 P1 P2 VLANID RESERVED

P0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

P1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

P2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

VLANID : no description available
bits : 3 - 14 (12 bit)
access : read-write

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-write


VIMEN

VLAN input manipulation enable
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VIMEN VIMEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 RESERVED

EN0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. ESW_VIMSEL has no effect and the frames are processed unmodified.

#1 : 1

Enable

End of enumeration elements list.

EN1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. ESW_VIMSEL has no effect and the frames are processed unmodified.

#1 : 1

Enable

End of enumeration elements list.

EN2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. ESW_VIMSEL has no effect and the frames are processed unmodified.

#1 : 1

Enable

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-write


DISCN

Number of discarded frames
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DISCN DISCN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


DISCB

Bytes of discarded frames
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DISCB DISCB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


NDISCN

Number of non-discarded frames
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NDISCN NDISCN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


NDISCB

Bytes of non-discarded frames
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

NDISCB NDISCB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P0OQC

Port 0 output queue congestion
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P0OQC P0OQC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P0MVID

Port 0 mismatching VLAN ID
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P0MVID P0MVID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P0MVTAG

Port 0 missing VLAN tag
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P0MVTAG P0MVTAG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P0BL

Port 0 blocked
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P0BL P0BL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P1OQC

Port 1 output queue congestion
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P1OQC P1OQC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P1MVID

Port 1 mismatching VLAN ID
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P1MVID P1MVID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P1MVTAG

Port 1 missing VLAN tag
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P1MVTAG P1MVTAG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P1BL

Port 1 blocked
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P1BL P1BL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P2OQC

Port 2 output queue congestion
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P2OQC P2OQC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P2MVID

Port 2 mismatching VLAN ID
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P2MVID P2MVID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P2MVTAG

Port 2 missing VLAN tag
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P2MVTAG P2MVTAG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


P2BL

Port 2 blocked
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P2BL P2BL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-only


VID

VLAN tag ID
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VID VID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : no description available
bits : 0 - 31 (32 bit)
access : read-write


SCR

Scratch register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH

SCRATCH : no description available
bits : 0 - 31 (32 bit)
access : read-write


MCR

Mirror control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT MEN INGMAP EGMAP INGSA INGDA EGSA EGDA RESERVED

PORT : no description available
bits : 0 - 3 (4 bit)
access : read-write

MEN : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

INGMAP : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Ingress port map has no effect

#1 : 1

Ingress map is enabled. A frame received on an ingress port that has a bit set in the ingress map is mirrored.

End of enumeration elements list.

EGMAP : no description available
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Egress port map has no effect

#1 : 1

Egress map is enabled. A frame forwarded to an output port that has a bit set in the egress map is mirrored.

End of enumeration elements list.

INGSA : no description available
bits : 7 - 7 (1 bit)
access : read-write

INGDA : no description available
bits : 8 - 8 (1 bit)
access : read-write

EGSA : no description available
bits : 9 - 9 (1 bit)
access : read-write

EGDA : no description available
bits : 10 - 10 (1 bit)
access : read-write

RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-write


ISR

Interrupt status register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBERR RXB RXF TXB TXF QM OD0 OD1 OD2 LRN RESERVED

EBERR : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXB : no description available
bits : 1 - 1 (1 bit)
access : read-write

RXF : no description available
bits : 2 - 2 (1 bit)
access : read-write

TXB : no description available
bits : 3 - 3 (1 bit)
access : read-write

TXF : no description available
bits : 4 - 4 (1 bit)
access : read-write

QM : no description available
bits : 5 - 5 (1 bit)
access : read-write

OD0 : no description available
bits : 6 - 6 (1 bit)
access : read-write

OD1 : no description available
bits : 7 - 7 (1 bit)
access : read-write

OD2 : no description available
bits : 8 - 8 (1 bit)
access : read-write

LRN : no description available
bits : 9 - 9 (1 bit)
access : read-write

RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-write


IMR

Interrupt mask register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBERR RXB RXF TXB TXF QM OD0 OD1 OD2 LRN RESERVED

EBERR : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

RXB : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

RXF : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

TXB : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

TXF : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

QM : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

OD0 : no description available
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

OD1 : no description available
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

OD2 : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

LRN : no description available
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt source is masked

#1 : 1

The interrupt source is not masked and an interrupt can occur .

End of enumeration elements list.

RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-write


RDSR

Receive descriptor ring pointer
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDSR RDSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ADDRESS

RESERVED : no description available
bits : 0 - 1 (2 bit)
access : read-write

ADDRESS : no description available
bits : 2 - 31 (30 bit)
access : read-write


TDSR

Transmit descriptor ring pointer
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDSR TDSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ADDRESS

RESERVED : no description available
bits : 0 - 1 (2 bit)
access : read-write

ADDRESS : no description available
bits : 2 - 31 (30 bit)
access : read-write


MRBR

Maximum receive buffer size
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRBR MRBR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED SIZE RESERVED

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-write

SIZE : no description available
bits : 4 - 13 (10 bit)
access : read-write

RESERVED : no description available
bits : 14 - 31 (18 bit)
access : read-write


RDAR

Receive descriptor active
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RDAR RDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RDAR RESERVED

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-write

RDAR : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-write


TDAR

Transmit descriptor active
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDAR TDAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED TDAR RESERVED

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-write

TDAR : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-write


EGMAP

Egress port definitions
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EGMAP EGMAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EG0 EG1 EG2 RESERVED

EG0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enabled. Frames destined for this port are mirrored to the mirror port.

End of enumeration elements list.

EG1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enabled. Frames destined for this port are mirrored to the mirror port.

End of enumeration elements list.

EG2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enabled. Frames destined for this port are mirrored to the mirror port.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-write


INGMAP

Ingress port definitions
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INGMAP INGMAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ING0 ING1 ING2 RESERVED

ING0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enabled. Frames from this port are mirrored to the mirror port.

End of enumeration elements list.

ING1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enabled. Frames from this port are mirrored to the mirror port.

End of enumeration elements list.

ING2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enabled. Frames from this port are mirrored to the mirror port.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-write


INGSAL

Ingress source MAC address low
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INGSAL INGSAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDLOW

ADDLOW : no description available
bits : 0 - 31 (32 bit)
access : read-write


INGSAH

Ingress source MAC address high
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INGSAH INGSAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDHIGH RESERVED

ADDHIGH : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


LREC0

Learning records A0 and B1
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LREC0 LREC0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_ADDR0

MAC_ADDR0 : no description available
bits : 0 - 31 (32 bit)
access : read-only


LREC1

Learning record B1
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LREC1 LREC1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAC_ADDR1 HASH SWPORT RESERVED

MAC_ADDR1 : no description available
bits : 0 - 15 (16 bit)
access : read-only

HASH : no description available
bits : 16 - 23 (8 bit)
access : read-only

SWPORT : no description available
bits : 24 - 25 (2 bit)
access : read-only

RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only


LSR

Learning data available status
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LSR LSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA RESERVED

DA : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Learning record invalid

#1 : 1

Learning record valid

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only


INGDAL

Ingress destination MAC address low
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INGDAL INGDAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDLOW

ADDLOW : no description available
bits : 0 - 31 (32 bit)
access : read-write


INGDAH

Ingress destination MAC address high
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INGDAH INGDAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDHIGH RESERVED

ADDHIGH : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


EGSAL

Egress source MAC address low
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EGSAL EGSAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDLOW

ADDLOW : no description available
bits : 0 - 31 (32 bit)
access : read-write


EGSAH

Egress source MAC address high
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EGSAH EGSAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDHIGH RESERVED

ADDHIGH : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


EGDAL

Egress destination MAC address low
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EGDAL EGDAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDLOW

ADDLOW : no description available
bits : 0 - 31 (32 bit)
access : read-write


EGDAH

Egress destination MAC address high
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EGDAH EGDAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDHIGH RESERVED

ADDHIGH : no description available
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


MCVAL

Mirror count value
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCVAL MCVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT RESERVED

COUNT : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-write


PER

Port enable register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PER PER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TE0 TE1 TE2 RESERVED RE0 RE1 RE2 RESERVED

TE0 : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. All frames forwarded to the port are discarded.

#1 : 1

Enable. A frame can be forwarded to the port.

End of enumeration elements list.

TE1 : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. All frames forwarded to the port are discarded.

#1 : 1

Enable. A frame can be forwarded to the port.

End of enumeration elements list.

TE2 : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. All frames forwarded to the port are discarded.

#1 : 1

Enable. A frame can be forwarded to the port.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 15 (13 bit)
access : read-write

RE0 : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. The input is ignored and never selected for frame reception.

#1 : 1

Enable. The port is selected and a frame is accepted if it indicates data available.

End of enumeration elements list.

RE1 : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. The input is ignored and never selected for frame reception.

#1 : 1

Enable. The port is selected and a frame is accepted if it indicates data available.

End of enumeration elements list.

RE2 : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable. The input is ignored and never selected for frame reception.

#1 : 1

Enable. The port is selected and a frame is accepted if it indicates data available.

End of enumeration elements list.

RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-write


MMSR

Memory manager status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMSR MMSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY NOCELL MEMFULL MFLATCH RESERVED DQGRNT RESERVED CELLS_AVAIL RESERVED

BUSY : no description available
bits : 0 - 0 (1 bit)
access : read-write

NOCELL : no description available
bits : 1 - 1 (1 bit)
access : read-write

MEMFULL : no description available
bits : 2 - 2 (1 bit)
access : read-write

MFLATCH : no description available
bits : 3 - 3 (1 bit)
access : read-write

RESERVED : no description available
bits : 4 - 5 (2 bit)
access : read-write

DQGRNT : no description available
bits : 6 - 6 (1 bit)
access : read-write

RESERVED : no description available
bits : 7 - 15 (9 bit)
access : read-write

CELLS_AVAIL : no description available
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-write


LMT

Low memory threshold
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMT LMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THRESH RESERVED

THRESH : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-write


LFC

Lowest number of free cells
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LFC LFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : no description available
bits : 0 - 31 (32 bit)
access : read-write


PCSR

Port congestion status
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCSR PCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC0 PC1 PC2 RESERVED

PC0 : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not congested

#1 : 1

Congested

End of enumeration elements list.

PC1 : no description available
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not congested

#1 : 1

Congested

End of enumeration elements list.

PC2 : no description available
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not congested

#1 : 1

Congested

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 31 (29 bit)
access : read-only


IOSR

Switch input and output interface status
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IOSR IOSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OR0 OR1 OR2 RESERVED IR0 IR1 IR2 RESERVED

OR0 : no description available
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not ready

#1 : 1

Ready

End of enumeration elements list.

OR1 : no description available
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not ready

#1 : 1

Ready

End of enumeration elements list.

OR2 : no description available
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not ready

#1 : 1

Ready

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 15 (13 bit)
access : read-only

IR0 : no description available
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not available

#1 : 1

Data available

End of enumeration elements list.

IR1 : no description available
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not available

#1 : 1

Data available

End of enumeration elements list.

IR2 : no description available
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

#0 : 0

Not available

#1 : 1

Data available

End of enumeration elements list.

RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-only


QWT

Queue weights
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QWT QWT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Q0WT RESERVED Q1WT RESERVED Q2WT RESERVED Q3WT RESERVED

Q0WT : no description available
bits : 0 - 4 (5 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-write

Q1WT : no description available
bits : 8 - 12 (5 bit)
access : read-write

RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-write

Q2WT : no description available
bits : 16 - 20 (5 bit)
access : read-write

RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-write

Q3WT : no description available
bits : 24 - 28 (5 bit)
access : read-write

RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-write


P0BCT

Port 0 Backpressure Congestion Threshold
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0BCT P0BCT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THRESH RESERVED

THRESH : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-write


FFEN

Port 0 forced forwarding enable
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FFEN FFEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEN RESERVED FD RESERVED

FEN : no description available
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-write

FD : no description available
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

Do not forward. Frame is processed normally.

#01 : 01

Forward to port 1 only

#10 : 10

Forward to port 2 only

#11 : 11

Forward to both ports

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-write


PSNP1

Port snooping registers
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP1 PSNP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP2

Port snooping registers
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP2 PSNP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP3

Port snooping registers
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP3 PSNP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP4

Port snooping registers
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP4 PSNP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP5

Port snooping registers
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP5 PSNP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP6

Port snooping registers
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP6 PSNP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP7

Port snooping registers
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP7 PSNP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


PSNP8

Port snooping registers
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSNP8 PSNP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE CD CS RESERVED PORT_COMPARE

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

CD : no description available
bits : 3 - 3 (1 bit)
access : read-write

CS : no description available
bits : 4 - 4 (1 bit)
access : read-write

RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-write

PORT_COMPARE : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP1

IP snooping registers
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP1 IPSNP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP2

IP snooping registers
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP2 IPSNP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP3

IP snooping registers
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP3 IPSNP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP4

IP snooping registers
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP4 IPSNP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP5

IP snooping registers
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP5 IPSNP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP6

IP snooping registers
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP6 IPSNP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP7

IP snooping registers
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP7 IPSNP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write


IPSNP8

IP snooping registers
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPSNP8 IPSNP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MODE RESERVED PROTOCOL RESERVED

EN : no description available
bits : 0 - 0 (1 bit)
access : read-write

MODE : no description available
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

Forward frame to designated management port only

#01 : 01

Copy to management port and forward normally

#10 : 10

Discard

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-write

PROTOCOL : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-write



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