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RLE_DEC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCR

SR

ISR

RIER

SPCR

EPCR

ICR

CISR

DICR


MCR

Module Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDIS RESERVED TXFFEN GRLE_EN RESERVED TX_FIFO_THRESHOLD RX_FIFO_THRESHOLD

MDIS : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable RLE_DEC clocks.

#1 : 1

Allow external logic to disable RLE_DEC clocks.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

TXFFEN : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger the DMA action only when TxFIFO has more data than TX_FIFO_THRESHOLD.

#1 : 1

Trigger the DMA action until the Tx FIFO is empty even if it is less than TX_FIFO_THRESHOLD.

End of enumeration elements list.

GRLE_EN : Enable Gradient RLE decoding
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the Gradient RLE decoding. Decoding is performed only as traditional RLE.

#1 : 1

Enables the Gradient RLE decoding. Decoding can be done according to either Gradient RLE or traditional RLE algorithm, based on the decoding of Command Byte.

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only

TX_FIFO_THRESHOLD : no description available
bits : 16 - 23 (8 bit)
access : read-write

RX_FIFO_THRESHOLD : no description available
bits : 24 - 31 (8 bit)
access : read-write


SR

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFILL RXFREE RESERVED

TXFILL : no description available
bits : 0 - 7 (8 bit)
access : read-write

RXFREE : no description available
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


ISR

Interrupt Request Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEIF RXEIF TXFIF RXFIF TXUIF RXUIF TXDIF RXDIF RESERVED

TXEIF : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXEIF : no description available
bits : 1 - 1 (1 bit)
access : read-write

TXFIF : no description available
bits : 2 - 2 (1 bit)
access : read-write

RXFIF : no description available
bits : 3 - 3 (1 bit)
access : read-write

TXUIF : no description available
bits : 4 - 4 (1 bit)
access : read-write

RXUIF : no description available
bits : 5 - 5 (1 bit)
access : read-write

TXDIF : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXDIF : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


RIER

Interrupt Request Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIER RIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEIE RXEIE TXFIE RXFIE TXUIE RXUIE TXDIE RXDIE RESERVED

TXEIE : no description available
bits : 0 - 0 (1 bit)
access : read-write

RXEIE : no description available
bits : 1 - 1 (1 bit)
access : read-write

TXFIE : no description available
bits : 2 - 2 (1 bit)
access : read-write

RXFIE : no description available
bits : 3 - 3 (1 bit)
access : read-write

TXUIE : no description available
bits : 4 - 4 (1 bit)
access : read-write

RXUIE : no description available
bits : 5 - 5 (1 bit)
access : read-write

TXDIE : no description available
bits : 6 - 6 (1 bit)
access : read-write

RXDIE : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


SPCR

Start Pixel Co-ordinate Register of Image
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPCR SPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y X

Y : no description available
bits : 0 - 15 (16 bit)
access : read-write

X : no description available
bits : 16 - 31 (16 bit)
access : read-write


EPCR

End Pixel Co-ordinate Register of Image
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCR EPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y X

Y : no description available
bits : 0 - 15 (16 bit)
access : read-write

X : no description available
bits : 16 - 31 (16 bit)
access : read-write


ICR

Image Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICR ICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WIDTH RESERVED RESERVED

WIDTH : no description available
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Pixel Width is 08-bits;

#01 : 01

Pixel Width is 16-bits;

#10 : 10

Pixel Width is 24-bits;

#11 : 11

Pixel Width is 32-bits.

End of enumeration elements list.

RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only

RESERVED : no description available
bits : 4 - 31 (28 bit)
access : read-only


CISR

Compressed Image Size Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CISR CISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE

SIZE : no description available
bits : 0 - 31 (32 bit)
access : read-write


DICR

Decompressed Image Co-ordinates register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DICR DICR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y X

Y : no description available
bits : 0 - 15 (16 bit)
access : read-write

X : no description available
bits : 16 - 31 (16 bit)
access : read-write



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