\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
SIRC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIRC_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
Enable SIRC
#0 : 0
Disable SIRC
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
SIRC_EN_ON_FAIL : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#1 : 1
If Power Fails and xtal32 is not available, enable SIRC
#0 : 0
If Power Fails and xtal32 is not available. Disable SIRC
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
SIRC_DIV : no description available
bits : 8 - 14 (7 bit)
access : read-write
Reseved : no description available
bits : 15 - 31 (17 bit)
access : read-only
SOSC Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOSC_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable oscillator 32 KHz XOSC
#1 : 1
Enable oscillator 32 KHz XOSC
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only
RESERVED : no description available
bits : 5 - 15 (11 bit)
access : read-only
RESERVED : no description available
bits : 16 - 30 (15 bit)
access : read-only
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-write
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