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SPDIF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCR

SIS

SIC

SRL

SRR

SRCSH

SRCSL

SRU

SRQ

STL

STR

STCSCH

STCSCL

SRCD

SRFM

STC

SRPC

SIE


SCR

SPDIF Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USrc_Sel TxSel ValCtrl RESERVED DMA_TX_En DMA_Rx_En TxFIFO_Ctrl Soft_Reset Low_Power RESERVED TxFIFOEmpty_Sel TxAutoSync RxAutoSync RxFIFOFull_Sel RxFIFO_Rst RxFIFO_En RxFIFO_Ctrl RESERVED

USrc_Sel : Defines the source of U Channel.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

No embedded U channel

#01 : 01

U channel from SPDIF receive block (CD mode)

#10 : 10

Reserved

#11 : 11

U channel from on chip transmitter

End of enumeration elements list.

TxSel : Transmit channel select
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

#000 : 000

Off and output 0

#001 : 001

Feed-through SPDIFIN

#101 : 101

Tx Normal operation

End of enumeration elements list.

ValCtrl : Defines the validity control of data.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Outgoing Validity always set

#1 : 1

Outgoing Validity always clear

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

DMA_TX_En : no description available
bits : 8 - 8 (1 bit)
access : read-write

DMA_Rx_En : no description available
bits : 9 - 9 (1 bit)
access : read-write

TxFIFO_Ctrl : Controls the Transmit operation from the Tx FIFO
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 00

Send out digital zero on SPDIF Tx

#01 : 01

Tx Normal operation

#10 : 10

Reset to 1 sample remaining

#11 : 11

Reserved

End of enumeration elements list.

Soft_Reset : no description available
bits : 12 - 12 (1 bit)
access : read-write

Low_Power : no description available
bits : 13 - 13 (1 bit)
access : read-write

RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only

TxFIFOEmpty_Sel : Defines the threshold for generation of empty interrupt
bits : 15 - 16 (2 bit)
access : read-write

Enumeration:

#00 : 00

Empty interrupt if 0 sample in Tx left and right FIFOs

#01 : 01

Empty interrupt if at most 4 sample in Tx left and right FIFOs

#10 : 10

Empty interrupt if at most 8 sample in Tx left and right FIFOs

#11 : 11

Empty interrupt if at most 12 sample in Tx left and right FIFOs

End of enumeration elements list.

TxAutoSync : Controls automatic synchronization of FIFO's. If enabled will check if the left and right Tx FIFOs are in sync.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tx FIFO auto sync off

#1 : 1

Tx FIFO auto sync on

End of enumeration elements list.

RxAutoSync : Controls automatic synchronization of FIFO's. If enabled will check if the left and right Rx FIFOs are in sync.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Rx FIFO auto sync off

#1 : 1

RxFIFO auto sync on

End of enumeration elements list.

RxFIFOFull_Sel : Defines the threshold for generation of FIFO Full interrupt
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

#00 : 00

Full interrupt if at least 1 sample in Rx left and right FIFOs

#01 : 01

Full interrupt if at least 4 sample in Rx left and right FIFOs

#10 : 10

Full interrupt if at least 8 sample in Rx left and right FIFOs

#11 : 11

Full interrupt if at least 16 sample in Rx left and right FIFO

End of enumeration elements list.

RxFIFO_Rst : Defines the reset state of RxFIFO
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Reset register to 1 sample remaining

End of enumeration elements list.

RxFIFO_En : Enables/Disables FIFO accepting data from the interface
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPDIF Rx FIFO is on

#1 : 1

SPDIF Rx FIFO is off. Does not accept data from interface

End of enumeration elements list.

RxFIFO_Ctrl : Controls the values read from Rx data Register
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Always read zero from Rx data register

End of enumeration elements list.

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SIS

InterruptStat Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : SPDIF
reset_Mask : 0x0

SIS SIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFIFOFul TxFIFOEmpty LockLoss RxFIFOResyn RxFIFOUnOv UQErr UQSync QRxOv RESERVED URxOv RESERVED BitErr SymErr ValNoGood CNew TxResyn TxUnOv Lock RESERVED

RxFIFOFul : Rx FIFO full flag
bits : 0 - 0 (1 bit)
access : read-only

TxFIFOEmpty : Tx FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only

LockLoss : no description available
bits : 2 - 2 (1 bit)
access : read-only

RxFIFOResyn : no description available
bits : 3 - 3 (1 bit)
access : read-only

RxFIFOUnOv : no description available
bits : 4 - 4 (1 bit)
access : read-only

UQErr : no description available
bits : 5 - 5 (1 bit)
access : read-only

UQSync : no description available
bits : 6 - 6 (1 bit)
access : read-only

QRxOv : no description available
bits : 7 - 7 (1 bit)
access : read-only

RESERVED : no description available
bits : 8 - 8 (1 bit)
access : read-only

URxOv : no description available
bits : 9 - 9 (1 bit)
access : read-only

RESERVED : no description available
bits : 10 - 13 (4 bit)
access : read-only

BitErr : no description available
bits : 14 - 14 (1 bit)
access : read-only

SymErr : no description available
bits : 15 - 15 (1 bit)
access : read-only

ValNoGood : no description available
bits : 16 - 16 (1 bit)
access : read-only

CNew : no description available
bits : 17 - 17 (1 bit)
access : read-only

TxResyn : no description available
bits : 18 - 18 (1 bit)
access : read-only

TxUnOv : no description available
bits : 19 - 19 (1 bit)
access : read-only

Lock : no description available
bits : 20 - 20 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 21 - 31 (11 bit)
access : read-only


SIC

InterruptClear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : SPDIF
reset_Mask : 0x0

SIC SIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED LockLoss RxFIFOResyn RxFIFOUnOv UQErr UQSync QRxOv RESERVED URxOv RESERVED BitErr SymErr ValNoGood CNew TxResyn TxUnOv Lock RESERVED

RESERVED : no description available
bits : 0 - 1 (2 bit)
access : read-only

LockLoss : no description available
bits : 2 - 2 (1 bit)
access : write-only

RxFIFOResyn : no description available
bits : 3 - 3 (1 bit)
access : write-only

RxFIFOUnOv : no description available
bits : 4 - 4 (1 bit)
access : write-only

UQErr : no description available
bits : 5 - 5 (1 bit)
access : write-only

UQSync : no description available
bits : 6 - 6 (1 bit)
access : write-only

QRxOv : no description available
bits : 7 - 7 (1 bit)
access : write-only

RESERVED : no description available
bits : 8 - 8 (1 bit)
access : read-only

URxOv : no description available
bits : 9 - 9 (1 bit)
access : write-only

RESERVED : no description available
bits : 10 - 13 (4 bit)
access : read-only

BitErr : no description available
bits : 14 - 14 (1 bit)
access : write-only

SymErr : no description available
bits : 15 - 15 (1 bit)
access : write-only

ValNoGood : no description available
bits : 16 - 16 (1 bit)
access : write-only

CNew : no description available
bits : 17 - 17 (1 bit)
access : write-only

TxResyn : no description available
bits : 18 - 18 (1 bit)
access : write-only

TxUnOv : no description available
bits : 19 - 19 (1 bit)
access : write-only

Lock : no description available
bits : 20 - 20 (1 bit)
access : write-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 21 - 31 (11 bit)
access : read-only


SRL

SPDIFRxLeft Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRL SRL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxDataLeft RESERVED

RxDataLeft : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRR

SPDIFRxRight Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRR SRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxDataRight RESERVED

RxDataRight : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRCSH

SPDIFRxCChannel_h Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRCSH SRCSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxCChannel_h RESERVED

RxCChannel_h : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRCSL

SPDIFRxCChannel_l Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRCSL SRCSL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxCChannel_l RESERVED

RxCChannel_l : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRU

UchannelRx Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRU SRU read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxUChannel RESERVED

RxUChannel : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


SRQ

QchannelRx Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRQ SRQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxQChannel RESERVED

RxQChannel : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


STL

SPDIFTxLeft Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STL STL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDataLeft RESERVED

TxDataLeft : no description available
bits : 0 - 23 (24 bit)
access : write-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


STR

SPDIFTxRight Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STR STR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxDataRight RESERVED

TxDataRight : no description available
bits : 0 - 23 (24 bit)
access : write-only

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


STCSCH

SPDIFTxCChannelCons_h Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCSCH STCSCH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCChannelCons_h RESERVED

TxCChannelCons_h : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


STCSCL

SPDIFTxCChannelCons_l Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCSCL STCSCL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxCChannelCons_l RESERVED

TxCChannelCons_l : no description available
bits : 0 - 23 (24 bit)
access : read-write

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRCD

CDText Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCD SRCD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED USyncMode RESERVED RESERVED RESERVED RESERVED RESERVED

RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only

USyncMode : Defines the Mode for User channel reception (CD and non CD)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-CD data

#1 : 1

CD user channel subcode

End of enumeration elements list.

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

RESERVED : no description available
bits : 8 - 14 (7 bit)
access : read-only

RESERVED : no description available
bits : 15 - 23 (9 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRFM

FreqMeas Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRFM SRFM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FreqMeas RESERVED

FreqMeas : no description available
bits : 0 - 23 (24 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


STC

SPDIFTxClk Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STC STC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TxClk_DF tx_all_clk_en TxClk_Source SYSCLK_DF RESERVED RESERVED

TxClk_DF : no description available
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

#0 : 0

divider factor is 1

#1 : 1

divider factor is 2

End of enumeration elements list.

tx_all_clk_en : no description available
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

disable transfer clock.

#1 : 1

enable transfer clock.

End of enumeration elements list.

TxClk_Source : Defines the transmit clock source
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

SPDIF EXTAL (EXTAL_CLK from PAD 79 ALT mode 5)

#001 : 001

PLL4 DIV CLK

#010 : 010

AUDIO EXTAL (AUD_EXT_CLK from PAD3 ALT2/PAD5 ALT2 /PAD40 ALT2)

#011 : 011

MLB CLK IN (MLB CLOCK from PAD1 ALT7/PAD54 ALT6)

#100 : 100

ESAI HCKT (ESAI High speed Transmitter Clock from PAD78 ALT3)

#101 : 101

SYS CLK (SPDIF BUS CLOCK)

#110 : 110

SAI0 TX BCLK (SAI0TX_BLCK Clock PAD93 ALT1)

#111 : 111

SAI3 TX BCLK (SAI3 TX_BCLK clock PAD16 ALT2)

End of enumeration elements list.

SYSCLK_DF : no description available
bits : 11 - 19 (9 bit)
access : read-write

Enumeration:

#0 : 0

no clock signal

#1 : 1

divider factor is 2

End of enumeration elements list.

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SRPC

PhaseConfig Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRPC SRPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED GainSel LOCK ClkSrc_Sel RESERVED RESERVED

RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only

GainSel : no description available
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 000

24*2**10

#001 : 001

16*2**10

#010 : 010

12*2**10

#011 : 011

8*2**10

#100 : 100

6*2**10

#101 : 101

4*2**10

#110 : 110

3*2**10

End of enumeration elements list.

LOCK : no description available
bits : 6 - 6 (1 bit)
access : read-only

ClkSrc_Sel : no description available
bits : 7 - 10 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

if (DPLL Locked) SPDIF_RxClk else extal_clk

#0001 : 0001

if (DPLL Locked) SPDIF_RxClk else pll4_div_clk

#0010 : 0010

if (DPLL Locked) SPDIF_RxClk else External audio clock input

#0011 : 0011

if (DPLL Locked) SPDIF_RxClk else mlb_clk

#0100 : 0100

if (DPLL Locked) SPDIF_Rxclk else esai_hckt

#0101 : 0101

extal_clk

#0110 : 0110

pll4_div_clk

#0111 : 0111

external audio clok

#1000 : 1000

mlb_clk

#1001 : 1001

esai_hckt

#1010 : 1010

if (DPLL Locked) SPDIF_RxClk else SAI0_TXBCLK

#1011 : 1011

if (DPLL Locked) SPDIF_RxClk else SAI3_TXBCLK

#1100 : 1100

sai0_txbclk

#1101 : 1101

sai3_txbclk

End of enumeration elements list.

RESERVED : no description available
bits : 11 - 23 (13 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only


SIE

InterruptEn Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIE SIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFIFOFul TxEm LockLoss RxFIFOResyn RxFIFOUnOv UQErr UQSync QRxOv QRxFul URxOv URxFul RESERVED BitErr SymErr ValNoGood CNew TxResyn TxUnOv Lock RESERVED RESERVED RESERVED

RxFIFOFul : no description available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

TxEm : no description available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

LockLoss : no description available
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

RxFIFOResyn : no description available
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

RxFIFOUnOv : no description available
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

UQErr : no description available
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

UQSync : no description available
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

QRxOv : no description available
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

QRxFul : no description available
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

URxOv : no description available
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

URxFul : no description available
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

RESERVED : no description available
bits : 11 - 13 (3 bit)
access : read-only

BitErr : no description available
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt disabled

End of enumeration elements list.

SymErr : no description available
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

ValNoGood : no description available
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

CNew : no description available
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

TxResyn : no description available
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

TxUnOv : no description available
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

Lock : no description available
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt disabled

#1 : 1

Interrupt enabled

End of enumeration elements list.

RESERVED : no description available
bits : 21 - 22 (2 bit)
access : read-only

RESERVED : no description available
bits : 23 - 23 (1 bit)
access : read-only

RESERVED : This is a 24-bit register the upper byte is unimplemented.
bits : 24 - 31 (8 bit)
access : read-only



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