Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x7 byte (0x0)
mem_usage : registers
protection : not protected
I2C Bus Address Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only
ADR : no description available
bits : 1 - 7 (7 bit)
access : read-write
I2C Bus Frequency Divider Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBC : no description available
bits : 0 - 7 (8 bit)
access : read-write
I2C Bus Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only
DMAEN : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the DMA TX/RX request signals
#1 : 1
Enable the DMA TX/RX request signals
End of enumeration elements list.
RSTA : no description available
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate repeat start cycle
End of enumeration elements list.
NOACK : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data
#1 : 1
No acknowledge signal response is sent (i.e., acknowledge bit = 1)
End of enumeration elements list.
TXRX : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive
#1 : 1
Transmit
End of enumeration elements list.
MSSL : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave Mode
#1 : 1
Master Mode
End of enumeration elements list.
IBIE : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from the I2C Bus module are disabled. This does not clear any currently pending interrupt condition.
#1 : 1
Interrupts from the I2C Bus module are enabled. An I2C Bus interrupt occurs provided the IBIF bit in the status register is also set.
End of enumeration elements list.
MDIS : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The I2C Bus module is enabled. This bit must be cleared before any other IBCR bits have any effect
#1 : 1
The module is reset and disabled. This is the power-on reset situation. When high, the interface is held in reset, but registers can still be accessed. Status register bits (IBSR) are not valid when module is disabled.
End of enumeration elements list.
I2C Bus Status Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXAK : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Acknowledge received
#1 : 1
No acknowledge received
End of enumeration elements list.
IBIF : no description available
bits : 1 - 1 (1 bit)
access : read-write
SRW : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slave receive, master writing to slave
#1 : 1
Slave transmit, master reading from slave
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
IBAL : no description available
bits : 4 - 4 (1 bit)
access : read-write
IBB : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Bus is Idle
#1 : 1
Bus is busy
End of enumeration elements list.
IAAS : no description available
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not addressed
#1 : 1
Addressed as a slave
End of enumeration elements list.
TCF : no description available
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transfer in progress
#1 : 1
Transfer complete
End of enumeration elements list.
I2C Bus Data I/O Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : no description available
bits : 0 - 7 (8 bit)
access : read-write
I2C Bus Interrupt Config Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only
RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only
RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
RESERVED : no description available
bits : 4 - 6 (3 bit)
access : read-only
BIIE : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus Idle Interrupts disabled
#1 : 1
Bus Idle Interrupts enabled
End of enumeration elements list.
I2C Bus Debug Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPG_DEBUG_EN : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation, Bus Idle Interrupts disabled
#1 : 1
IP is in debug mode
End of enumeration elements list.
IPG_DEBUG_HALTED : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
IP is still executing a transaction
#1 : 1
IP has entered the debug mode
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 7 (6 bit)
access : read-only
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