\n
address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection : not protected
CCM Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCNT : no description available
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#00000000 : 00000000
count 1 cycle of 32 KHz SXOSC clock
#11111111 : 11111111
count 256 cycles of 32 KHz SXOSC clock
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 11 (4 bit)
access : read-only
FXOSC_EN : no description available
bits : 12 - 12 (1 bit)
access : read-write
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
FIRC_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable on-chip RC oscillator
#1 : 1
Enable on-chip RC oscillator
End of enumeration elements list.
RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only
CCM Serial Clock Multiplexer Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI0_CLK_SEL : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Audio external clock
#01 : 01
MLB CLK
#10 : 10
SPDIF RX clock
#11 : 11
Divided PLL4 main clock, defined by CCM_CACRR[PLL4_CLK_DIV]
End of enumeration elements list.
SAI1_CLK_SEL : no description available
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Audio external clock
#01 : 01
MLB CLK
#10 : 10
SPDIF RX clock
#11 : 11
Divided PLL4 main clock, defined by CCM_CACRR[PLL4_CLK_DIV]
End of enumeration elements list.
SAI2_CLK_SEL : no description available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Audio external clock
#01 : 01
MLB CLK
#10 : 10
SPDIF RX Clk
#11 : 11
Divided PLL4 Main clock, defined by CCM_CACRR[PLL4_CLK_DIV]
End of enumeration elements list.
SAI3_CLK_SEL : no description available
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Audio external clock
#01 : 01
MLB CLK
#10 : 10
SPDIF RX clock
#11 : 11
Divided PLL4 main clock, defined by CCM_CACRR[PLL4_CLK_DIV]
End of enumeration elements list.
VADC_CLK_SEL : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divided PLL6 main clock, defined by CCM_CACRR[PLL6_CLK_DIV]
#01 : 01
Divided PLL3 main clock, defined by CCM_CACRR[PLL3_CLK_DIV]
#10 : 10
PLL3 main clock
#11 : 11
Reserved
End of enumeration elements list.
RESERVED : no description available
bits : 10 - 11 (2 bit)
access : read-only
NFC_CLK_SEL : no description available
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
Platform bus clock
#01 : 01
PLL1 PFD1 clock
#10 : 10
PLL3 PFD1 clock
#11 : 11
PLL3 PFD3 clock
End of enumeration elements list.
GPU_CLK_SEL : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 PFD2 clock
#1 : 1
PLL3 PFD2 clock
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
ESDHC0_CLK_SEL : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
PLL3 main clock (default)
#01 : 01
PLL3 PFD3
#10 : 10
PLL1 PFD3
#11 : 11
Platform bus clock
End of enumeration elements list.
ESDHC1_CLK_SEL : no description available
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
PLL3 main clock (default)
#01 : 01
PLL3 PFD3
#10 : 10
PLL1 PFD3
#11 : 11
Platform bus clock
End of enumeration elements list.
ESAI_CLK_SEL : no description available
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Audio External clock
#01 : 01
MLB CLK
#10 : 10
SPDIF RX Clk
#11 : 11
Divided PLL4 main clock, defined by CCM_CACRR[PLL4_CLK_DIV]
End of enumeration elements list.
QSPI0_CLK_SEL : no description available
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
PLL3 main clock
#01 : 01
PLL3 PFD4
#10 : 10
PLL2 PFD4
#11 : 11
PLL1 PFD4
End of enumeration elements list.
QSPI1_CLK_SEL : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
PLL3 main clock
#01 : 01
PLL3 PFD4
#10 : 10
PLL2 PFD4
#11 : 11
PLL1 PFD4
End of enumeration elements list.
RESERVED : no description available
bits : 26 - 27 (2 bit)
access : read-only
DCU0_CLK_SEL : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL1 PFD2 Clk
#1 : 1
PLL3 MAIN Clk
End of enumeration elements list.
DCU1_CLK_SEL : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL1 PFD2 clock
#1 : 1
PLL3 MAIN clock
End of enumeration elements list.
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Platform Clock Gating Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPCG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
PPCG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
PPCG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
PPCG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
PPCG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
PPCG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
PPCG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
PPCG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
PPCG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
PPCG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
PPCG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
PPCG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
PPCG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
PPCG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
PPCG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
PPCG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Serial Clock Divider Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAI0_DIV : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
SAI1_DIV : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
SAI2_DIV : no description available
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
SAI3_DIV : no description available
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
SAI0_EN : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SAI0 clock
#1 : 1
Enable SAI0 clock
End of enumeration elements list.
SAI1_EN : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SAI1 clock
#1 : 1
Enable SAI1 clock
End of enumeration elements list.
SAI2_EN : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SAI2 clock
#1 : 1
Enable SAI2 clock
End of enumeration elements list.
SAI3_EN : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SAI3 clock
#1 : 1
Enable SAI3 clock
End of enumeration elements list.
VADC_DIV : no description available
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide by 1
#01 : 01
Divide by 2
#10 : 10
Divide by 3
#11 : 11
Divide by 4
End of enumeration elements list.
VADC_EN : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Video ADC clock
#1 : 1
Enable Video ADC clock
End of enumeration elements list.
ENET_TS_EN : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ENET TS clock
#1 : 1
Enable ENET TS clock
End of enumeration elements list.
RMII_CLK_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ENET RMII clock
#1 : 1
Enable ENET RMII clock
End of enumeration elements list.
FTM0_CLK_EN : FTM 0 clock enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0 clock disabled
#1 : 1
FTM1 clock enabled
End of enumeration elements list.
FTM1_CLK_EN : FTM1 clock enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1 clock disabled
#1 : 1
FTM1 clock enabled
End of enumeration elements list.
FTM2_CLK_EN : FTM2 clock enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2 clock disabled
#1 : 1
FTM2 clock enabled
End of enumeration elements list.
FTM3_CLK_EN : FTM3 clock enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM clock disabled
#1 : 1
FTM3 clock enabled
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only
CCM Module Enable Override Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MO0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MO1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MO2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MO3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MO4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MO5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MO6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MO7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MO8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MO9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MO10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MO11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
MO12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MO13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
MO14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MO15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MO16 : no description available
bits : 16 - 16 (1 bit)
access : read-write
MO17 : no description available
bits : 17 - 17 (1 bit)
access : read-write
MO18 : no description available
bits : 18 - 18 (1 bit)
access : read-write
MO19 : no description available
bits : 19 - 19 (1 bit)
access : read-write
MO20 : no description available
bits : 20 - 20 (1 bit)
access : read-write
MO21 : no description available
bits : 21 - 21 (1 bit)
access : read-write
MO22 : no description available
bits : 22 - 22 (1 bit)
access : read-write
MO23 : no description available
bits : 23 - 23 (1 bit)
access : read-write
MO24 : no description available
bits : 24 - 24 (1 bit)
access : read-write
MO25 : no description available
bits : 25 - 25 (1 bit)
access : read-write
MO26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
MO27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
MO28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
MO29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
MO30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
MO31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
CCM Clock Gating Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Serial Clock Divider Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only
NFC_FRAC_DIV : no description available
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 8 (1 bit)
access : read-only
NFC_EN : no description available
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable NFC clock
#1 : 1
Enable NFC clock
End of enumeration elements list.
GPU_EN : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable GPU clock
#1 : 1
Enable GPU clock
End of enumeration elements list.
CAN0_EN : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CAN0 clock
#1 : 1
Enable CAN0 clock
End of enumeration elements list.
CAN1_EN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CAN1 clock
#1 : 1
Enable CAN1 clock
End of enumeration elements list.
NFC_FRAC_DIV_EN : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
NFC_FRAC_DIV divider acts as integer divider
#1 : 1
Fractional 0.5 divider enabled (in addition to FRAC_DIV). Example: When NFC_FRAC_DIV = 1 and NFC_FRAC_DIV_EN =0 the division value is 1. When NFC_FRAC_DIV = 1 and NFC_FRAC_DIV_EN =1 the division value = 1.5.
End of enumeration elements list.
NFC_CLK_INV : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Phase of NFC clock > 50%
#1 : 1
High Phase of NFC clock > 50%
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
ESDHC0_DIV : no description available
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
ESDHC1_DIV : no description available
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
ESAI_DIV : no description available
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#1111 : 1111
Divide by 16
End of enumeration elements list.
ESDHC0_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ESDHC1 clock
#1 : 1
Enable ESDHC1 clock
End of enumeration elements list.
ESDHC1_EN : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ESDHC2 clock
#1 : 1
Enable ESDHC2 clock
End of enumeration elements list.
ESAI_EN : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ESAI clock
#1 : 1
Enable ESAI clock
End of enumeration elements list.
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Platform Clock Gating Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPCG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
PPCG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
PPCG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
PPCG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
PPCG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
PPCG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
PPCG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
PPCG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
PPCG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
PPCG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
PPCG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
PPCG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
PPCG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
PPCG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
PPCG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
PPCG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Serial Clock Divider Register 3
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPI0_X4_DIV : no description available
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide by 1
#01 : 01
Divide by 2
#10 : 10
Divide by 3
#11 : 11
Divide by 4
End of enumeration elements list.
QSPI0_X2_DIV : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2
End of enumeration elements list.
QSPI0_DIV : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2
End of enumeration elements list.
QSPI0_EN : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable QSPI0 clock
#1 : 1
Enable QSPI0 clock
End of enumeration elements list.
RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only
QSPI1_X4_DIV : no description available
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide by 1
#01 : 01
Divide by 2
#10 : 10
Divide by 3
#11 : 11
Divide by 4
End of enumeration elements list.
QSPI1_X2_DIV : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2
End of enumeration elements list.
QSPI1_DIV : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2
End of enumeration elements list.
QSPI1_EN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable QSPI1 clock
#1 : 1
Enable QSPI1 clock
End of enumeration elements list.
NFC_PRE_DIV : NFC Pre-divider. The divider is used to provide divided clock to the fractional divider.
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 3
#011 : 011
Divide by 4
#100 : 100
Divide by 5
#101 : 101
Divide by 6
#110 : 110
Divide by 7
#111 : 111
Divide by 8
End of enumeration elements list.
DCU0_DIV : no description available
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#111 : 111
Divide by 8
End of enumeration elements list.
DCU0_EN : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DCU0 clock
#1 : 1
Enable DCU0 clock
End of enumeration elements list.
DCU1_DIV : no description available
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#111 : 111
Divide by 8
End of enumeration elements list.
DCU1_EN : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DCU1 clock
#1 : 1
Enable DCU1 clock
End of enumeration elements list.
TRACE_DIV : no description available
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide by 1
#01 : 01
Divide by 2
#10 : 10
Divide by 3
#11 : 11
Divide by 4
End of enumeration elements list.
TRACE_EN : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Trace clock
#1 : 1
Enable Trace clock
End of enumeration elements list.
SWO_DIV : no description available
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1
#1 : 1
Divide by 2
End of enumeration elements list.
SWO_EN : no description available
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SWO clock
#1 : 1
Enable SWO clock
End of enumeration elements list.
RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only
CCM Module Enable Override Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MO0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MO1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MO2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MO3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MO4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MO5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MO6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MO7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MO8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MO9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MO10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MO11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
MO12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MO13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
MO14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MO15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MO16 : no description available
bits : 16 - 16 (1 bit)
access : read-write
MO17 : no description available
bits : 17 - 17 (1 bit)
access : read-write
MO18 : no description available
bits : 18 - 18 (1 bit)
access : read-write
MO19 : no description available
bits : 19 - 19 (1 bit)
access : read-write
MO20 : no description available
bits : 20 - 20 (1 bit)
access : read-write
MO21 : no description available
bits : 21 - 21 (1 bit)
access : read-write
MO22 : no description available
bits : 22 - 22 (1 bit)
access : read-write
MO23 : no description available
bits : 23 - 23 (1 bit)
access : read-write
MO24 : no description available
bits : 24 - 24 (1 bit)
access : read-write
MO25 : no description available
bits : 25 - 25 (1 bit)
access : read-write
MO26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
MO27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
MO28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
MO29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
MO30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
MO31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
CCM Clock Gating Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Serial Clock Multiplexer Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENET_TS_CLK_SEL : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
ENET RMII clock
#001 : 001
24 MHz FXOSC clock
#010 : 010
Audio external clock
#011 : 011
USB clock (60 MHz)
#100 : 100
ENET time stamping clock
#101 : 101
PLL5 main clock divided by 2
#110 : 110
PLL5 main clock
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
RMII_CLK_SEL : no description available
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
ENET RMII clock
#01 : 01
Audio external clock
#10 : 10
PLL5 main clock
#11 : 11
Divided by 2 of PLL5 main clock
End of enumeration elements list.
FTM0_EXT_CLK_SEL : FTM0 External clock select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
128 kHz IRC clock
#01 : 01
32 KHz FXOSC clock
#10 : 10
12 MHz - 24 MHz FXOSC divided by 2
#11 : 11
Audio external clock
End of enumeration elements list.
FTM1_EXT_CLK_SEL : FTM1 external clock select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
128 kHz IRC clock
#01 : 01
32 KHz FXOSC clock
#10 : 10
12 MHz - 24 MHz FXOSC divided by 2
#11 : 11
Audio external clock
End of enumeration elements list.
FTM2_EXT_CLK_SEL : FTM2 external clock select
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
128 kHz IRC clock
#01 : 01
32 KHz FXOSC clock
#10 : 10
12 MHz - 24 MHz FXOSC divided by 2
#11 : 11
Audio external clock
End of enumeration elements list.
FTM3_EXT_CLK_SEL : FTM3 external clock select
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
128 kHz IRC clock
#01 : 01
32 KHz FXOSC clock
#10 : 10
12 MHz - 24 MHz FXOSC divided by 2
#11 : 11
Audio External clock
End of enumeration elements list.
FTM0_FIX_CLK_SEL : FTM0 fixed clock select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 KHz FXOSC clock
#1 : 1
128 kHz IRC clock
End of enumeration elements list.
FTM1_FIX_CLK_SEL : FTM1 fixed clock select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 KHz FXOSC clock
#1 : 1
128 kHz IRC clock
End of enumeration elements list.
FTM2_FIX_CLK_SEL : FTM2 fixed clock select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 KHz FXOSC clock
#1 : 1
128 kHz IRC clock
End of enumeration elements list.
FTM3_FIX_CLK_SEL : FTM3 fixed clock select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 KHz FXOSC clock
#1 : 1
128 kHz IRC clock
End of enumeration elements list.
TRACE_CLK_SEL : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Platform Bus clock
#1 : 1
PLL3 Main clock
End of enumeration elements list.
SWO_CLK_SEL : no description available
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
24 MHz IRC clock
#1 : 1
IPS Bus clock
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 31 (12 bit)
access : read-only
CCM Module Enable Override Register
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MO0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MO1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MO2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MO3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MO4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MO5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MO6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MO7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MO8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MO9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MO10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MO11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
MO12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MO13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
MO14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MO15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MO16 : no description available
bits : 16 - 16 (1 bit)
access : read-write
MO17 : no description available
bits : 17 - 17 (1 bit)
access : read-write
MO18 : no description available
bits : 18 - 18 (1 bit)
access : read-write
MO19 : no description available
bits : 19 - 19 (1 bit)
access : read-write
MO20 : no description available
bits : 20 - 20 (1 bit)
access : read-write
MO21 : no description available
bits : 21 - 21 (1 bit)
access : read-write
MO22 : no description available
bits : 22 - 22 (1 bit)
access : read-write
MO23 : no description available
bits : 23 - 23 (1 bit)
access : read-write
MO24 : no description available
bits : 24 - 24 (1 bit)
access : read-write
MO25 : no description available
bits : 25 - 25 (1 bit)
access : read-write
MO26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
MO27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
MO28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
MO29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
MO30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
MO31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
CCM Platform Clock Gating Register
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPCG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
PPCG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
PPCG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
PPCG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
PPCG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
PPCG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
PPCG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
PPCG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
PPCG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
PPCG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
PPCG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
PPCG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
PPCG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
PPCG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
PPCG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
PPCG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Gating Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Testing Observability Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OBS_OUTPUT_0_SEL : no description available
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Low power mode exit
#00001 : 00001
Clock ignition indicator
#00010 : 00010
PLL3 PFD1 disable
#00011 : 00011
PLL2 PFD1 disable
#00100 : 00100
PLL1 PFD4 disable
#00101 : 00101
PLL1 PFD1 disable
#00110 : 00110
PLL4 Lock ready flag
#00111 : 00111
PLL1 Lock ready flag
#01000 : 01000
Isolation enable
#01001 : 01001
IPS debug enable
#01010 : 01010
Memory repair mode
#01011 : 01011
Low power mode FSM state [2]
#01100 : 01100
Fuse latch/read indicator
#01101 : 01101
low power handshake FSM state[2]
#01110 : 01110
Deep sleep mode wakeup signal
#01111 : 01111
Debug power-up request
#10000 : 10000
FXOSC enable
#10001 : 10001
FUSE bits for core
#10010 : 10010
Wait mode indicator
#10011 : 10011
Stop mode indicator
#10100 : 10100
Camp disable
#10101 : 10101
Core Cortex-A5 clock gating enable
#10110 : 10110
CAN0 Clock Sel
#10111 : 10111
CAMP1 Lock ready Flag
#11000 : 11000
CORE DSM request [3]
#11001 : 11001
CORE Clock enable
#11010 : 11010
AHB clock Syncronizer
End of enumeration elements list.
OBS_OUTPUT_1_SEL : no description available
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Powerdown intiation indicator
#00001 : 00001
Reset input
#00010 : 00010
PLL3 PFD2 disable
#00011 : 00011
PLL2 PFD2 disable
#00100 : 00100
PLL2 PFD4 disable
#00101 : 00101
PLL1 PFD2 disable
#00110 : 00110
PLL5 Lock ready flag
#00111 : 00111
PLL2 Lock ready flag
#01000 : 01000
Tied to Zero
#01001 : 01001
IPS debug enable
#01010 : 01010
Tied to Zero
#01011 : 01011
Low power mode FSM state [1]
#01100 : 01100
Sampled Low power mode input [1]
#01101 : 01101
low power handshake FSM state[1]
#01110 : 01110
GPC Low power mode input
#01111 : 01111
DAP power-up Ack
#10000 : 10000
FIRX enable
#10001 : 10001
Core Fuse [0]
#10010 : 10010
PLL Ref enable
#10011 : 10011
Stop mode indicator
#10100 : 10100
System reset
#10101 : 10101
Core Cortex-M4 clock gating enable
#10110 : 10110
CAN 1 clock select
#10111 : 10111
CAMP2 lock ready flag
#11000 : 11000
Core DSM request [2]
#11001 : 11001
clock gating mode
#11010 : 11010
IPS clock synchronizer
End of enumeration elements list.
OBS_OUTPUT_2_SEL : no description available
bits : 10 - 14 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Core clock configuration in low power mode
#00001 : 00001
Reset clock enable
#00010 : 00010
PLL3 PFD3 disable
#00011 : 00011
PLL2 PFD3 disable
#00100 : 00100
PLL3 PFD4 disable
#00101 : 00101
PLL1 PFD3 disable
#00110 : 00110
PLL6 lock ready flag
#00111 : 00111
PLL3 lock ready flag
#01000 : 01000
Tied to Zero
#01001 : 01001
Well Bias control
#01010 : 01010
Tied to Zero
#01011 : 01011
Low power mode FSM state [0]
#01100 : 01100
Sampled Low power mode input [0]
#01101 : 01101
low power handshake FSM state[0]
#01110 : 01110
Low power mode request
#01111 : 01111
Platform powerup request
#10000 : 10000
FXOSC power down
#10001 : 10001
Core Fuse
#10010 : 10010
PLL enable
#10011 : 10011
IPS wait request
#10100 : 10100
Anatop Reg bypass
#10101 : 10101
Core DSM request [0]
#10110 : 10110
Tied to Zero
#10111 : 10111
CAMP1 disable
#11000 : 11000
Core DSM request[1]
#11001 : 11001
Core clock stop
#11010 : 11010
GPC clock synchronizer
End of enumeration elements list.
OBS_EN : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Observability mux disabled.
#1 : 1
Observability mux enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Low Power Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only
RESERVED : no description available
bits : 3 - 4 (2 bit)
access : read-only
ARM_CLK_LPM : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
ARM clock enabled on wait mode.
#1 : 1
ARM clock disabled on wait mode.
End of enumeration elements list.
SBYOS : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
On-chip oscillator will not be powered down, after next entrance to stop mode.
#1 : 1
On-chip oscillator will be powered down, after next entrance to stop mode.
End of enumeration elements list.
DIS_REF_OSC : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high frequency oscillator will be enabled, i.e. ref_en_b = '0'.(default)
#1 : 1
External high frequency oscillator will be disabled, i.e. ref_en_b = '1'
End of enumeration elements list.
ANADIG_STOP_MODE : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop Mode indication is masked to Anatop
#1 : 1
Stop Mode indication is sent to Anatop
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only
FXOSC_BYPSEN : 24 Mhz Oscillator bypass enable signal.
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
24 Mhz oscillator is not bypassed
#1 : 1
24 Mhz oscillator is bypassed by external oscillator
End of enumeration elements list.
FXOSC_PWRDWN : no description available
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
On-chip oscillator will not be powered down
#1 : 1
On-chip oscillator will be powered down
End of enumeration elements list.
FXOSC_BYPSS : Bypass status of 24 MHz oscillator
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
24 Mhz oscialltor not bypassed
#1 : 1
24 Mhz oscillator bypassed by external oscillator
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 18 (6 bit)
access : read-only
RESERVED : no description available
bits : 19 - 19 (1 bit)
access : read-write
RESERVED : no description available
bits : 20 - 21 (2 bit)
access : read-only
M_CORE0_WFI : no description available
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
WFI of core0 is not masked
#1 : 1
WFI of core0 is masked
End of enumeration elements list.
M_CORE1_WFI : no description available
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#1 : 1
WFI of core1 is masked
#0 : 0
WFI of core1 is not masked
End of enumeration elements list.
M_SCU_IDLE : no description available
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SCU IDLE is not masked
#1 : 1
SCU IDLE is masked
End of enumeration elements list.
M_L2CC_IDLE : no description available
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
L2CC IDLE is not masked
#1 : 1
L2CC IDLE is masked
End of enumeration elements list.
RESERVED : no description available
bits : 26 - 31 (6 bit)
access : read-only
CCM Module Enable Override Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MO0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MO1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MO2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MO3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MO4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MO5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MO6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MO7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MO8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MO9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MO10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MO11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
MO12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MO13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
MO14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MO15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MO16 : no description available
bits : 16 - 16 (1 bit)
access : read-write
MO17 : no description available
bits : 17 - 17 (1 bit)
access : read-write
MO18 : no description available
bits : 18 - 18 (1 bit)
access : read-write
MO19 : no description available
bits : 19 - 19 (1 bit)
access : read-write
MO20 : no description available
bits : 20 - 20 (1 bit)
access : read-write
MO21 : no description available
bits : 21 - 21 (1 bit)
access : read-write
MO22 : no description available
bits : 22 - 22 (1 bit)
access : read-write
MO23 : no description available
bits : 23 - 23 (1 bit)
access : read-write
MO24 : no description available
bits : 24 - 24 (1 bit)
access : read-write
MO25 : no description available
bits : 25 - 25 (1 bit)
access : read-write
MO26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
MO27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
MO28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
MO29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
MO30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
MO31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
CCM Platform Clock Gating Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PPCG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
PPCG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
PPCG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
PPCG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
PPCG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
PPCG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
PPCG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
PPCG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
PPCG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
PPCG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
PPCG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
PPCG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
PPCG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
PPCG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
PPCG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
PPCG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LRF_PLL1 : Lock ready flag status of the PLL1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock ready flag of PLL1 generates no interrupt
#1 : 1
Lock ready flag of PLL1 generates interrupt
End of enumeration elements list.
LRF_PLL2 : Lock ready flag status of the PLL2
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock ready flag of PLL2 generates no interrupt
#1 : 1
Lock ready flag of PLL2 generates interrupt
End of enumeration elements list.
LRF_PLL3 : Lock ready flag status of the PLL3
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock ready flag of PLL3 generates no interrupt
#1 : 1
Lock ready flag of PLL3 generates interrupt
End of enumeration elements list.
LRF_PLL4 : Lock ready flag status of the PLL4
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock ready flag of PLL4 generates no interrupt
#1 : 1
Lock ready flag of PLL4 generates interrupt
End of enumeration elements list.
LRF_PLL5 : Lock ready flag status of the PLL5
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock ready flag of PLL5 generates no interrupt
#1 : 1
Lock ready flag of PLL5 generates interrupt
End of enumeration elements list.
LRF_PLL6 : Lock ready flag status of the PLL6
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock ready flag of PLL6 generates no interrupt
#1 : 1
Lock ready flag of PLL6 generates interrupt
End of enumeration elements list.
FXOSC_RDY : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
On bard oscillatory is not ready
#1 : 1
On bard oscillatory is ready
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Interrupt Mask Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M_LRF_PLL1 : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt is masked
End of enumeration elements list.
M_LRF_PLL2 : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt is masked
End of enumeration elements list.
M_LRF_PLL3 : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt is masked
End of enumeration elements list.
M_LRF_PLL4 : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt is masked
End of enumeration elements list.
M_LRF_PLL5 : no description available
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt in masked
End of enumeration elements list.
M_LRF_PLL6 : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt is masked
End of enumeration elements list.
M_FXOSC_READY : no description available
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is not masked
#1 : 1
Interrupt is masked
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-only
CCM Module Enable Override Register
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MO0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MO1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MO2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MO3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MO4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MO5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MO6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MO7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MO8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MO9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MO10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MO11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
MO12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MO13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
MO14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MO15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MO16 : no description available
bits : 16 - 16 (1 bit)
access : read-write
MO17 : no description available
bits : 17 - 17 (1 bit)
access : read-write
MO18 : no description available
bits : 18 - 18 (1 bit)
access : read-write
MO19 : no description available
bits : 19 - 19 (1 bit)
access : read-write
MO20 : no description available
bits : 20 - 20 (1 bit)
access : read-write
MO21 : no description available
bits : 21 - 21 (1 bit)
access : read-write
MO22 : no description available
bits : 22 - 22 (1 bit)
access : read-write
MO23 : no description available
bits : 23 - 23 (1 bit)
access : read-write
MO24 : no description available
bits : 24 - 24 (1 bit)
access : read-write
MO25 : no description available
bits : 25 - 25 (1 bit)
access : read-write
MO26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
MO27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
MO28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
MO29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
MO30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
MO31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
CCM Clock Gating Register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Output Source Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKO1_SEL : no description available
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
QSPI 0 Serial clk
#000001 : 000001
QSPI 0 Serial clk -inverted
#000010 : 000010
PLL6 Main clock
#000011 : 000011
PLL6 Main Clock divided by 2
#000100 : 000100
PLL5 Main Clock
#000101 : 000101
PLL5 divided Clock
#000110 : 000110
PLL4 Main clock
#000111 : 000111
PLL4 Divided Clock
#001000 : 001000
PLL3 PFD 4 clock
#001001 : 001001
PLL3 PFD 3 clock
#001010 : 001010
PLL3 PFD 2 clock
#001011 : 001011
PLL3 PFD 1 clock
#001100 : 001100
PLL3 Main clock
#001101 : 001101
PLL3 Div clock
#001110 : 001110
PLL2 PFD 4 clock
#001111 : 001111
PLL2 PFD 3 clock
#010000 : 010000
PLL2 PFD 2 clock
#010001 : 010001
PLL2 PFD 1 clock
#010010 : 010010
PLL2 Main clock
#010011 : 010011
PLL1 PFD 4 clock
#010100 : 010100
PLL1 PFD 3 clock
#010101 : 010101
PLL1 PFD 2 clock
#010110 : 010110
PLL1 PFD 1 clock
#010111 : 010111
PLL1 Main clock
#011000 : 011000
nfc_clk_root
#011001 : 011001
MLB Clock
#011010 : 011010
Test Clock 0
#011011 : 011011
IPS Bus clock
#011100 : 011100
ENET Time Sampling clock
#011101 : 011101
GPUx2 clock
#011110 : 011110
GPC clock
#011111 : 011111
FTM3 Fix clock
#100000 : 100000
FTM3 External clock
#100001 : 100001
FTM2 Fix clock
#100010 : 100010
FTM2 External clock
#100011 : 100011
FTM1 Fix clock
#100100 : 100100
FTM1 External clock
#100101 : 100101
FTM0 Fix clock
#100110 : 100110
FTM0 External clock
#100111 : 100111
FXOSC Divided by 2 clock
#101000 : 101000
FXOSC clock
#101001 : 101001
FIRC clock
#101010 : 101010
ESDHC1 clock
#101011 : 101011
ESDHC0 clock
#101100 : 101100
ESAI clock
#101101 : 101101
ENET External clock (scan muxed)
#101110 : 101110
ENET TS input clock
#101111 : 101111
ENET RMII clock
#110000 : 110000
ENET External clock
#110001 : 110001
Scan clock
#110010 : 110010
TCLK
#110011 : 110011
DRAMC clock
#110100 : 110100
DCU1 pixel clock
#110101 : 110101
DCU0 pixel clock
#110110 : 110110
DAP clock
#110111 : 110111
Cortex-M4 core clock
#111000 : 111000
32 KHz Clock
#111001 : 111001
24Mhz clock
#111010 : 111010
Clock Igniton clock
#111011 : 111011
CAN1 clock
#111100 : 111100
CAN0 clock
#111101 : 111101
Cortex-A5 core clock
#111110 : 111110
Platform Bus clock
#111111 : 111111
Audio external clock
End of enumeration elements list.
CKO1_DIV : no description available
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1(default)
#0001 : 0001
Divide by 2
#0010 : 0010
Divide by 3
#0011 : 0011
Divide by 4
#0100 : 0100
Divide by 5
#0101 : 0101
Divide by 6
#0110 : 0110
Divide by 7
#0111 : 0111
Divide by 8
#1000 : 1000
Divide by 9
#1001 : 1001
Divide by 10
#1010 : 1010
Divide by 11
#1011 : 1011
Divide by 12
#1100 : 1100
Divide by 13
#1101 : 1101
Divide by 14
#1110 : 1110
Divide by 15
#1111 : 1111
Divide by 16
End of enumeration elements list.
CKO1_EN : no description available
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
CKO1 disabled.
#1 : 1
CKO1 enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 15 (5 bit)
access : read-only
CKO2_SEL : no description available
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
#000000 : 000000
Memory repair clock
#000001 : 000001
Video ADC divided by 2 clock
#000010 : 000010
Video ADC clock
#000011 : 000011
USB clock
#000100 : 000100
Trace clock
#000101 : 000101
SWO clock
#000110 : 000110
SPDIF recieve clock
#000111 : 000111
SPDIF clock
#001000 : 001000
SXOSC clock (synchronised at IPS Bus clock)
#001001 : 001001
SXOSC clock
#001010 : 001010
sirc_ipg_sync_clk
#001011 : 001011
SIRC clock (synchronised at IPS Bus clock)
#001100 : 001100
SAI3 clock
#001101 : 001101
SAI2 clock
#001110 : 001110
SAI1 clock
#001111 : 001111
SAI0 clock
#010000 : 010000
QSPI1 Serial x4 clock
#010001 : 010001
QSPI1 Serial x2 clock
#010010 : 010010
QSPI1 Serial clock
#010011 : 010011
Inverted QSPI1Serial clock
#010100 : 010100
QSPI0 Serial x4 clock
#010101 : 010101
QSPI0 Serial x2 clock
#010110 : 010110
PLL6 Main clock
#010111 : 010111
PLL6 Divided by 2 clock
#011000 : 011000
PLL5 Main clock
#011001 : 011001
PLL5 Divided clock
#011010 : 011010
PLL4 Main clock
#011011 : 011011
PLL4 Divided clock
#011100 : 011100
PLL3 PFD4 clock
#011101 : 011101
PLL3 PFD3 clock
#011110 : 011110
PLL3 PFD2 clock
#011111 : 011111
PLL3 PFD1 clock
#100000 : 100000
PLL3 Main clock
#100001 : 100001
PLL3 divided clock
#100010 : 100010
PLL2 PFD4 clock
#100011 : 100011
PLL2 PFD3 clock
#100100 : 100100
PLL2 PFD2 clock
#100101 : 100101
PLL2 PFD1 clock
#100110 : 100110
PLL2 Main clock
#100111 : 100111
PLL1 PFD4 clock
#101000 : 101000
PLL1 PFD3 clock
#101001 : 101001
PLL1 PFD2 clock
#101010 : 101010
PLL1 PFD1 clock
#101011 : 101011
PLL1 Main clock
End of enumeration elements list.
CKO2_DIV : no description available
bits : 22 - 25 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1(Default)
#0001 : 0001
Divide by 2
#0010 : 0010
Divide by 3
#0011 : 0011
Divide by 4
#0100 : 0100
Divide by 5
#0101 : 0101
Divide by 6
#0110 : 0110
Divide by 7
#0111 : 0111
Divide by 8
#1000 : 1000
Divide by 9
#1001 : 1001
Divide by 10
#1010 : 1010
Divide by 11
#1011 : 1011
Divide by 12
#1100 : 1100
Divide by 13
#1101 : 1101
Divide by 14
#1110 : 1110
Divide by 15
#1111 : 1111
Divide by 16
End of enumeration elements list.
CKO2_EN : no description available
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
CKO2 disabled.
#1 : 1
CKO2 enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 27 - 31 (5 bit)
access : read-only
CCM General Purpose Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FS_ENABLE : MLB 1024xFs enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
1024xFs MLB is disabled
#1 : 1
1024xFs is enabled
End of enumeration elements list.
QSPIn_ACCZ : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source to QSPIn depends on CCM_CSCMR1[QSPIn_CLK_SEL]
#1 : 1
QSPIn clock source is platform bus clock
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only
RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-write
RESERVED : no description available
bits : 1 - 3 (3 bit)
access : read-only
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only
FXOSC_RDY : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
On board oscillator is not ready.
#1 : 1
On board oscillator is ready.
End of enumeration elements list.
RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Clock Switcher Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYS_CLK_SEL : System clock select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Fast clock o/p defined by CCM_CCSR[FAST_CLK_SEL]
#001 : 001
Slow clock o/p defined by CCM_CCSR[SLOW_CLK_SEL]
#010 : 010
PLL2 PFD o/p clock defined by CCM_CCSR[PLL2_PFD_CLK_SEL]
#011 : 011
PLL2 main clock
#100 : 100
PLL1 PFD o/p clock defined by CCM_CCSR[PLL1_PFD_CLK_SEL]
#101 : 101
PLL3 main clock
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-write
SLOW_CLK_SEL : Slow clock select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 KHz divided 128 kHz IRC clock
#1 : 1
32 KHz FXOSC clock
End of enumeration elements list.
FAST_CLK_SEL : Fast clock select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
24 MHz IRC clock
#1 : 1
24 MHz FXOSC clock
End of enumeration elements list.
DDRC_CLK_SEL : DDRC clock select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 PFD2 clk
#1 : 1
SYS_DIV_OUT_CLK
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
PLL1_PFD1_EN : Enable for PLL1 PFD1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL1 PFD1 (will override the CCM internally generated enables)
#1 : 1
Enable PLL1 PFD1 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL1_PFD2_EN : Enable for PLL1 PFD2
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL1 PFD2 (will override the CCM internally generated enables)
#1 : 1
Enable PLL1 PFD2 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL1_PFD3_EN : Enable for PLL1 PFD3
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL1 PFD3 (will override the CCM internally generated enables)
#1 : 1
Enable PLL1 PFD3 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL1_PFD4_EN : Enable for PLL1 PFD4
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL1 PFD4 (will override the CCM internally generated enables)
#1 : 1
Enable PLL1 PFD4 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL2_PFD1_EN : Enable for PLL2 PFD1
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL2 PFD1 (will override the CCM internally generated enables)
#1 : 1
Enable PLL2 PFD1 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL2_PFD2_EN : Enable for PLL2 PFD2
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL2 PFD2 (will override the CCM internally generated enables)
#1 : 1
Enable PLL2 PFD2 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL2_PFD3_EN : Enable for PLL2 PFD3
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL2 PFD3 (will override the CCM internally generated enables)
#1 : 1
Enable PLL2 PFD3 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL2_PFD4_EN : Enable for PLL2 PFD4
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL2 PFD4 (will override the CCM internally generated enables)
#1 : 1
Enable PLL2 PFD4 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL1_PFD_CLK_SEL : PLL1 PFD clock select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
PLL1 main clock
#001 : 001
PLL1 PFD1 clock
#010 : 010
PLL1 PFD2 clock
#011 : 011
PLL1 PFD3 clock
#100 : 100
PLL1 PFD4 clock
End of enumeration elements list.
PLL2_PFD_CLK_SEL : PLL2 PFD clock select
bits : 19 - 21 (3 bit)
access : read-write
Enumeration:
#000 : 000
PLL2 main clock
#001 : 001
PLL2 PFD1 clock
#010 : 010
PLL2 PFD2 clock
#011 : 011
PLL2 PFD3 clock
#100 : 100
PLL2 PFD4 clock
End of enumeration elements list.
RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only
DAP_EN : Enable for Debug Access port clock
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Debug Access Port clock
#1 : 1
Enable Debug Access Port clock, an acknowledgement is sent to Debug Access port once the clock is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 25 - 27 (3 bit)
access : read-only
PLL3_PFD1_EN : Enable for PLL3 PFD1
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL3 PFD1 (will override the CCM internally generated enables)
#1 : 1
Enable PLL3 PFD1 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL3_PFD2_EN : Enable for PLL3 PFD2
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL3 PFD2 (will override the CCM internally generated enables)
#1 : 1
Enable PLL3 PFD2 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL3_PFD3_EN : Enable for PLL3 PFD3
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PL3 PFD3 (will override the CCM internally generated enables)
#1 : 1
Enable PLL3 PFD3 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
PLL3_PFD4_EN : Enable for PLL3 PFD4
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PLL3 PFD4 (will override the CCM internally generated enables)
#1 : 1
Enable PLL3 PFD4 (PLL PFD may still be disabled, if not used by CCM)
End of enumeration elements list.
CCM Clock Gating Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM PLL PFD Disable Status Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PLL1_PFD1 : no description available
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabledPFD output is disabled
End of enumeration elements list.
PLL1_PFD2 : no description available
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabledPFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL1_PFD3 : no description available
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL1_PFD4 : no description available
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL2_PFD1 : no description available
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL2_PFD2 : no description available
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL2_PFD3 : no description available
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL2_PFD4 : no description available
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL3_PFD1 : no description available
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL3_PFD2 : no description available
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL3_PFD3 : no description available
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
PLL3_PFD4 : no description available
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
PFD output is enabled
#1 : 1
PFD output is disabled
End of enumeration elements list.
RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only
CCM CORE Wakeup Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUP_KEY : no description available
bits : 0 - 15 (16 bit)
access : write-only
AUX_CORE_WKUP : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Secondary core clock is gated
#1 : 1
Secondary core clock is enabled
End of enumeration elements list.
RESERVED : no description available
bits : 17 - 31 (15 bit)
access : read-only
CCM ARM Clock Root Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARM_CLK_DIV : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1(default)
#001 : 001
Divide by 2
#010 : 010
Divide by 3
#011 : 011
Divide by 4
#100 : 100
Divide by 5
#101 : 101
Divide by 6
#110 : 110
Divide by 7
#111 : 111
Divide by 8
End of enumeration elements list.
BUS_CLK_DIV : no description available
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 3
#011 : 011
Divide by 4
#100 : 100
Divide by 5
#101 : 101
Divide by 6
#110 : 110
Divide by 7
#111 : 111
Divide by 8
End of enumeration elements list.
PLL4_CLK_DIV : no description available
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1 (only if PLL frequency less than or equal to 650 MHz)
#001 : 001
Divide by 4
#010 : 010
Divide by 6
#011 : 011
Divide by 8
#100 : 100
Divide by 10
#101 : 101
Divide by 12
#110 : 110
Divide by 14
#111 : 111
Divide by 16
End of enumeration elements list.
RESERVED : no description available
bits : 9 - 10 (2 bit)
access : read-only
IPG_CLK_DIV : no description available
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide by 1
#01 : 01
Divide by 2
#10 : 10
Divide by 3
#11 : 11
Divide by 4
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 15 (3 bit)
access : read-only
PLL1_PFD_CLK_DIV : no description available
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide by 1 (default)
#01 : 01
Divide by 2
#10 : 10
Divide by 3
#11 : 11
Divide by 4
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 19 (2 bit)
access : read-only
PLL3_CLK_DIV : no description available
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1 (default)
#1 : 1
Divide by 2
End of enumeration elements list.
PLL6_CLK_DIV : no description available
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divide by 1 (used only if PLL is less than or equal to 650 MHz)
#1 : 1
Divide by 2
End of enumeration elements list.
FLEX_CLK_DIV : no description available
bits : 22 - 24 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 3
#011 : 011
Divide by 4
#100 : 100
Divide by 5
#101 : 101
Divide by 6
#110 : 110
Divide by 7
#111 : 111
Divide by 8
End of enumeration elements list.
RESERVED : no description available
bits : 25 - 31 (7 bit)
access : read-only
CCM Clock Gating Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CG0 : no description available
bits : 0 - 1 (2 bit)
access : read-write
CG1 : no description available
bits : 2 - 3 (2 bit)
access : read-write
CG2 : no description available
bits : 4 - 5 (2 bit)
access : read-write
CG3 : no description available
bits : 6 - 7 (2 bit)
access : read-write
CG4 : no description available
bits : 8 - 9 (2 bit)
access : read-write
CG5 : no description available
bits : 10 - 11 (2 bit)
access : read-write
CG6 : no description available
bits : 12 - 13 (2 bit)
access : read-write
CG7 : no description available
bits : 14 - 15 (2 bit)
access : read-write
CG8 : no description available
bits : 16 - 17 (2 bit)
access : read-write
CG9 : no description available
bits : 18 - 19 (2 bit)
access : read-write
CG10 : no description available
bits : 20 - 21 (2 bit)
access : read-write
CG11 : no description available
bits : 22 - 23 (2 bit)
access : read-write
CG12 : no description available
bits : 24 - 25 (2 bit)
access : read-write
CG13 : no description available
bits : 26 - 27 (2 bit)
access : read-write
CG14 : no description available
bits : 28 - 29 (2 bit)
access : read-write
CG15 : no description available
bits : 30 - 31 (2 bit)
access : read-write
CCM Module Enable Override Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MO0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
MO1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
MO2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
MO3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
MO4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
MO5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
MO6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
MO7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
MO8 : no description available
bits : 8 - 8 (1 bit)
access : read-write
MO9 : no description available
bits : 9 - 9 (1 bit)
access : read-write
MO10 : no description available
bits : 10 - 10 (1 bit)
access : read-write
MO11 : no description available
bits : 11 - 11 (1 bit)
access : read-write
MO12 : no description available
bits : 12 - 12 (1 bit)
access : read-write
MO13 : no description available
bits : 13 - 13 (1 bit)
access : read-write
MO14 : no description available
bits : 14 - 14 (1 bit)
access : read-write
MO15 : no description available
bits : 15 - 15 (1 bit)
access : read-write
MO16 : no description available
bits : 16 - 16 (1 bit)
access : read-write
MO17 : no description available
bits : 17 - 17 (1 bit)
access : read-write
MO18 : no description available
bits : 18 - 18 (1 bit)
access : read-write
MO19 : no description available
bits : 19 - 19 (1 bit)
access : read-write
MO20 : no description available
bits : 20 - 20 (1 bit)
access : read-write
MO21 : no description available
bits : 21 - 21 (1 bit)
access : read-write
MO22 : no description available
bits : 22 - 22 (1 bit)
access : read-write
MO23 : no description available
bits : 23 - 23 (1 bit)
access : read-write
MO24 : no description available
bits : 24 - 24 (1 bit)
access : read-write
MO25 : no description available
bits : 25 - 25 (1 bit)
access : read-write
MO26 : no description available
bits : 26 - 26 (1 bit)
access : read-write
MO27 : no description available
bits : 27 - 27 (1 bit)
access : read-write
MO28 : no description available
bits : 28 - 28 (1 bit)
access : read-write
MO29 : no description available
bits : 29 - 29 (1 bit)
access : read-write
MO30 : no description available
bits : 30 - 30 (1 bit)
access : read-write
MO31 : no description available
bits : 31 - 31 (1 bit)
access : read-write
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