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NFC

Peripheral Memory Blocks

address_offset : 0x3F00 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected

Registers

CMD1

CMD2

CAR

RAR

RPT

RAI

SR1

SR2

DMA_CH1

DMACFG

SWAP

SECSZ

CFG

DMA_CH2

ISR


CMD1

Flash command 1
address_offset : 0x3F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD1 CMD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED BYTE3 BYTE2

RESERVED : no description available
bits : 0 - 15 (16 bit)
access : read-only

BYTE3 : Third command byte that may be sent to the flash device
bits : 16 - 23 (8 bit)
access : read-write

BYTE2 : Second command byte that may be sent to the flash device
bits : 24 - 31 (8 bit)
access : read-write


CMD2

Flash command 2
address_offset : 0x3F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD2 CMD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY_START BUFNO RESERVED CODE BYTE1

BUSY_START : Busy indicator and start command
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

During reads, flash controller is idle and it is okay to send next command. During writes, no action.

#1 : 1

During reads, command execution is busy. During writes, start command execution.

End of enumeration elements list.

BUFNO : Internal buffer number used for this command
bits : 1 - 2 (2 bit)
access : read-write

RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only

CODE : User-defined flash operation sequencer
bits : 8 - 23 (16 bit)
access : read-write

BYTE1 : First command byte that may be sent to the flash device
bits : 24 - 31 (8 bit)
access : read-write


CAR

Column address
address_offset : 0x3F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAR CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYTE1 BYTE2 RESERVED

BYTE1 : First byte of column address
bits : 0 - 7 (8 bit)
access : read-write

BYTE2 : Second byte of column address
bits : 8 - 15 (8 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


RAR

Row address
address_offset : 0x3F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAR RAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BYTE1 BYTE2 BYTE3 CS0 CS1 RESERVED RB0 RESERVED

BYTE1 : First byte of row address
bits : 0 - 7 (8 bit)
access : read-write

BYTE2 : Second byte of row address
bits : 8 - 15 (8 bit)
access : read-write

BYTE3 : Third byte of row address
bits : 16 - 23 (8 bit)
access : read-write

CS0 : Chip select 0 enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

NFC_CE0 is disabled

#1 : 1

NFC_CE0 is enabled

End of enumeration elements list.

CS1 : Chip select 1 enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

NFC_CE1 is disabled

#1 : 1

NFC_CE1 is enabled

End of enumeration elements list.

RESERVED : no description available
bits : 26 - 27 (2 bit)
access : read-only

RB0 : Ready/busy 0 enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

NFC_R/ B 0 is disabled

#1 : 1

NFC_R/ B 0 is enabled

End of enumeration elements list.

RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only


RPT

Flash command repeat
address_offset : 0x3F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPT RPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT RESERVED

COUNT : 16-bit repeat count
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


RAI

Row address increment
address_offset : 0x3F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAI RAI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INC1 INC2 INC3 RESERVED

INC1 : Increment for the first byte of row address
bits : 0 - 7 (8 bit)
access : read-write

INC2 : Increment for the second byte of row address
bits : 8 - 15 (8 bit)
access : read-write

INC3 : Increment for the third byte of row address
bits : 16 - 23 (8 bit)
access : read-write

RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only


SR1

Flash status 1
address_offset : 0x3F18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID4 ID3 ID2 ID1

ID4 : Fourth byte returned by read ID command
bits : 0 - 7 (8 bit)
access : read-only

ID3 : Third byte returned by read ID command
bits : 8 - 15 (8 bit)
access : read-only

ID2 : Second byte returned by read ID command
bits : 16 - 23 (8 bit)
access : read-only

ID1 : First byte returned by read ID command
bits : 24 - 31 (8 bit)
access : read-only


SR2

Flash status 2
address_offset : 0x3F1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS1 RESERVED ID5

STATUS1 : Byte returned by read status command
bits : 0 - 7 (8 bit)
access : read-only

RESERVED : no description available
bits : 8 - 23 (16 bit)
access : read-only

ID5 : Fifth byte returned by read ID command
bits : 24 - 31 (8 bit)
access : read-only


DMA_CH1

DMA channel 1 address
address_offset : 0x3F20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_CH1 DMA_CH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : DMA channel 1 address. DMA channel 1 address, it is 8-byte aligned.
bits : 0 - 31 (32 bit)
access : read-write


DMACFG

DMA configuration
address_offset : 0x3F24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFG DMACFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACT2 ACT1 RESERVED OFFSET2 COUNT2 COUNT1

ACT2 : DMA channel 2 status
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inactive

#1 : 1

Active, and transfers to memory when triggered

End of enumeration elements list.

ACT1 : DMA channel 1 status
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inactive

#1 : 1

Active, and transfers to memory when triggered

End of enumeration elements list.

RESERVED : no description available
bits : 2 - 8 (7 bit)
access : read-only

OFFSET2 : 256-byte offset for DMA channel 2. DMA channel 2 transfer starts at this offset count x 256 bytes. For example, if OFFSET2 = 0x2, DMA channel 2 transfer starts at 0x200.
bits : 9 - 12 (4 bit)
access : read-write

COUNT2 : Number of bytes to be transferred by DMA channel 2. It should be multiple of 8 bytes.
bits : 13 - 19 (7 bit)
access : read-write

COUNT1 : Number of bytes to be transferred by DMA channel 1. It should be multiple of 8 bytes.
bits : 20 - 31 (12 bit)
access : read-write


SWAP

Cach swap
address_offset : 0x3F28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWAP SWAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED ADDR2 RESERVED ADDR1 RESERVED

RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only

ADDR2 : Upper swap address
bits : 1 - 11 (11 bit)
access : read-write

RESERVED : no description available
bits : 12 - 16 (5 bit)
access : read-only

ADDR1 : Lower swap address
bits : 17 - 27 (11 bit)
access : read-write

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only


SECSZ

Sector size
address_offset : 0x3F2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECSZ SECSZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE RESERVED

SIZE : Size in bytes of one elementary transfer unit
bits : 0 - 12 (13 bit)
access : read-write

RESERVED : no description available
bits : 13 - 31 (19 bit)
access : read-only


CFG

Flash configuration
address_offset : 0x3F30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAGECNT AIBN AIAD BTMD BITWIDTH TIMEOUT IDCNT FAST ECCMODE DMAREQ ECCSRAM ECCAD STOPWERR

PAGECNT : Number of virtual pages (in one physical flash page) to be programmed or read, etc.
bits : 0 - 3 (4 bit)
access : read-write

AIBN : Auto-incrementing of buffer numbers
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not auto-increment buffer number

#1 : 1

Auto-increment buffer number

End of enumeration elements list.

AIAD : Auto-incrementing of flash row address
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not auto-increment flash row address

#1 : 1

Auto-increment flash row address

End of enumeration elements list.

BTMD : no description available
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal mode

#1 : 1

Boot mode

End of enumeration elements list.

BITWIDTH : Flash mode width
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

8-bit wide flash mode

#1 : 1

16-bit wide flash mode

End of enumeration elements list.

TIMEOUT : no description available
bits : 8 - 12 (5 bit)
access : read-write

IDCNT : Number of bytes that are read for the read id command.
bits : 13 - 15 (3 bit)
access : read-write

FAST : See the "Fast Flash Configuration for EDO" section for more details.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Slow flash timing. Clock in read data on rising edge of read strobe

#1 : 1

Fast flash timing. Clock in read data a half clock later than rising edge of read strobe

End of enumeration elements list.

ECCMODE : ECC type
bits : 17 - 19 (3 bit)
access : read-write

Enumeration:

#000 : 000

No correction, ECC bypass

#001 : 001

4-error correction (8 ECC bytes)

#010 : 010

6-error correction (12 ECC bytes)

#011 : 011

8-error correction (15 ECC bytes)

#100 : 100

12-error correction (23 ECC bytes)

#101 : 101

16-error correction (30 ECC bytes)

#110 : 110

24-error correction (45 ECC bytes)

#111 : 111

32-error correction (60 ECC bytes)

End of enumeration elements list.

DMAREQ : Transferring sectors after ECC
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not transfer sector after ECC is done

#1 : 1

After ECC is done, transfer sector using DMA

End of enumeration elements list.

ECCSRAM : Writing ECC status to SRAM
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not write ECC status to SRAM

#1 : 1

Write ECC status to SRAM

End of enumeration elements list.

ECCAD : Byte address in SRAM where ECC status is written. ECCAD[2:0] are always zeros
bits : 22 - 30 (9 bit)
access : read-write

STOPWERR : Stopping on write error
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

No stop on write error

#1 : 1

Auto-sequencer stops on a write error

End of enumeration elements list.


DMA_CH2

DMA channel 2 address
address_offset : 0x3F34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_CH2 DMA_CH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : DMA channel 2 address, it is 8-byte aligned.
bits : 0 - 31 (32 bit)
access : read-write


ISR

Interrupt status
address_offset : 0x3F38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMABN ECCBN RESBN RESERVED IDLECLR DONECLR WERRCLR IDLEEN DONEEN WERREN DMABUSY ECCBUSY RESBUSY CMDBUSY WERRNS RESERVED IDLE DONE WERR

DMABN : DMA buffer number
bits : 0 - 1 (2 bit)
access : read-only

ECCBN : ECC buffer number
bits : 2 - 3 (2 bit)
access : read-only

RESBN : Residue buffer number
bits : 4 - 5 (2 bit)
access : read-only

RESERVED : no description available
bits : 6 - 16 (11 bit)
access : read-only

IDLECLR : no description available
bits : 17 - 17 (1 bit)
access : read-write

DONECLR : no description available
bits : 18 - 18 (1 bit)
access : read-write

WERRCLR : no description available
bits : 19 - 19 (1 bit)
access : read-write

IDLEEN : no description available
bits : 20 - 20 (1 bit)
access : read-write

DONEEN : no description available
bits : 21 - 21 (1 bit)
access : read-write

WERREN : no description available
bits : 22 - 22 (1 bit)
access : read-write

DMABUSY : DMA engine busy
bits : 23 - 23 (1 bit)
access : read-only

ECCBUSY : ECC engine busy
bits : 24 - 24 (1 bit)
access : read-only

RESBUSY : Residue engine busy
bits : 25 - 25 (1 bit)
access : read-only

CMDBUSY : Command busy
bits : 26 - 26 (1 bit)
access : read-only

WERRNS : Write error status
bits : 27 - 27 (1 bit)
access : read-only

RESERVED : no description available
bits : 28 - 28 (1 bit)
access : read-only

IDLE : Command idle interrupt
bits : 29 - 29 (1 bit)
access : read-only

DONE : DONE interrupt
bits : 30 - 30 (1 bit)
access : read-only

WERR : Write error interrupt
bits : 31 - 31 (1 bit)
access : read-only



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