Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x17 byte (0x0)
mem_usage : registers
protection : not protected
UART Baud Rate Registers: High
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : UART Baud Rate Bits
bits : 0 - 4 (5 bit)
access : read-write
RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only
RXEDGIE : RxD Input Active Edge Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from RXEDGIF disabled using polling.
#1 : 1
RXEDGIF interrupt request enabled.
End of enumeration elements list.
LBKDIE : LIN Break Detect Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
LBKDIF interrupt requests disabled.
#1 : 1
LBKDIF interrupt requests enabled.
End of enumeration elements list.
UART Baud Rate Registers: Low
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : UART Baud Rate Bits
bits : 0 - 7 (8 bit)
access : read-write
UART FIFO Parameters
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFOSIZE : Receive FIFO. Buffer Depth
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
#000 : 000
Receive FIFO/Buffer depth = 1 dataword.
#001 : 001
Receive FIFO/Buffer depth = 4 datawords.
#010 : 010
Receive FIFO/Buffer depth = 8 datawords.
#011 : 011
Receive FIFO/Buffer depth = 16 datawords.
#100 : 100
Receive FIFO/Buffer depth = 32 datawords.
#101 : 101
Receive FIFO/Buffer depth = 64 datawords.
#110 : 110
Receive FIFO/Buffer depth = 128 datawords.
#111 : 111
Reserved.
End of enumeration elements list.
RXFE : Receive FIFO Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#1 : 1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
End of enumeration elements list.
TXFIFOSIZE : Transmit FIFO. Buffer Depth
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#000 : 000
Transmit FIFO/Buffer depth = 1 dataword.
#001 : 001
Transmit FIFO/Buffer depth = 4 datawords.
#010 : 010
Transmit FIFO/Buffer depth = 8 datawords.
#011 : 011
Transmit FIFO/Buffer depth = 16 datawords.
#100 : 100
Transmit FIFO/Buffer depth = 32 datawords.
#101 : 101
Transmit FIFO/Buffer depth = 64 datawords.
#110 : 110
Transmit FIFO/Buffer depth = 128 datawords.
#111 : 111
Reserved.
End of enumeration elements list.
TXFE : Transmit FIFO Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#1 : 1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
End of enumeration elements list.
UART FIFO Control Register
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUFE : Receive FIFO Underflow Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXUF flag does not generate an interrupt to the host.
#1 : 1
RXUF flag generates an interrupt to the host.
End of enumeration elements list.
TXOFE : Transmit FIFO Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXOF flag does not generate an interrupt to the host.
#1 : 1
TXOF flag generates an interrupt to the host.
End of enumeration elements list.
RXOFE : Receive FIFO Overflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXOF flag does not generate an interrupt to the host.
#1 : 1
RXOF flag generates an interrupt to the host.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 5 (3 bit)
access : read-only
RXFLUSH : Receive FIFO/Buffer Flush
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No flush operation occurs.
#1 : 1
All data in the receive FIFO/buffer is cleared out.
End of enumeration elements list.
TXFLUSH : Transmit FIFO/Buffer Flush
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No flush operation occurs.
#1 : 1
All data in the transmit FIFO/Buffer is cleared out.
End of enumeration elements list.
UART FIFO Status Register
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUF : Receiver Buffer Underflow Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive buffer underflow has occurred since the last time the flag was cleared.
#1 : 1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
TXOF : Transmitter Buffer Overflow Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#1 : 1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
RXOF : Receiver Buffer Overflow Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive buffer overflow has occurred since the last time the flag was cleared.
#1 : 1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 5 (3 bit)
access : read-only
RXEMPT : Receive Buffer/FIFO Empty
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer is not empty.
#1 : 1
Receive buffer is empty.
End of enumeration elements list.
TXEMPT : Transmit Buffer/FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit buffer is not empty.
#1 : 1
Transmit buffer is empty.
End of enumeration elements list.
UART FIFO Transmit Watermark
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXWATER : Transmit Watermark
bits : 0 - 7 (8 bit)
access : read-write
UART FIFO Transmit Count
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOUNT : Transmit Counter
bits : 0 - 7 (8 bit)
access : read-only
UART FIFO Receive Watermark
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXWATER : Receive Watermark
bits : 0 - 7 (8 bit)
access : read-write
UART FIFO Receive Count
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCOUNT : Receive Counter
bits : 0 - 7 (8 bit)
access : read-only
UART Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT : Parity Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even parity.
#1 : 1
Odd parity.
End of enumeration elements list.
PE : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Parity function disabled.
#1 : 1
Parity function enabled.
End of enumeration elements list.
ILT : Idle Line Type Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle character bit count starts after start bit.
#1 : 1
Idle character bit count starts after stop bit.
End of enumeration elements list.
WAKE : Receiver Wakeup Method Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle line wakeup.
#1 : 1
Address mark wakeup.
End of enumeration elements list.
M : 9-bit or 8-bit Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#1 : 1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
End of enumeration elements list.
RSRC : Receiver Source Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#1 : 1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
End of enumeration elements list.
RESERVED : Reserved.
bits : 6 - 6 (1 bit)
access : read-only
LOOPS : Loop Mode Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
End of enumeration elements list.
UART Control Register 2
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBK : Send Break
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal transmitter operation.
#1 : 1
Queue break characters to be sent.
End of enumeration elements list.
RWU : Receiver Wakeup Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation.
#1 : 1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
End of enumeration elements list.
RE : Receiver Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver off.
#1 : 1
Receiver on.
End of enumeration elements list.
TE : Transmitter Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter off.
#1 : 1
Transmitter on.
End of enumeration elements list.
ILIE : Idle Line Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
IDLE interrupt requests disabled.
#1 : 1
IDLE interrupt requests enabled.
End of enumeration elements list.
RIE : Receiver Full Interrupt or DMA Transfer Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
RDRF interrupt and DMA transfer requests disabled.
#1 : 1
RDRF interrupt or DMA transfer requests enabled.
End of enumeration elements list.
TCIE : Transmission Complete Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TC interrupt requests disabled.
#1 : 1
TC interrupt requests enabled.
End of enumeration elements list.
TIE : Transmitter Interrupt or DMA Transfer Enable.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDRE interrupt and DMA transfer requests disabled.
#1 : 1
TDRE interrupt or DMA transfer requests enabled.
End of enumeration elements list.
UART Status Register 1
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PF : Parity Error Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#1 : 1
At least one dataword was received with a parity error since the last time this flag was cleared.
End of enumeration elements list.
FE : Framing Error Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No framing error detected.
#1 : 1
Framing error.
End of enumeration elements list.
NF : Noise Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#1 : 1
At least one dataword was received with noise detected since the last time the flag was cleared.
End of enumeration elements list.
OR : Receiver Overrun Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No overrun has occurred since the last time the flag was cleared.
#1 : 1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
End of enumeration elements list.
IDLE : Idle Line Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#1 : 1
Receiver input has become idle or the flag has not been cleared since it last asserted.
End of enumeration elements list.
RDRF : Receive Data Register Full Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#1 : 1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
End of enumeration elements list.
TC : Transmit Complete Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter active (sending data, a preamble, or a break).
#1 : 1
Transmitter idle (transmission activity complete).
End of enumeration elements list.
TDRE : Transmit Data Register Empty Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#1 : 1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
End of enumeration elements list.
UART Status Register 2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAF : Receiver Active Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART receiver idle/inactive waiting for a start bit.
#1 : 1
UART receiver active, RxD input not idle.
End of enumeration elements list.
LBKDE : LIN Break Detection Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character detection is disabled.
#1 : 1
Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
End of enumeration elements list.
BRK13 : Break Transmit Character Length
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character is 10, 11, or 12 bits long.
#1 : 1
Break character is 13 or 14 bits long.
End of enumeration elements list.
RWUID : Receive Wakeup Idle Detect
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
S1[IDLE] is not set upon detection of an idle character.
#1 : 1
S1[IDLE] is set upon detection of an idle character.
End of enumeration elements list.
RXINV : Receive Data Inversion
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data is not inverted.
#1 : 1
Receive data is inverted.
End of enumeration elements list.
MSBF : Most Significant Bit First
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#1 : 1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
End of enumeration elements list.
RXEDGIF : RxD Pin Active Edge Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active edge on the receive pin has occurred.
#1 : 1
An active edge on the receive pin has occurred.
End of enumeration elements list.
LBKDIF : LIN Break Detect Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No LIN break character detected.
#1 : 1
LIN break character detected.
End of enumeration elements list.
UART Control Register 3
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEIE : Parity Error Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF interrupt requests are disabled.
#1 : 1
PF interrupt requests are enabled.
End of enumeration elements list.
FEIE : Framing Error Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FE interrupt requests are disabled.
#1 : 1
FE interrupt requests are enabled.
End of enumeration elements list.
NEIE : Noise Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
NF interrupt requests are disabled.
#1 : 1
NF interrupt requests are enabled.
End of enumeration elements list.
ORIE : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OR interrupts are disabled.
#1 : 1
OR interrupt requests are enabled.
End of enumeration elements list.
TXINV : Transmit Data Inversion.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is not inverted.
#1 : 1
Transmit data is inverted.
End of enumeration elements list.
TXDIR : Transmitter Pin Data Direction in Single-Wire mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXD pin is an input in single wire mode.
#1 : 1
TXD pin is an output in single wire mode.
End of enumeration elements list.
T8 : Transmit Bit 8
bits : 6 - 6 (1 bit)
access : read-write
R8 : Received Bit 8
bits : 7 - 7 (1 bit)
access : read-only
UART Data Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RT : no description available
bits : 0 - 7 (8 bit)
access : read-write
UART Match Address Registers 1
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Match Address
bits : 0 - 7 (8 bit)
access : read-write
UART Match Address Registers 2
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Match Address
bits : 0 - 7 (8 bit)
access : read-write
UART Control Register 4
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRFA : Baud Rate Fine Adjust
bits : 0 - 4 (5 bit)
access : read-write
M10 : 10-bit Mode select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The parity bit is the ninth bit in the serial transmission.
#1 : 1
The parity bit is the tenth bit in the serial transmission.
End of enumeration elements list.
MAEN2 : Match Address Mode Enable 2
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
All data received is transferred to the data buffer if MAEN1 is cleared.
#1 : 1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
End of enumeration elements list.
MAEN1 : Match Address Mode Enable 1
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
All data received is transferred to the data buffer if MAEN2 is cleared.
#1 : 1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
End of enumeration elements list.
UART Control Register 5
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only
RESERVED : no description available
bits : 4 - 4 (1 bit)
access : read-only
RDMAS : Receiver Full DMA Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#1 : 1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
End of enumeration elements list.
RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-only
TDMAS : Transmitter DMA Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#1 : 1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
End of enumeration elements list.
UART Extended Data Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 5 (6 bit)
access : read-only
PARITYE : no description available
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
The dataword was received without a parity error.
#1 : 1
The dataword was received with a parity error.
End of enumeration elements list.
NOISY : no description available
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The dataword was received without noise.
#1 : 1
The data was received with noise.
End of enumeration elements list.
UART Modem Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTSE : Transmitter clear-to-send enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTS has no effect on the transmitter.
#1 : 1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
End of enumeration elements list.
TXRTSE : Transmitter request-to-send enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitter has no effect on RTS.
#1 : 1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
End of enumeration elements list.
TXRTSPOL : Transmitter request-to-send polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter RTS is active low.
#1 : 1
Transmitter RTS is active high.
End of enumeration elements list.
RXRTSE : Receiver request-to-send enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receiver has no effect on RTS.
#1 : 1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only
UART Infrared Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TNP : Transmitter narrow pulse
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
3/16.
#01 : 01
1/16.
#10 : 10
1/32.
#11 : 11
1/4.
End of enumeration elements list.
IREN : Infrared enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
IR disabled.
#1 : 1
IR enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 7 (5 bit)
access : read-only
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