Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x10 Bytes (0x0)
size : 0x2B4 byte (0x0)
mem_usage : registers
protection : not protected
PLL3 Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-write
DIV_SELECT : Select PLL multiplication factor (MFI), Fout = Fref * 20 to generates Fout = 480 MHz when Fref = 24 MHz.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fout = Fref*20 (default value)
#1 : 1
Fout = Fref*22
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 4 (3 bit)
access : read-only
RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only
EN_USB_CLKS : Clock Gating for 8 Phase clock of USB0 PHY.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
8-phase PLL outputs for USB0 PHY are powered down.
#1 : 1
8-phase PLL outputs for USB0 PHY are powered up.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-only
POWER : Powers up the USB0 PLL.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not powered up
#1 : 1
Powered up
End of enumeration elements list.
ENABLE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL output clock is gated, so disabled.
#1 : 1
PLL output clock is enabled.
End of enumeration elements list.
BYPASS_CLK_SRC : Bypass Clock Source selection.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL.
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable bypass
#1 : 1
Enable bypass
End of enumeration elements list.
RESERVED : no description available
bits : 17 - 30 (14 bit)
access : read-only
LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
ANADIG PLL2 PFD definition register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD1_FRAC : This field controls the fractional divide value.
bits : 0 - 5 (6 bit)
access : read-write
PFD1_STABLE : no description available
bits : 6 - 6 (1 bit)
access : read-only
PFD1_CLKGATE : This bit controls the generation of PFD1.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd1 fractional divider clock is enabled.
#1 : 1
ref_pfd1 fractional divider clock is disabled for power saving.
End of enumeration elements list.
PFD2_FRAC : no description available
bits : 8 - 13 (6 bit)
access : read-write
PFD2_STABLE : no description available
bits : 14 - 14 (1 bit)
access : read-only
PFD2_CLKGATE : This bit controls the generation of PFD2.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd2 fractional divider clock is enabled.
#1 : 1
ref_pfd2 fractional divider clock is disabled for power savings.
End of enumeration elements list.
PFD3_FRAC : no description available
bits : 16 - 21 (6 bit)
access : read-write
PFD3_STABLE : no description available
bits : 22 - 22 (1 bit)
access : read-only
PFD3_CLKGATE : This bit controls the generation of PFD3.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd3 fractional divider clock is enabled.
#1 : 1
ref_pfd3 fractional divider clock is disabled for power savings.
End of enumeration elements list.
PFD4_FRAC : no description available
bits : 24 - 29 (6 bit)
access : read-write
PFD4_STABLE : no description available
bits : 30 - 30 (1 bit)
access : read-only
PFD4_CLKGATE : This bit controls the generation of PFD4.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd4 fractional divider clock is enabled.
#1 : 1
ref_pfd4 fractional divider clock is disabled for power savings.
End of enumeration elements list.
ANADIG Regulator 1P1 definition register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Regulator output is not enabled
#1 : 1
Enable the regulator output.
End of enumeration elements list.
ENABLE_BO : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out circuitry in the regulator is not enabled
#1 : 1
Enable the brown-out circuitry in the regulator.
End of enumeration elements list.
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator input power.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Current-limit circuitry in the regulator is not enabled
#1 : 1
Enable the current-limit circuitry in the regulator.
End of enumeration elements list.
ENABLE_PULLDOWN : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-down circuitry in the regulator is not enabled
#1 : 1
enable the pull-down circuitry in the regulator.
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only
BO_VDD1P1 : This is the status bit that shows if the regulator Brown-out is asserted of not.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Brown-out is not detected on the regulator output.
#1 : 1
Brown-out is detected on the regulator output.
End of enumeration elements list.
OK_VDD1P1 : no description available
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Regulator output is not ok.
#1 : 1
Regulator output is ok.
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 31 (14 bit)
access : read-only
ANADIG Regulator 3P0 definition register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Regulator output is not enabled
#1 : 1
Enable the regulator output.
End of enumeration elements list.
ENABLE_BO : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out circuitry in the regulator is not enabled
#1 : 1
Enable the brown-out circuitry in the regulator
End of enumeration elements list.
ENABLE_ILIMIT : Control bit to enable the current-limit circuitry in the regulator input power.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Current-limit circuitry in the regulator is not enabled
#1 : 1
Enable the current-limit circuitry in the regulator
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 6 (4 bit)
access : read-only
REG_3P0_VBUS_SEL : no description available
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Utilize host power.
#1 : 1
Utilize OTG power.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only
BO_VDD3P0 : This is the status bit that shows if the regulator Brown-out is asserted of not.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Brown-out is not detected on the regulator output.
#1 : 1
Brown-out is detected on the regulator output.
End of enumeration elements list.
OK_VDD3P0 : This status bit signals that the regulator output is ok.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Regulator output is not ok
#1 : 1
Regulator output is ok
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 31 (14 bit)
access : read-only
ANADIG Regulator 2P5 definition register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE_LINREG : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
Regulator output is not enabled
#0 : 0
Enable the regulator output.
End of enumeration elements list.
ENABLE_BO : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out circuitry in the regulator is not enabled
#1 : 1
Enable the brown-out circuitry in the regulator
End of enumeration elements list.
ENABLE_ILIMIT : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Current-limit circuitry in the regulator is not enabled
#1 : 1
Enable the current-limit circuitry in the regulator
End of enumeration elements list.
ENABLE_PULLDOWN : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-down circuitry in the regulator is not enabled
#1 : 1
Enable the pull-down circuitry in the regulator
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 15 (12 bit)
access : read-only
BO_VDD2P5 : This is the status bit that shows if the regulator Brown-out is asserted of not.
bits : 16 - 16 (1 bit)
access : read-only
OK_VDD2P5 : no description available
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Regulator output is not ok.
#1 : 1
Regulator output is ok.
End of enumeration elements list.
ENABLE_WEAK_LINREG : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Weak 2p5 regulator is not enabled
#1 : 1
Enable the weak 2p5 regulator
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 31 (13 bit)
access : read-only
ANADIG Analog Miscellaneous definition register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTOP_PWD : no description available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog bandgap reference circuitry is not powered down
#1 : 1
Powerdown the analog bandgap reference circuitry
End of enumeration elements list.
REFTOP_PWDVBGUP : no description available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
VBG-up detection circuitry in the analog bandgap is not powered down
#1 : 1
Power-down the VBG-up detection circuitry in the analog bandgap
End of enumeration elements list.
REFTOP_LOWPOWER : no description available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-power mode in the analog bandgap is not enabled
#1 : 1
Enable the low-power mode in the analog bandgap
End of enumeration elements list.
REFTOP_SELBIASOFF : no description available
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Self-bias circuit in the analog bandgap is not diabled
#1 : 1
Disable the self-bias circuit in the analog bandgap
End of enumeration elements list.
RESERVED : no description available
bits : 4 - 6 (3 bit)
access : read-only
REFTOP_VBGUP : no description available
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Analog bandgap voltage is not up and stable
#1 : 1
Analog bandgap voltage is up and stable
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 11 (4 bit)
access : read-only
STOP_MODE_CONFIG : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
All analog except rtc powered down on stop mode assertion.
#1 : 1
On the device Anatop, just the Reftop (reference bias circuit) can be kept alive in Stop mode. To support wake-up from USB (Device Mode) , this bit must be set to '1' if 'analog_stop_mode' is used in stop mode (i.e if 'analog_stop_mode bit is set '1' in CCM Low Power Control Register).
End of enumeration elements list.
CLK_24M_IRC_XTAL_SEL : Select internal 24M IRC clock or External 24M xtal clock as a source of 24MHz.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 24Mhz Xtal Clock
#1 : 1
24MHz Internal IRC. It is recommended to not use internal IRC for enabling PLL's.
End of enumeration elements list.
RESERVED : no description available
bits : 14 - 15 (2 bit)
access : read-only
OSC_XTALOK : no description available
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Output of the 24 MHz crystal oscillator is not stable
#1 : 1
Output of the 24 MHz crystal oscillator is stable
End of enumeration elements list.
OSC_XTALOK_EN : Oscillator Crystal Lock Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Oscillator crystal lock is not enabled
#1 : 1
Enable the oscillator crystal lock
End of enumeration elements list.
RESERVED : no description available
bits : 18 - 28 (11 bit)
access : read-only
RESERVED : no description available
bits : 29 - 31 (3 bit)
access : read-only
ANADIG Analog Miscellaneous definition register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only
RESERVED : no description available
bits : 5 - 9 (5 bit)
access : read-only
LVDSCLK1_OBEN : This bit enables the lvds output buffer for selected internal clock.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
LVDs output buffer is not enabled for driving internal clock
#1 : 1
Enable the LVDs output buffer for driving internal clock
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 11 (1 bit)
access : read-only
LVDSCLK1_IBEN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
LVDs input buffer not enabled for AnaClock
#1 : 1
Enable the LVDs input buffer for AnaClock
End of enumeration elements list.
RESERVED : no description available
bits : 13 - 28 (16 bit)
access : read-only
IRQ_TEMPSENSE : no description available
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor interrupt is not asserted
#1 : 1
Set to one when when the temperature sensor interrupt is asserted
End of enumeration elements list.
IRQ_ANA_BO : no description available
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of the analog regulator brownout interrupts is asserted
#1 : 1
Set to one when when any of the analog regulator brownout interrupts is asserted
End of enumeration elements list.
RESERVED : no description available
bits : 31 - 31 (1 bit)
access : read-only
PLL7 Control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-write
DIV_SELECT : Select PLL multiplication factor (MFI), Fout = Fref * 20 to generates Fout = 480 MHz when Fref = 24 MHz.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fout = Fref * 20 (default value)
#1 : 1
Fout = Fref * 22
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 4 (3 bit)
access : read-only
RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only
EN_USB_CLKS : Clock Gating for 8 Phase clock of USB0 PHY.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
8-phase PLL outputs for USB1 PHY are powered down.
#1 : 1
8-phase PLL outputs for USB1 PHY are powered up.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-write
POWER : Powers up the USB1 PLL
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not powered up
#1 : 1
Powered up
End of enumeration elements list.
ENABLE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock output not enabled
#1 : 1
Enable clock output
End of enumeration elements list.
BYPASS_CLK_SRC : Bypass Clock Source selection.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL.
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : Bypasses the PLL.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable bypass
#1 : 1
Enable bypass
End of enumeration elements list.
RESERVED : no description available
bits : 17 - 30 (14 bit)
access : read-only
LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
ANADIG Digital Program register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MINOR : no description available
bits : 0 - 7 (8 bit)
access : read-only
MAJOR : no description available
bits : 8 - 23 (16 bit)
access : read-only
RESERVED : no description available
bits : 24 - 31 (8 bit)
access : read-only
PLL1 Control register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : Frequency multipler selection.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : 00
Fout = Fref * 20
#01 : 01
Fout = Fref * 22
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 6 (6 bit)
access : read-only
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-only
POWERDOWN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is not powered down
#1 : 1
Power down the PLL
End of enumeration elements list.
ENABLE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL output clock is gated, so disabled.
#1 : 1
PLL output clock is enabled.
End of enumeration elements list.
BYPASS_CLK_SRC : Bypass Clock Source.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : Reserved.
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : Bypasses the PLL
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable bypass
#1 : 1
Enable bypass
End of enumeration elements list.
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dither in the fractional modulator calculation is not enabled
#1 : 1
Enable dither in the fractional modulator calculation.
End of enumeration elements list.
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Offset in the phase frequency detector is not enabled
#1 : 1
Enable an offset in the phase frequency detector
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 30 (12 bit)
access : read-only
LOCK : Lock bit.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
PLL1 Spread Spectrum register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP : STOP and STEP together control the modulation depth (maximum frequency change) and Modulation Depth in the SSCG mode (as per given formula).
bits : 0 - 14 (15 bit)
access : read-write
ENABLE : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spread spectrum modulation is not enabled
#1 : 1
Enable spread spectrum modulation
End of enumeration elements list.
STOP : STOP and STEP together control the modulation depth (maximum frequency change) and Modulation Depth in the SSCG mode (as per given formula).
bits : 16 - 31 (16 bit)
access : read-write
PLL1 Numerator register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFN : This is the 30-bit numerator of the fractional loop divider.
bits : 0 - 29 (30 bit)
access : read-write
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL1 Denominator register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFD : This is the 30-bit denominator of the fractional loop divider.
bits : 0 - 29 (30 bit)
access : read-write
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
ANADIG PLL1_PFD definition register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD1_FRAC : no description available
bits : 0 - 5 (6 bit)
access : read-write
D1_STABLE : no description available
bits : 6 - 6 (1 bit)
access : read-only
PFD1_CLKGATE : This bit enables the fractional divider clock.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd1 fractional divider clock is enabled.
#1 : 1
ref_pfd1 fractional divider clock is disabled for power saving.
End of enumeration elements list.
PFD2_FRAC : no description available
bits : 8 - 13 (6 bit)
access : read-write
PFD2_STABLE : no description available
bits : 14 - 14 (1 bit)
access : read-only
PFD2_CLKGATE : This bit controls the generation of PFD2.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd2 fractional divider clock is enabled.
#1 : 1
ref_pfd2 fractional divider clock is disabled for power savings.
End of enumeration elements list.
PFD3_FRAC : no description available
bits : 16 - 21 (6 bit)
access : read-write
PFD3_STABLE : no description available
bits : 22 - 22 (1 bit)
access : read-only
PFD3_CLKGATE : This bit enables the fractional divider clock.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd3 fractional divider clock is enabled.
#1 : 1
ref_pfd3 fractional divider clock is disabled for power savings.
End of enumeration elements list.
PFD4_FRAC : no description available
bits : 24 - 29 (6 bit)
access : read-write
PFD4_STABLE : no description available
bits : 30 - 30 (1 bit)
access : read-only
PFD4_CLKGATE : This bit enables the fractional divider clock.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd4 fractional divider clock is enabled.
#1 : 1
ref_pfd4 fractional divider clock is disabled for power savings.
End of enumeration elements list.
ANADIG PLL Lock register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PLL7 : This bit shows if PLL7 (USB1) is locked.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL1 not locked yet.
#1 : 1
PLL1 locked.
End of enumeration elements list.
PLL3 : This bit shows if PLL3 (USB0) is locked.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL2 not locked yet.
#1 : 1
PLL2 locked.
End of enumeration elements list.
PLL5 : This bit shows if PLL5 (ENET)is locked.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL4 not locked yet.
#1 : 1
PLL4 locked.
End of enumeration elements list.
PLL6 : This bit shows if PLL6 (Video) is locked.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL6 not locked yet.
#1 : 1
PLL6 locked.
End of enumeration elements list.
PLL4 : This bit shows if PLL4 (Audio) is locked.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL5 not locked yet.
#1 : 1
PLL5 locked.
End of enumeration elements list.
PLL2 : This bit shows id PLL2 (528) is locked.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL3 not locked yet.
#1 : 1
528 PLL3 locked.
End of enumeration elements list.
PLL1 : This bit shows if PLL1 (528 SYS) is locked.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL7 not locked yet.
#1 : 1
PLL7 locked.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-only
PLL2 Control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : Frequency multipler selection (MFI).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fout = Fref * 20
#1 : 1
Fout = Fref * 22. If PLL frequency is to be 528MHz, Fout = 528 MHz = 24 MHz xtal * 22.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 6 (6 bit)
access : read-only
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-only
POWERDOWN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is not powered down
#1 : 1
Power down the PLL
End of enumeration elements list.
ENABLE : Enables the PLL output clock.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL output clock is gated, so disabled.
#1 : 1
PLL output clock is enabled.
End of enumeration elements list.
BYPASS_CLK_SRC : Bypass Clock Source selection.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : Reserved.
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : Bypasses the PLL
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable bypass
#1 : 1
Enable bypass
End of enumeration elements list.
DITHER_ENABLE : Enables dither in the fractional modulator calculation.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dither in the fractional modulator calculation is not enabled
#1 : 1
Enable dither in the fractional modulator calculation.
End of enumeration elements list.
PFD_OFFSET_EN : Enables an offset in the phase frequency detector.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Offset in the phase frequency detector is not enabled
#1 : 1
Enable an offset in the phase frequency detector
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 30 (12 bit)
access : read-only
LOCK : Lock bit.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
PLL2 Spread Spectrum definition register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP : STOP and STEP together control the modulation depth (maximum frequency change) and Modulation Depth in the SSCG mode (as per given formula).
bits : 0 - 14 (15 bit)
access : read-write
ENABLE : no description available
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spectrum modulation is not enabled
#1 : 1
Enable spectrum modulation
End of enumeration elements list.
STOP : STOP and STEP together control the modulation depth (maximum frequency change) and Modulation Depth in the SSCG mode (as per given formula).
bits : 16 - 31 (16 bit)
access : read-write
PLL2 Numerator definition register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFN : 30-bit numerator of the fractional loop divider (unsigned integer).
bits : 0 - 29 (30 bit)
access : read-only
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL2 Denominator definition register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFD : 30-bit denominator of the fractional loop divider (unsigned integer).
bits : 0 - 29 (30 bit)
access : read-only
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL4 Control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : Frequency multipler factor selection.
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-only
POWERDOWN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Power Down
#1 : 1
PLL Power Down
End of enumeration elements list.
ENABLE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL output clock is disabled.
#1 : 1
PLL output clock is enabled.
End of enumeration elements list.
BYPASS_CLK_SRC : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL.
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : no description available
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Bypass, PLL will drive its own Clock
#1 : 1
Enable bypass
End of enumeration elements list.
DITHER_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dither is not enabled
#1 : 1
Enable ditther
End of enumeration elements list.
PFD_OFFSET_EN : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PFD offset is not enabled
#1 : 1
Enable PFD offset
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 20 (2 bit)
access : read-only
RESERVED : no description available
bits : 21 - 30 (10 bit)
access : read-only
LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
PLL4 Numerator register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFN : no description available
bits : 0 - 29 (30 bit)
access : read-write
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL4 Denominator register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFD : no description available
bits : 0 - 29 (30 bit)
access : read-write
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL6 Control register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : Frequency multiplier factor selection.
bits : 0 - 6 (7 bit)
access : read-write
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-only
POWERDOWN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power down is not enabled
#1 : 1
Enable power down
End of enumeration elements list.
ENABLE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock output is not enabled
#1 : 1
Enable clock output
End of enumeration elements list.
BYPASS_CLK_SRC : Bypass Clock Source selection.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL.
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : Bypasses the PLL.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bypass is not enabled
#1 : 1
Enable bypass
End of enumeration elements list.
DITHER_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dither is not enabled
#1 : 1
Enable dither
End of enumeration elements list.
PFD_OFFSET_EN : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PFD offset is not enabled
#1 : 1
Enable PFD offset
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 20 (2 bit)
access : read-only
RESERVED : no description available
bits : 21 - 30 (10 bit)
access : read-only
LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
PLL6 Numerator register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFN : no description available
bits : 0 - 29 (30 bit)
access : read-write
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL6 Denominator register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFD : no description available
bits : 0 - 29 (30 bit)
access : read-write
RESERVED : no description available
bits : 30 - 31 (2 bit)
access : read-only
PLL5 Control register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_SELECT : Controls the frequency of the Ethernet reference clock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#01 : 01
50 MHz
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 6 (5 bit)
access : read-only
RESERVED : no description available
bits : 7 - 11 (5 bit)
access : read-only
POWERDOWN : no description available
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power down is not enabled
#1 : 1
Enable power down
End of enumeration elements list.
ENABLE : no description available
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock output is not enabled
#1 : 1
Enable clock output
End of enumeration elements list.
BYPASS_CLK_SRC : no description available
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
24M XTAL clock is selected as clock source for the PLL.
#1 : 1
External clock through LVDS pad is selected as clock source for the PLL.
End of enumeration elements list.
RESERVED : no description available
bits : 15 - 15 (1 bit)
access : read-only
BYPASS : Bypasses the PLL..
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bypass is not enabled
#1 : 1
Enable bypass
End of enumeration elements list.
DITHER_ENABLE : no description available
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dither is not enabled
#1 : 1
Enable dither
End of enumeration elements list.
PFD_OFFSET_EN : no description available
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PFD offset is not enabled
#1 : 1
Enable PFD offset
End of enumeration elements list.
RESERVED : no description available
bits : 19 - 30 (12 bit)
access : read-only
LOCK : no description available
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is not currently locked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
ANADIG PLL3 PFD definition register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PFD1_FRAC : This field controls the fractional divide value.
bits : 0 - 5 (6 bit)
access : read-write
PFD1_STABLE : no description available
bits : 6 - 6 (1 bit)
access : read-only
PFD1_CLKGATE : This bit controls the generation of PFD1.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd1 fractional divider clock is enabled.
#1 : 1
ref_pfd1 fractional divider clock is disabled for power saving.
End of enumeration elements list.
PFD2_FRAC : no description available
bits : 8 - 13 (6 bit)
access : read-write
PFD2_STABLE : no description available
bits : 14 - 14 (1 bit)
access : read-only
PFD2_CLKGATE : This bit controls the generation of PFD2.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd2 fractional divider clock is enabled.
#1 : 1
ref_pfd2 fractional divider clock is disabled for power savings.
End of enumeration elements list.
PFD3_FRAC : no description available
bits : 16 - 21 (6 bit)
access : read-write
PFD3_STABLE : no description available
bits : 22 - 22 (1 bit)
access : read-only
PFD3_CLKGATE : This bit controls the generation of PFD3.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd3 fractional divider clock is enabled.
#1 : 1
ref_pfd3 fractional divider clock is disabled for power savings.
End of enumeration elements list.
PFD4_FRAC : no description available
bits : 24 - 29 (6 bit)
access : read-write
PFD4_STABLE : no description available
bits : 30 - 30 (1 bit)
access : read-only
PFD4_CLKGATE : This bit controls the generation of PFD4.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ref_pfd4 fractional divider clock is enabled.
#1 : 1
ref_pfd4 fractional divider clock is disabled for power savings.
End of enumeration elements list.
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