\n
address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection : not protected
USB PHY Power-Down Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only
TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write
TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.
End of enumeration elements list.
TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Nornal operation.
#1 : 1
Powerdown the USB PHY transmit V-to-I converter and the current mirror.
End of enumeration elements list.
RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only
RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write
RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write
RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write
RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only
USB PHY Transmitter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D_CAL : no description available
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Maximum current, approximately 19% above nominal.
#0111 : 0111
Nominal.
#1111 : 1111
Minimum current, approximately 19% below nominal
End of enumeration elements list.
RSVD0 : no description available
bits : 4 - 7 (4 bit)
access : read-write
TXCAL45DM : no description available
bits : 8 - 11 (4 bit)
access : read-write
RSVD1 : no description available
bits : 12 - 15 (4 bit)
access : read-write
TXCAL45DP : no description available
bits : 16 - 19 (4 bit)
access : read-write
RSVD2 : no description available
bits : 20 - 31 (12 bit)
access : read-only
USB PHY Receiver Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only
DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only
RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write
RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only
USB PHY Receiver Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only
DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only
RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write
RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only
USB PHY Receiver Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only
DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only
RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write
RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only
USB PHY Receiver Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only
DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write
RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only
RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write
RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only
USB PHY General Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write
DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write
OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write
ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write
RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write
DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write
DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write
ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write
ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write
ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write
FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write
OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
USB PHY General Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write
DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write
OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write
ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write
RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write
DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write
DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write
ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write
ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write
ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write
FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write
OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
USB PHY General Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write
DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write
OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write
ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write
RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write
DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write
DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write
ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write
ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write
ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write
FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write
OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
USB PHY General Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write
ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write
ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write
HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write
ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write
DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write
OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write
ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write
RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write
ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write
RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write
ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write
DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write
DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write
ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write
ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write
ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write
WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write
ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write
ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write
ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write
ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write
ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write
FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write
RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write
RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write
OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write
HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write
UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write
USB PHY Power-Down Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only
TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write
TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.
End of enumeration elements list.
TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Nornal operation.
#1 : 1
Powerdown the USB PHY transmit V-to-I converter and the current mirror.
End of enumeration elements list.
RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only
RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write
RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write
RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write
RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only
USB PHY Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 2 (3 bit)
access : read-only
HOSTDISCONDETECT_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-write
RSVD1 : no description available
bits : 4 - 5 (2 bit)
access : read-only
DEVPLUGIN_STATUS : no description available
bits : 6 - 6 (1 bit)
access : read-write
RSVD2 : no description available
bits : 7 - 7 (1 bit)
access : read-only
OTGID_STATUS : no description available
bits : 8 - 8 (1 bit)
access : read-write
RSVD3 : no description available
bits : 9 - 9 (1 bit)
access : read-only
RESUME_STATUS : no description available
bits : 10 - 10 (1 bit)
access : read-write
RSVD4 : no description available
bits : 11 - 31 (21 bit)
access : read-only
USB PHY Debug Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write
DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write
HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write
ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write
RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only
TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write
ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only
SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only
ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write
SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write
HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only
USB PHY Debug Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write
DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write
HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write
ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write
RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only
TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write
ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only
SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only
ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write
SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write
HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only
USB PHY Debug Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write
DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write
HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write
ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write
RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only
TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write
ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only
SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only
ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write
SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write
HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only
USB PHY Debug Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write
DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write
HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write
ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write
RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only
TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write
ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write
RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only
SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only
ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write
SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write
HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write
CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write
RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only
UTMI Debug Status Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOP_BACK_FAIL_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write
UTMI_RXERROR_FAIL_COUNT : no description available
bits : 16 - 25 (10 bit)
access : read-write
SQUELCH_COUNT : no description available
bits : 26 - 31 (6 bit)
access : read-write
UTMI Debug Status Register 1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only
ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only
UTMI Debug Status Register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only
ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only
UTMI Debug Status Register 1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only
ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only
UTMI Debug Status Register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only
ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write
RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only
USB PHY Power-Down Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only
TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write
TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.
End of enumeration elements list.
TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Nornal operation.
#1 : 1
Powerdown the USB PHY transmit V-to-I converter and the current mirror.
End of enumeration elements list.
RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only
RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write
RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write
RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write
RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only
UTMI RTL Version
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STEP : no description available
bits : 0 - 15 (16 bit)
access : read-only
MINOR : no description available
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : no description available
bits : 24 - 31 (8 bit)
access : read-only
USB PHY IP Block Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write
PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write
EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write
USB PHY IP Block Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write
PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write
EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write
USB PHY IP Block Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write
PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write
EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write
USB PHY IP Block Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write
PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write
EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write
RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write
RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write
RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write
USB PHY Power-Down Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only
TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write
TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.
End of enumeration elements list.
TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Nornal operation.
#1 : 1
Powerdown the USB PHY transmit V-to-I converter and the current mirror.
End of enumeration elements list.
RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only
RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write
RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write
RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write
RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write
RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.