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USBPHY

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWD

TX

RX

RX_SET

RX_CLR

RX_TOG

CTRL

CTRL_SET

CTRL_CLR

CTRL_TOG

PWD_SET

STATUS

DEBUG

DEBUG_SET

DEBUG_CLR

DEBUG_TOG

DEBUG0_STATUS

DEBUG1

DEBUG1_SET

DEBUG1_CLR

DEBUG1_TOG

PWD_CLR

VERSION

IP

IP_SET

IP_CLR

IP_TOG

PWD_TOG


PWD

USB PHY Power-Down Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD PWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.

End of enumeration elements list.

TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Nornal operation.

#1 : 1

Powerdown the USB PHY transmit V-to-I converter and the current mirror.

End of enumeration elements list.

RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only


TX

USB PHY Transmitter Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D_CAL RSVD0 TXCAL45DM RSVD1 TXCAL45DP RSVD2

D_CAL : no description available
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Maximum current, approximately 19% above nominal.

#0111 : 0111

Nominal.

#1111 : 1111

Minimum current, approximately 19% below nominal

End of enumeration elements list.

RSVD0 : no description available
bits : 4 - 7 (4 bit)
access : read-write

TXCAL45DM : no description available
bits : 8 - 11 (4 bit)
access : read-write

RSVD1 : no description available
bits : 12 - 15 (4 bit)
access : read-write

TXCAL45DP : no description available
bits : 16 - 19 (4 bit)
access : read-write

RSVD2 : no description available
bits : 20 - 31 (12 bit)
access : read-only


RX

USB PHY Receiver Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only


RX_SET

USB PHY Receiver Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_SET RX_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only


RX_CLR

USB PHY Receiver Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_CLR RX_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only


RX_TOG

USB PHY Receiver Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_TOG RX_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVADJ RSVD0 DISCONADJ RSVD1 RXDBYPASS RSVD2

ENVADJ : no description available
bits : 0 - 2 (3 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 3 (1 bit)
access : read-only

DISCONADJ : no description available
bits : 4 - 6 (3 bit)
access : read-write

RSVD1 : no description available
bits : 7 - 21 (15 bit)
access : read-only

RXDBYPASS : no description available
bits : 22 - 22 (1 bit)
access : read-write

RSVD2 : no description available
bits : 23 - 31 (9 bit)
access : read-only


CTRL

USB PHY General Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RESERVED ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RESERVED RESERVED OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write

ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write

OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write

HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


CTRL_SET

USB PHY General Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_SET CTRL_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RESERVED ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RESERVED RESERVED OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write

ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write

OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write

HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


CTRL_CLR

USB PHY General Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_CLR CTRL_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RESERVED ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RESERVED RESERVED OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write

ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write

OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write

HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


CTRL_TOG

USB PHY General Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_TOG CTRL_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENOTG_ID_CHG_IRQ ENHOSTDISCONDETECT ENIRQHOSTDISCON HOSTDISCONDETECT_IRQ ENDEVPLUGINDETECT DEVPLUGIN_POLARITY OTG_ID_CHG_IRQ ENOTGIDDETECT RESUMEIRQSTICKY ENIRQRESUMEDETECT RESUME_IRQ ENIRQDEVPLUGIN DEVPLUGIN_IRQ DATA_ON_LRADC ENUTMILEVEL2 ENUTMILEVEL3 ENIRQWAKEUP WAKEUP_IRQ RESERVED ENAUTOCLR_CLKGATE ENAUTOCLR_PHY_PWD ENDPDMCHG_WKUP ENIDCHG_WKUP ENVBUSCHG_WKUP FSDLL_RST_EN RESERVED RESERVED OTG_ID_VALUE HOST_FORCE_LS_SE0 UTMI_SUSPENDM CLKGATE SFTRST

ENOTG_ID_CHG_IRQ : no description available
bits : 0 - 0 (1 bit)
access : read-write

ENHOSTDISCONDETECT : no description available
bits : 1 - 1 (1 bit)
access : read-write

ENIRQHOSTDISCON : no description available
bits : 2 - 2 (1 bit)
access : read-write

HOSTDISCONDETECT_IRQ : no description available
bits : 3 - 3 (1 bit)
access : read-write

ENDEVPLUGINDETECT : no description available
bits : 4 - 4 (1 bit)
access : read-write

DEVPLUGIN_POLARITY : no description available
bits : 5 - 5 (1 bit)
access : read-write

OTG_ID_CHG_IRQ : no description available
bits : 6 - 6 (1 bit)
access : read-write

ENOTGIDDETECT : no description available
bits : 7 - 7 (1 bit)
access : read-write

RESUMEIRQSTICKY : no description available
bits : 8 - 8 (1 bit)
access : read-write

ENIRQRESUMEDETECT : no description available
bits : 9 - 9 (1 bit)
access : read-write

RESUME_IRQ : no description available
bits : 10 - 10 (1 bit)
access : read-write

ENIRQDEVPLUGIN : no description available
bits : 11 - 11 (1 bit)
access : read-write

DEVPLUGIN_IRQ : no description available
bits : 12 - 12 (1 bit)
access : read-write

DATA_ON_LRADC : no description available
bits : 13 - 13 (1 bit)
access : read-write

ENUTMILEVEL2 : no description available
bits : 14 - 14 (1 bit)
access : read-write

ENUTMILEVEL3 : no description available
bits : 15 - 15 (1 bit)
access : read-write

ENIRQWAKEUP : no description available
bits : 16 - 16 (1 bit)
access : read-write

WAKEUP_IRQ : no description available
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : no description available
bits : 18 - 18 (1 bit)
access : read-write

ENAUTOCLR_CLKGATE : no description available
bits : 19 - 19 (1 bit)
access : read-write

ENAUTOCLR_PHY_PWD : no description available
bits : 20 - 20 (1 bit)
access : read-write

ENDPDMCHG_WKUP : no description available
bits : 21 - 21 (1 bit)
access : read-write

ENIDCHG_WKUP : no description available
bits : 22 - 22 (1 bit)
access : read-write

ENVBUSCHG_WKUP : no description available
bits : 23 - 23 (1 bit)
access : read-write

FSDLL_RST_EN : no description available
bits : 24 - 24 (1 bit)
access : read-write

RESERVED : no description available
bits : 25 - 25 (1 bit)
access : read-write

RESERVED : no description available
bits : 26 - 26 (1 bit)
access : read-write

OTG_ID_VALUE : no description available
bits : 27 - 27 (1 bit)
access : read-write

HOST_FORCE_LS_SE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write

UTMI_SUSPENDM : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

SFTRST : no description available
bits : 31 - 31 (1 bit)
access : read-write


PWD_SET

USB PHY Power-Down Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD_SET PWD_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.

End of enumeration elements list.

TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Nornal operation.

#1 : 1

Powerdown the USB PHY transmit V-to-I converter and the current mirror.

End of enumeration elements list.

RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only


STATUS

USB PHY Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 HOSTDISCONDETECT_STATUS RSVD1 DEVPLUGIN_STATUS RSVD2 OTGID_STATUS RSVD3 RESUME_STATUS RSVD4

RSVD0 : no description available
bits : 0 - 2 (3 bit)
access : read-only

HOSTDISCONDETECT_STATUS : no description available
bits : 3 - 3 (1 bit)
access : read-write

RSVD1 : no description available
bits : 4 - 5 (2 bit)
access : read-only

DEVPLUGIN_STATUS : no description available
bits : 6 - 6 (1 bit)
access : read-write

RSVD2 : no description available
bits : 7 - 7 (1 bit)
access : read-only

OTGID_STATUS : no description available
bits : 8 - 8 (1 bit)
access : read-write

RSVD3 : no description available
bits : 9 - 9 (1 bit)
access : read-only

RESUME_STATUS : no description available
bits : 10 - 10 (1 bit)
access : read-write

RSVD4 : no description available
bits : 11 - 31 (21 bit)
access : read-only


DEBUG

USB PHY Debug Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG DEBUG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only


DEBUG_SET

USB PHY Debug Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_SET DEBUG_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only


DEBUG_CLR

USB PHY Debug Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_CLR DEBUG_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only


DEBUG_TOG

USB PHY Debug Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_TOG DEBUG_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTGIDPIOLOCK DEBUG_INTERFACE_HOLD HSTPULLDOWN ENHSTPULLDOWN RSVD0 TX2RXCOUNT ENTX2RXCOUNT RSVD1 SQUELCHRESETCOUNT RSVD2 ENSQUELCHRESET SQUELCHRESETLENGTH HOST_RESUME_DEBUG CLKGATE RSVD3

OTGIDPIOLOCK : no description available
bits : 0 - 0 (1 bit)
access : read-write

DEBUG_INTERFACE_HOLD : no description available
bits : 1 - 1 (1 bit)
access : read-write

HSTPULLDOWN : no description available
bits : 2 - 3 (2 bit)
access : read-write

ENHSTPULLDOWN : no description available
bits : 4 - 5 (2 bit)
access : read-write

RSVD0 : no description available
bits : 6 - 7 (2 bit)
access : read-only

TX2RXCOUNT : no description available
bits : 8 - 11 (4 bit)
access : read-write

ENTX2RXCOUNT : no description available
bits : 12 - 12 (1 bit)
access : read-write

RSVD1 : no description available
bits : 13 - 15 (3 bit)
access : read-only

SQUELCHRESETCOUNT : no description available
bits : 16 - 20 (5 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 23 (3 bit)
access : read-only

ENSQUELCHRESET : no description available
bits : 24 - 24 (1 bit)
access : read-write

SQUELCHRESETLENGTH : no description available
bits : 25 - 28 (4 bit)
access : read-write

HOST_RESUME_DEBUG : no description available
bits : 29 - 29 (1 bit)
access : read-write

CLKGATE : no description available
bits : 30 - 30 (1 bit)
access : read-write

RSVD3 : no description available
bits : 31 - 31 (1 bit)
access : read-only


DEBUG0_STATUS

UTMI Debug Status Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG0_STATUS DEBUG0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOP_BACK_FAIL_COUNT UTMI_RXERROR_FAIL_COUNT SQUELCH_COUNT

LOOP_BACK_FAIL_COUNT : no description available
bits : 0 - 15 (16 bit)
access : read-write

UTMI_RXERROR_FAIL_COUNT : no description available
bits : 16 - 25 (10 bit)
access : read-write

SQUELCH_COUNT : no description available
bits : 26 - 31 (6 bit)
access : read-write


DEBUG1

UTMI Debug Status Register 1
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1 DEBUG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only

ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only


DEBUG1_SET

UTMI Debug Status Register 1
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1_SET DEBUG1_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only

ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only


DEBUG1_CLR

UTMI Debug Status Register 1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1_CLR DEBUG1_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only

ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only


DEBUG1_TOG

UTMI Debug Status Register 1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG1_TOG DEBUG1_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 ENTAILADJVD RSVD1

RSVD0 : no description available
bits : 0 - 12 (13 bit)
access : read-only

ENTAILADJVD : no description available
bits : 13 - 14 (2 bit)
access : read-write

RSVD1 : no description available
bits : 15 - 31 (17 bit)
access : read-only


PWD_CLR

USB PHY Power-Down Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD_CLR PWD_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.

End of enumeration elements list.

TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Nornal operation.

#1 : 1

Powerdown the USB PHY transmit V-to-I converter and the current mirror.

End of enumeration elements list.

RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only


VERSION

UTMI RTL Version
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEP MINOR MAJOR

STEP : no description available
bits : 0 - 15 (16 bit)
access : read-only

MINOR : no description available
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : no description available
bits : 24 - 31 (8 bit)
access : read-only


IP

USB PHY IP Block Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP IP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_POWER PLL_LOCKED EN_USB_CLKS RSVD0 RESERVED RESERVED RESERVED RSVD1

PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write

PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write

EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write

RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write


IP_SET

USB PHY IP Block Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP_SET IP_SET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_POWER PLL_LOCKED EN_USB_CLKS RSVD0 RESERVED RESERVED RESERVED RSVD1

PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write

PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write

EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write

RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write


IP_CLR

USB PHY IP Block Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP_CLR IP_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_POWER PLL_LOCKED EN_USB_CLKS RSVD0 RESERVED RESERVED RESERVED RSVD1

PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write

PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write

EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write

RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write


IP_TOG

USB PHY IP Block Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP_TOG IP_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_POWER PLL_LOCKED EN_USB_CLKS RSVD0 RESERVED RESERVED RESERVED RSVD1

PLL_POWER : no description available
bits : 0 - 0 (1 bit)
access : read-write

PLL_LOCKED : no description available
bits : 1 - 1 (1 bit)
access : read-write

EN_USB_CLKS : no description available
bits : 2 - 2 (1 bit)
access : read-write

RSVD0 : no description available
bits : 3 - 15 (13 bit)
access : read-only

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 16 - 16 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 17 - 17 (1 bit)
access : read-write

RESERVED : Setting this bit will not guarantee chip functionality.
bits : 18 - 18 (1 bit)
access : read-write

RSVD1 : no description available
bits : 19 - 31 (13 bit)
access : read-write


PWD_TOG

USB PHY Power-Down Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWD_TOG PWD_TOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD0 TXPWDFS TXPWDIBIAS TXPWDV2I RSVD1 RXPWDENV RXPWD1PT1 RXPWDDIFF RXPWDRX RSVD2

RSVD0 : no description available
bits : 0 - 9 (10 bit)
access : read-only

TXPWDFS : no description available
bits : 10 - 10 (1 bit)
access : read-write

TXPWDIBIAS : This bit can power-down the USB PHY current bias block for the transmitter.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path.

End of enumeration elements list.

TXPWDV2I : This bit is used to powerdown the USB PHY transmit V-to-I converter and the current mirror.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Nornal operation.

#1 : 1

Powerdown the USB PHY transmit V-to-I converter and the current mirror.

End of enumeration elements list.

RSVD1 : no description available
bits : 13 - 16 (4 bit)
access : read-only

RXPWDENV : no description available
bits : 17 - 17 (1 bit)
access : read-write

RXPWD1PT1 : no description available
bits : 18 - 18 (1 bit)
access : read-write

RXPWDDIFF : no description available
bits : 19 - 19 (1 bit)
access : read-write

RXPWDRX : no description available
bits : 20 - 20 (1 bit)
access : read-write

RSVD2 : no description available
bits : 21 - 31 (11 bit)
access : read-only



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