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WKPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NSR

WISR

IRER

WRER

WIREER

WIFEER

WIFER

WIPUER

NCR


NSR

NMI Status Flag Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSR NSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED NOVF0 NIF0

RESERVED : no description available
bits : 0 - 5 (6 bit)
access : read-only

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

RESERVED : no description available
bits : 8 - 13 (6 bit)
access : read-only

RESERVED : no description available
bits : 14 - 15 (2 bit)
access : read-only

RESERVED : no description available
bits : 16 - 21 (6 bit)
access : read-only

RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only

RESERVED : no description available
bits : 24 - 29 (6 bit)
access : read-only

NOVF0 : no description available
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

No overrun has occurred on NMI input 0

#1 : 1

An overrun has occurred on NMI input 0

End of enumeration elements list.

NIF0 : no description available
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

No event has occurred on the pad

#1 : 1

An event as defined by NREE0 and NFEE0 has occurred

End of enumeration elements list.


WISR

Wakeup/Interrupt Status Flag Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WISR WISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIF

EIF : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

No event has occurred on the pad

#1 : 1

An event as defined by WIREER and WIFEER has occurred

End of enumeration elements list.


IRER

Interrupt Request Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRER IRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIRE

EIRE : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt requests from the corresponding EIF[x] bit are disabled

#1 : 1

A set EIF[x] bit causes an interrupt request

End of enumeration elements list.


WRER

Wakeup Request Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRER WRER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRE

WRE : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

System wakeup requests from the corresponding EIF[x] bit are disabled

#1 : 1

A set EIF[x] bit causes a system wakeup request

End of enumeration elements list.


WIREER

Wakeup/Interrupt Rising-Edge Event Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIREER WIREER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IREE

IREE : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Rising-edge event is disabled

#1 : 1

Rising-edge event is enabled

End of enumeration elements list.


WIFEER

Wakeup/Interrupt Falling-Edge Event Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIFEER WIFEER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFEEx

IFEEx : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#1 : 1

Falling-edge event is enabled

#0 : 0

Falling-edge event is disabled

End of enumeration elements list.


WIFER

Wakeup/Interrupt Filter Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIFER WIFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFE

IFE : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Filter is disabled

#1 : 1

Filter is enabled

End of enumeration elements list.


WIPUER

Wakeup/Interrupt Pullup Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WIPUER WIPUER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPUE

IPUE : no description available
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Pullup is disabled

#1 : 1

Pullup is enabled

End of enumeration elements list.


NCR

NMI Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NCR NCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED NFE0 NFEE0 NREE0 RESERVED NWRE0 NDSS0 NLOCK0

RESERVED : no description available
bits : 0 - 23 (24 bit)
access : read-only

NFE0 : no description available
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Filter is disabled

#1 : 1

Filter is enabled

End of enumeration elements list.

NFEE0 : no description available
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Falling-edge event is disabled

#1 : 1

Falling-edge event is enabled

End of enumeration elements list.

NREE0 : no description available
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Rising-edge event is disabled

#1 : 1

Rising-edge event is enabled

End of enumeration elements list.

RESERVED : no description available
bits : 27 - 27 (1 bit)
access : read-only

NWRE0 : no description available
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

System wakeup requests from the corresponding NIF0 bit are disabled

#1 : 1

A set NIF0 bit or set NOVF0 bit causes a system wakeup request

End of enumeration elements list.

NDSS0 : no description available
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

#00 : 00

non-maskable interrupt

#01 : 01

Reserved

#10 : 10

Reserved

#11 : 11

Reserved

End of enumeration elements list.

NLOCK0 : no description available
bits : 31 - 31 (1 bit)
access : read-write



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