\n

LS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IRQEN

LS1_TRIM

PWMSRCSEL

LS2_TRIM

CTRL

IRQS

IRQCLR


IRQEN

Low Side Driver Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQEN IRQEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_OT_PREWARN_IEN LS1_OT_IEN LS1_OL_IEN LS1_OC_IEN LS2_OT_PREWARN_IEN LS2_OT_IEN LS2_OL_IEN LS2_OC_IEN

LS1_OT_PREWARN_IEN : Low-Side 1 Overtemperature prewarn interrupt enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : disabled

None

0b1 : enable

None

End of enumeration elements list.

LS1_OT_IEN : Low-Side 1 Overtemperature interrupt enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : disabled

None

0b1 : enable

None

End of enumeration elements list.

LS1_OL_IEN : Low-Side 1 Open Load interrupt enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS1_OC_IEN : Low-Side 1 Overcurrent interrupt enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS2_OT_PREWARN_IEN : Low-Side 2 Overtemperature prewarn interrupt enable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : disabled

None

0b1 : enable

None

End of enumeration elements list.

LS2_OT_IEN : Low-Side 2 Overtemperature interrupt enable
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

0b0 : disabled

None

0b1 : enable

None

End of enumeration elements list.

LS2_OL_IEN : Low-Side 2 Open Load interrupt enable
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

LS2_OC_IEN : Low-Side 2 Overcurrent interrupt enable
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.


LS1_TRIM

Low Side Trimming Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LS1_TRIM LS1_TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_OL_BTFILT_SEL LS1_OC_BTFILT_SEL

LS1_OL_BTFILT_SEL : Open load Blank Time Select for LS1
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.

LS1_OC_BTFILT_SEL : Overcurrent BlankTime Select for LS1
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.


PWMSRCSEL

Low Side PWM Source Selection Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMSRCSEL PWMSRCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS2_SRC_SEL LS1_SRC_SEL

LS2_SRC_SEL : LS2 PWM Source Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0b0000 : CC60

PWM output of CCU6

0b0001 : CC61

PWM output of CCU6

0b0010 : CC62

PWM output of CCU6

0b0011 : COUT60

PWM output of CCU6

0b0100 : COUT61

PWM output of CCU6

0b0101 : COUT62

PWM output of CCU6

0b0110 : T3OUT

PWM output of GPT12

End of enumeration elements list.

LS1_SRC_SEL : LS1 PWM Source Selection
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0b0000 : CC60

PWM output of CCU6

0b0001 : CC61

PWM output of CCU6

0b0010 : CC62

PWM output of CCU6

0b0011 : COUT60

PWM output of CCU6

0b0100 : COUT61

PWM output of CCU6

0b0101 : COUT62

PWM output of CCU6

0b0110 : T3OUT

PWM output of GPT12

End of enumeration elements list.


LS2_TRIM

Low Side Trimming Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LS2_TRIM LS2_TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS2_OL_BTFILT_SEL LS2_OC_BTFILT_SEL

LS2_OL_BTFILT_SEL : Open load Blank Time Select for LS2
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.

LS2_OC_BTFILT_SEL : Overcurrent BlankTime Select for LS2
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.


CTRL

Low Side Driver Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_EN LS1_PWM LS1_ON LS1_OL_EN LS1_SRCTL_SEL LS2_EN LS2_PWM LS2_ON LS2_OL_EN LS2_SRCTL_SEL

LS1_EN : Low-Side switch 1 Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables LS1

0b1 : ENABLE

enables LS1

End of enumeration elements list.

LS1_PWM : Low-Side switch 1 PWM Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

normal mode controlled by LS1_ON

0b1 : ENABLE

enables LS1 for PWM mode

End of enumeration elements list.

LS1_ON : Low-Side switch 1 On/Off
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

switches LS1 off

0b1 : ON

turns on LS1

End of enumeration elements list.

LS1_OL_EN : Open load Detection Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Open load detection

0b1 : ENABLE

Open load detection

End of enumeration elements list.

LS1_SRCTL_SEL : Low-Side switch 1 Slew Rate selection
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : Slow

slow slew rate is selected

0b1 : Fast

fast slew rate is selected

End of enumeration elements list.

LS2_EN : Low-Side switch 2 Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables LS2

0b1 : ENABLE

enables LS2

End of enumeration elements list.

LS2_PWM : Low-Side switch 2 PWM Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

normal mode controlled by LS2_ON

0b1 : ENABLE

enables LS2 for PWM mode

End of enumeration elements list.

LS2_ON : Low-Side switch 2 On/Off
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

switches LS2 off

0b1 : ON

turns on LS2

End of enumeration elements list.

LS2_OL_EN : Open load Detection Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Open load detection

0b1 : ENABLE

Open load detection

End of enumeration elements list.

LS2_SRCTL_SEL : Low-Side switch 2 Slew Rate selection
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : Slow

slow slew rate is selected

0b1 : Fast

fast slew rate is selected

End of enumeration elements list.


IRQS

Low Side Driver Interrupt Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQS IRQS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_OT_PREWARN_IS LS1_OT_IS LS1_OL_IS LS1_OC_IS LS1_OT_PREWARN_STS LS1_OT_STS LS1_OL_STS LS2_OT_PREWARN_IS LS2_OT_IS LS2_OL_IS LS2_OC_IS LS2_OT_PREWARN_STS LS2_OT_STS LS2_OL_STS

LS1_OT_PREWARN_IS : Low-Side 1 Overtemperature Prewarning Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature Prewarn

no overtemperature prewarn occurred.

0b1 : Overtemperature Prewarn

overtemperature prewarn occurred. Write sets status

End of enumeration elements list.

LS1_OT_IS : Low-Side 1 Overtemperature Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature

no overtemperature occurred.

0b1 : Overtemperature

overtemperature occurred switch is automatically shutdown. Write sets status

End of enumeration elements list.

LS1_OL_IS : Low-Side 1 Open Load Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : no Open Load

no open load Condition occurred.

0b1 : Open Load

open load occurred switch is not automatically shutdown. Write sets status.

End of enumeration elements list.

LS1_OC_IS : Low-Side 1 Overcurrent Interrupt Status
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : no Overcurrent

no overcurrent Condition occurred.

0b1 : Overcurrent

overcurrent occurred switch is automatically shutdown. Write sets status.

End of enumeration elements list.

LS1_OT_PREWARN_STS : Low-Side 1 Overtemperature Prewarning Status
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature Prewarn

no overtemperature prewarn occurred.

0b1 : Overtemperature

overtemperature prewarn occurred Write sets status

End of enumeration elements list.

LS1_OT_STS : Low-Side 1 Overtemperature Status
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature

no overtemperature occurred.

0b1 : Overtemperature

overtemperature occurred switch is automatically shutdown. Write sets status

End of enumeration elements list.

LS1_OL_STS : Low-Side 1 Open Load Status
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : no Open Load

no open load Condition occurred.

0b1 : Open Load

open load occurred switch is not automatically shutdown. Write sets status.

End of enumeration elements list.

LS2_OT_PREWARN_IS : Low-Side 2 Overtemperature Prewarning Interrupt Status
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature Prewarn

no overtemperature prewarn occurred.

0b1 : Overtemperature Prewarn

overtemperature prewarn occurred. Write sets status

End of enumeration elements list.

LS2_OT_IS : Low-Side 2 Overtemperature Interrupt Status
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature

no overtemperature occurred.

0b1 : Overtemperature

overtemperature occurred switch is automatically shutdown. Write sets status

End of enumeration elements list.

LS2_OL_IS : Low-Side 2 Open Load Interrupt Status
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : no Open Load

no open load Condition occurred.

0b1 : Open Load

open load occurred switch is not automatically shutdown. Write sets status.

End of enumeration elements list.

LS2_OC_IS : Low-Side 2 Overcurrent Interrupt Status
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

0b0 : no Overcurrent

no overcurrent Condition occurred.

0b1 : Overcurrent

overcurrent occurred switch is automatically shutdown. Write sets status.

End of enumeration elements list.

LS2_OT_PREWARN_STS : Low-Side 2 Overtemperature Prewarning Status
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature Prewarn

no overtemperature prewarn occurred.

0b1 : Overtemperature

overtemperature prewarn occurred Write sets status

End of enumeration elements list.

LS2_OT_STS : Low-Side 2 Overtemperature Status
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature

no overtemperature occurred.

0b1 : Overtemperature

overtemperature occurred switch is automatically shutdown. Write sets status

End of enumeration elements list.

LS2_OL_STS : Low-Side 2 Open Load Status
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

0b0 : no Open Load

no open load Condition occurred.

0b1 : Open Load

open load occurred switch is not automatically shutdown. Write sets status.

End of enumeration elements list.


IRQCLR

Low Side Driver Interrupt Status Register Clear
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCLR IRQCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_OT_PREWARN_ISC LS1_OT_ISC LS1_OL_ISC LS1_OC_ISC LS1_OT_PREWARN_SC LS1_OT_SC LS1_OL_SC LS2_OT_PREWARN_ISC LS2_OT_ISC LS2_OL_ISC LS2_OC_ISC LS2_OT_PREWARN_SC LS2_OT_SC LS2_OL_SC

LS1_OT_PREWARN_ISC : Low-Side 1 Overtemperature prewarn interrupt status clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS1_OT_ISC : Low-Side 1 Overtemperature interrupt status clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS1_OL_ISC : Low-Side 1 Open Load interrupt status clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS1_OC_ISC : Low-Side 1 Overcurrent interrupt status clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS1_OT_PREWARN_SC : Low-Side 1 Overtemperature prewarn status clear
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS1_OT_SC : Low-Side 1 Overtemperature status clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS1_OL_SC : Low-Side 1 Open Load status clear
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS2_OT_PREWARN_ISC : Low-Side 2Overtemperature prewarn interrupt status clear
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS2_OT_ISC : Low-Side 2 Overtemperature interrupt status clear
bits : 21 - 20 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS2_OL_ISC : Low-Side 2 Open Load interrupt status clear
bits : 22 - 21 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

LS2_OC_ISC : Low-Side 2 Overcurrent interrupt status clear
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS2_OT_PREWARN_SC : Low-Side 2 Overtemperature prewarn status clear
bits : 28 - 27 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS2_OT_SC : Low-Side switch 2 Overtemperature status Clear
bits : 29 - 28 (0 bit)
access : write-only

Enumeration:

0x0 : No Clear

None

0x1 : Clear

None

End of enumeration elements list.

LS2_OL_SC : Low-Side 2 Open Load status clear
bits : 30 - 29 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.



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