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SCUPM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

AMCLK_FREQ_STS

SYS_ISCLR

SYS_IS

SYS_SUPPLY_IRQ_STS

SYS_SUPPLY_IRQ_CTRL

SYS_SUPPLY_IRQ_CLR

SYS_IRQ_CTRL

PCU_CTRL_STS

WDT1_TRIG

AMCLK_CTRL

STCALIB

AMCLK_TH_HYS


AMCLK_FREQ_STS

Analog Module Clock Frequency Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMCLK_FREQ_STS AMCLK_FREQ_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMCLK1_FREQ AMCLK2_FREQ

AMCLK1_FREQ : Current frequency of Analog Module Clock System Clock (MI_CLK)
bits : 0 - 4 (5 bit)
access : read-only

AMCLK2_FREQ : Current frequency of Analog Module Clock 2 (TFILT_CLK)
bits : 8 - 12 (5 bit)
access : read-only


SYS_ISCLR

System Interrupt Status Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_ISCLR SYS_ISCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS_OTWARN_ISC SYS_OT_ISC REFBG_LOTHWARN_ISC REFBG_UPTHWARN_ISC SYS_OTWARN_SC SYS_OT_SC

SYS_OTWARN_ISC : System Overtemperature Prewarning status clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

SYS_OT_ISC : System Overtemperature Shutdown status clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

REFBG_LOTHWARN_ISC : 8-Bit ADC2 Reference Undervoltage interrupt status clear
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

REFBG_UPTHWARN_ISC : 8-Bit ADC2 Reference Overvoltage interrupt status clear
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

SYS_OTWARN_SC : System Overtemperature Prewarning status clear
bits : 24 - 23 (0 bit)
access : write-only

Enumeration:

0b0 : No CLear

None

0b1 : Clear

None

End of enumeration elements list.

SYS_OT_SC : System Overtemperature Shutdown status clear
bits : 25 - 24 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.


SYS_IS

System Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IS SYS_IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_FAIL_IS LS2_FAIL_IS HS1_FAIL_IS HS2_FAIL_IS LIN_FAIL_IS SYS_OTWARN_IS SYS_OT_IS REFBG_LOTHWARN_IS REFBG_UPTHWARN_IS LS1_FAIL_STS LS2_FAIL_STS HS1_FAIL_STS HS2_FAIL_STS LIN_FAIL_STS SYS_OTWARN_STS SYS_OT_STS

LS1_FAIL_IS : Low Side Driver 1 Fail Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

LS2_FAIL_IS : Low Side Driver 2 Fail Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

HS1_FAIL_IS : High Side Driver 1 Fail Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

HS2_FAIL_IS : High Side Driver 2 Fail Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

LIN_FAIL_IS : LIN Fail Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

SYS_OTWARN_IS : System Overtemperature Prewarning (ADC2, Channel 6) interrupt status
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

SYS_OT_IS : System Overtemperature Shutdown (ADC2, Channel 6) interrupt status
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

REFBG_LOTHWARN_IS : 8-Bit ADC2 Reference Undervoltage (ADC2, Channel 3) interrupt status
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

REFBG_UPTHWARN_IS : 8-Bit ADC2 Reference Overvoltage (ADC2, Channel 3) interrupt status
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

LS1_FAIL_STS : Low Side Driver 1 Fail Status
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

LS2_FAIL_STS : Low Side Driver 2 Fail Status
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

HS1_FAIL_STS : High Side Driver 1 Fail Status
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

HS2_FAIL_STS : High Side Driver 2 Fail Status
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

LIN_FAIL_STS : LIN Fail Status
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

SYS_OTWARN_STS : System Overtemperature Prewarning (ADC2, Channel 6) status
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.

SYS_OT_STS : System Overtemperature Shutdown (ADC2, Channel 6) status
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : INACTIVE

no status set

0b1 : ACTIVE

at least one status set

End of enumeration elements list.


SYS_SUPPLY_IRQ_STS

System Supply Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SUPPLY_IRQ_STS SYS_SUPPLY_IRQ_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT_UV_IS VS_UV_IS VDD5V_UV_IS VDD1V5_UV_IS VDDEXT_UV_IS VBAT_OV_IS VS_OV_IS VDD5V_OV_IS VDD1V5_OV_IS VDDEXT_OV_IS VBAT_UV_STS VS_UV_STS VDD5V_UV_STS VDD1V5_UV_STS VDDEXT_UV_STS VBAT_OV_STS VS_OV_STS VDD5V_OV_STS VDD1V5_OV_STS VDDEXT_OV_STS

VBAT_UV_IS : VBAT Undervoltage Interrupt Status
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage Interrupt

occurred

0b1 : Undervoltage Interrupt

occurred

End of enumeration elements list.

VS_UV_IS : VS Undervoltage Interrupt Status
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage Interrupt

occurred

0b1 : Undervoltage Interrupt

occurred

End of enumeration elements list.

VDD5V_UV_IS : VDDP Undervoltage Interrupt Status
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage Interrupt

occurred

0b1 : Undervoltage Interrupt

occurred

End of enumeration elements list.

VDD1V5_UV_IS : VDDC Undervoltage Interrupt Status
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage Interrupt

occurred

0b1 : Undervoltage Interrupt

occurred

End of enumeration elements list.

VDDEXT_UV_IS : VDDEXT Undervoltage Interrupt Status
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage Interrupt

occurred

0b1 : Undervoltage Interrupt

occurred

End of enumeration elements list.

VBAT_OV_IS : VBAT Overvoltage Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage Interrupt

occurred

0b1 : Overvoltage Interrupt

occurred

End of enumeration elements list.

VS_OV_IS : VS Overvoltage Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage Interrupt

occurred

0b1 : Overvoltage Interrupt

occurred

End of enumeration elements list.

VDD5V_OV_IS : VDDP Overvoltage Interrupt Status
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage Interrupt

occurred

0b1 : Overvoltage Interrupt

occurred

End of enumeration elements list.

VDD1V5_OV_IS : VDDC Overvoltage Interrupt Status
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage Interrupt

occurred

0b1 : Overvoltage Interrupt

occurred

End of enumeration elements list.

VDDEXT_OV_IS : VDDEXT Overvoltage Interrupt Status
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage Interrupt

occurred

0b1 : Overvoltage Interrupt

occurred

End of enumeration elements list.

VBAT_UV_STS : VBAT Undervoltage Status
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VS_UV_STS : VS Undervoltage Status
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDD5V_UV_STS : VDDP Undervoltage Status
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDD1V5_UV_STS : VDDC Undervoltage Status
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDDEXT_UV_STS : VDDEXT Undervoltage Status
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : No Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VBAT_OV_STS : VBAT Overvoltage Status
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VS_OV_STS : VS Overvoltage Status
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDD5V_OV_STS : VDDP Overvoltage Status
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDD1V5_OV_STS : VDDC Overvoltage Status
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDDEXT_OV_STS : VDDEXT Overvoltage Status
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : No Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.


SYS_SUPPLY_IRQ_CTRL

System Supply Interrupt Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SUPPLY_IRQ_CTRL SYS_SUPPLY_IRQ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT_UV_IE VS_UV_IE VDD5V_UV_IE VDD1V5_UV_IE VDDEXT_UV_IE VBAT_OV_IE VS_OV_IE VDD5V_OV_IE VDD1V5_OV_IE VDDEXT_OV_IE

VBAT_UV_IE : VBAT Undervoltage Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VS_UV_IE : VS Undervoltage Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD5V_UV_IE : VDDP Undervoltage Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD1V5_UV_IE : VDDC Undervoltage Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDDEXT_UV_IE : VDDEXT Undervoltage Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VBAT_OV_IE : VBAT Overvoltage Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VS_OV_IE : VS Overvoltage Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD5V_OV_IE : VDDP Overvoltage Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD1V5_OV_IE : VDDC Overvoltage Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDDEXT_OV_IE : VDDEXT Overvoltage Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.


SYS_SUPPLY_IRQ_CLR

System Supply Interrupt Status Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SUPPLY_IRQ_CLR SYS_SUPPLY_IRQ_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT_UV_ISC VS_UV_ISC VDD5V_UV_ISC VDD1V5_UV_ISC VDDEXT_UV_ISC VBAT_OV_ISC VS_OV_ISC VDD5V_OV_ISC VDD1V5_OV_ISC VDDEXT_OV_ISC VBAT_UV_SC VS_UV_SC VDD5V_UV_SC VDD1V5_UV_SC VDDEXT_UV_SC VBAT_OV_SC VS_OV_SC VDD5V_OV_SC VDD1V5_OV_SC VDDEXT_OV_SC

VBAT_UV_ISC : VBAT Undervoltage Interrupt Status clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VS_UV_ISC : VS Undervoltage Interrupt Status clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD5V_UV_ISC : VDDP Undervoltage Interrupt Status clear
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD1V5_UV_ISC : VDDC Undervoltage Interrupt Status clear
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDDEXT_UV_ISC : VDDEXT Undervoltage Interrupt Status clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VBAT_OV_ISC : VBAT Overvoltage Interrupt Status clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VS_OV_ISC : VS Overvoltage Interrupt Status clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD5V_OV_ISC : VDDP Overvoltage Interrupt Status clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD1V5_OV_ISC : VDDC Overvoltage Interrupt Status clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDDEXT_OV_ISC : VDDEXT Overvoltage Interrupt Status clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VBAT_UV_SC : VBAT Undervoltage Status clear
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VS_UV_SC : VS Undervoltage Status clear
bits : 17 - 16 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD5V_UV_SC : VDDP Undervoltage Status clear
bits : 18 - 17 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD1V5_UV_SC : VDDC Undervoltage Status clear
bits : 19 - 18 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDDEXT_UV_SC : VDDEXT Undervoltage Status clear
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VBAT_OV_SC : VBAT Overvoltage Status clear
bits : 21 - 20 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VS_OV_SC : VS Overvoltage Status clear
bits : 22 - 21 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD5V_OV_SC : VDDP Overvoltage Status clear
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDD1V5_OV_SC : VDDC Overvoltage Status clear
bits : 24 - 23 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.

VDDEXT_OV_SC : VDDEXT Overvoltage Status clear
bits : 25 - 24 (0 bit)
access : write-only

Enumeration:

0b0 : No Clear

None

0b1 : Clear

None

End of enumeration elements list.


SYS_IRQ_CTRL

System Interrupt Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IRQ_CTRL SYS_IRQ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS_OTWARN_IE SYS_OT_IE REFBG_LOTHWARN_IE REFBG_UPTHWARN_IE

SYS_OTWARN_IE : System Overtemperature Warning Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

SYS_OT_IE : System Overtemperature Shutdown Interrupt Enable (leads to shutdown of System)
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

REFBG_LOTHWARN_IE : Reference Voltage Undervoltage Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

REFBG_UPTHWARN_IE : Reference Voltage Overvoltage Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.


PCU_CTRL_STS

Power Control Unit Control Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCU_CTRL_STS PCU_CTRL_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKWDT_SD_DIS LIN_VS_UV_SD_DIS

CLKWDT_SD_DIS : Power Modules Clock Watchdog Shutdown Disable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : Shutdown Enable

Power Devices will be switched off when Clock Watchdog occurs

0b1 : Shutdown Disable

Power Devices will not be shutdown when Clock Watchdog occurs

End of enumeration elements list.

LIN_VS_UV_SD_DIS : LIN Module VS Undervoltage Transmitter Shutdown
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Automatic Shutdown for Power modules in case of VS Undervoltage enabled

0b1 : Disable

Automatic Shutdown for Power modules in case of VS Undervoltage disabled

End of enumeration elements list.


WDT1_TRIG

WDT1 Watchdog Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDT1_TRIG WDT1_TRIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDP_SEL SOWCONF

WDP_SEL : Watchdog Period Selection and trigger
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x00 : SOW_TRIG

trigger short open window

0x01 : WP_1

Watchdog period 16 ms

0x02 : WP_2

Watchdog period 32 ms

0x03 : WP_3

Watchdog period 48 ms

0x3F : WP_63

Watchdog period 1008 ms

End of enumeration elements list.

SOWCONF : Short Open Window Configuration
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0x0 : DIS

Short Open Windows disabled

0x1 : SOW1

one successive Short Open Window allowed

0x2 : SOW2

two successive Short Open Windows allowed

0x3 : SOW3

three successive Short Open Windows allowed

End of enumeration elements list.


AMCLK_CTRL

Analog Module Clock Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMCLK_CTRL AMCLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKWDT_PD_N

CLKWDT_PD_N : Clock Watchdog Powerdown
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Clock Watchdog disabled

0b1 : ENABLE

Clock Watchdog enabled

End of enumeration elements list.


STCALIB

System Tick Calibration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCALIB STCALIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCALIB

STCALIB : System Tick Calibration
bits : 0 - 24 (25 bit)
access : read-write


AMCLK_TH_HYS

Analog Module Clock Limit Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMCLK_TH_HYS AMCLK_TH_HYS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMCLK1_UP_TH AMCLK1_UP_HYS AMCLK1_LOW_TH AMCLK1_LOW_HYS AMCLK2_UP_TH AMCLK2_UP_HYS AMCLK2_LOW_TH AMCLK2_LOW_HYS

AMCLK1_UP_TH : Analog Module Clock 1 (MI_CLK) Upper Limit Threshold
bits : 0 - 4 (5 bit)
access : read-write

AMCLK1_UP_HYS : Analog Module Clock 1 (MI_CLK) Upper Hysteresis
bits : 6 - 6 (1 bit)
access : read-write

AMCLK1_LOW_TH : Analog Module Clock 1 (MI_CLK) Lower Limit Threshold
bits : 8 - 12 (5 bit)
access : read-write

AMCLK1_LOW_HYS : Analog Module Clock 1 (MI_CLK) Lower Hysteresis
bits : 14 - 14 (1 bit)
access : read-write

AMCLK2_UP_TH : Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold
bits : 16 - 20 (5 bit)
access : read-write

AMCLK2_UP_HYS : Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis
bits : 22 - 22 (1 bit)
access : read-write

AMCLK2_LOW_TH : Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold
bits : 24 - 28 (5 bit)
access : read-write

AMCLK2_LOW_HYS : Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis
bits : 30 - 30 (1 bit)
access : read-write



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