\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Counter Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Counter disabled.
#1 : value2
Counter enabled.
End of enumeration elements list.
TICKINT : SysTick Exception Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Counting down to zero does not assert the SysTick exception request.
#1 : value2
Counting down to zero to assert the SysTick exception request.
End of enumeration elements list.
CLKSOURCE : Clock Source
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
External clock.
#1 : value2
Processor clock.
End of enumeration elements list.
COUNTFLAG : Counter Flag
bits : 16 - 15 (0 bit)
access : read-write
Interrupt Set-enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Node Set-enable
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
#0 : value1
Read: Interrupt node disabled. Write: No effect.
#1 : value2
Read: Interrupt node enabled. Write: Enable interrupt node
End of enumeration elements list.
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Reload Value
bits : 0 - 22 (23 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : SysTick Counter Current Value
bits : 0 - 22 (23 bit)
access : read-write
IInterrupt Clear-enable Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Node Clear-enable
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
#0 : value1
Read: Interrupt node disabled. Write: No effect
#1 : value2
Read: Interrupt node enabled. Write: Disable interrupt node.
End of enumeration elements list.
SysTick Calibration Value Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : 10 Milliseconds
bits : 0 - 22 (23 bit)
access : read-only
SKEW : Clock Skew
bits : 30 - 29 (0 bit)
access : read-only
NOREF : Reference Clock
bits : 31 - 30 (0 bit)
access : read-only
Interrupt Set-pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Node Set-pending
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
#0 : value1
Read: Interrupt node is not pending. Write: No effect
#1 : value2
Read: Interrupt node is pending. Write: Change interrupt state to pending.
End of enumeration elements list.
Interrupt Clear-pending Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt Node Clear-pending
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
#0 : value1
Read: Interrupt node is not pending. Write: No effect.
#1 : value2
Read: Interrupt node is pending. Write: Remove interrupt state from pending.
End of enumeration elements list.
Interrupt Priority Register 0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 1
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 2
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 3
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 4
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 5
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 6
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority Register 7
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority, Byte Offset 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_1 : Priority, Byte Offset 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_2 : Priority, Byte Offset 2
bits : 16 - 22 (7 bit)
access : read-write
PRI_3 : Priority, Byte Offset 3
bits : 24 - 30 (7 bit)
access : read-write
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Revision : Revision Number
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x0 : value1
Patch 0
End of enumeration elements list.
PartNo : Part Number of the Processor
bits : 4 - 14 (11 bit)
access : read-only
Enumeration:
0xC20 : value1
Cortex-M0
End of enumeration elements list.
Architecture : Architecture
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0xC : value1
ARMv6-M
End of enumeration elements list.
Variant : Variant Number
bits : 20 - 22 (3 bit)
access : read-only
Enumeration:
0x0 : value1
Revision 0
End of enumeration elements list.
Implementer : Implementer Code
bits : 24 - 30 (7 bit)
access : read-only
Enumeration:
0x41 : value1
ARM
End of enumeration elements list.
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active Exception Number
bits : 0 - 4 (5 bit)
access : read-only
Enumeration:
0x00 : value1
Thread mode
End of enumeration elements list.
VECTPENDING : Pending Exception Number
bits : 12 - 16 (5 bit)
access : read-only
Enumeration:
0x0 : value1
No pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt Pending Flag
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
#0 : value1
Interrupt not pending
#1 : value2
Interrupt pending.
End of enumeration elements list.
PENDSTCLR : SysTick Exception Clear-pending
bits : 25 - 24 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
removes the pending state from the SysTick exception.
End of enumeration elements list.
PENDSTSET : SysTick Exception Set-pending
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
0 : value1
SysTick exception is not pending
1 : value2
SysTick exception is pending.
End of enumeration elements list.
PENDSVCLR : PendSV Clear Pending
bits : 27 - 26 (0 bit)
access : write-only
Enumeration:
#0 : value1
Do not clear.
#1 : value2
Removes pending state from PendSV exception.
End of enumeration elements list.
PENDSVSET : PendSV Set Pending
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
PendSV exception is not pending.
#1 : value2
PendSV excepton is pending.
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSRESETREQ : System Reset Request
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Requests a system level reset.
End of enumeration elements list.
ENDIANNESS : Data Endianness
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
Little-endian
End of enumeration elements list.
VECTKEY : Register Key
bits : 16 - 30 (15 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-on-exit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Do not sleep when returning to Thread mode.
#1 : value2
Enter sleep, or deep sleep, on return from an ISR to Thread mode.
End of enumeration elements list.
SLEEPDEEP : Low Power Sleep Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Sleep
#1 : value2
Deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
#1 : value2
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
End of enumeration elements list.
Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNALIGN_TRP : Unaligned Access Traps
bits : 3 - 2 (0 bit)
access : read-only
STKALIGN : Stack Alignment
bits : 9 - 8 (0 bit)
access : read-only
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of System Handler 11
bits : 24 - 30 (7 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of System Handler 14
bits : 16 - 22 (7 bit)
access : read-write
PRI_15 : Priority of System Handler 15
bits : 24 - 30 (7 bit)
access : read-write
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVCALLPENDED : SVCall Pending bit
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
SVCall is not pending.
#1 : value2
SVCall is pending.
End of enumeration elements list.
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