Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
RCU Reset Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTSTAT : Reset Status Information
bits : 0 - 8 (9 bit)
access : read-only
LCKEN : Enable Lockup Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
Reset by Lockup disabled
#1 : value2
Reset by Lockup enabled
End of enumeration elements list.
RCU Reset Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCKEN : Enable Lockup Reset
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
Enable reset when Lockup gets asserted
End of enumeration elements list.
RCU Reset Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSCLR : Clear Reset Status
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
Clears field RSTSTAT.RSTSTAT
End of enumeration elements list.
LCKEN : Enable Lockup Reset
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
Disable reset when Lockup gets asserted
End of enumeration elements list.
RCU Reset Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECCRSTEN : Enable ECC Error Reset
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No reset when ECC double bit error occur
#1 : value2
Reset when ECC double bit error occur
End of enumeration elements list.
LOCRSTEN : Enable Loss of Clock Reset
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
No reset when loss of clock occur
#1 : value2
Reset when loss of clock occur
End of enumeration elements list.
SPERSTEN : Enable 16kbytes SRAM Parity Error Reset
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No reset when SRAM parity error occur
#1 : value2
Reset when SRAM parity error occur
End of enumeration elements list.
U0PERSTEN : Enable USIC0 SRAM Parity Error Reset
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
No reset when USIC0 memory parity error occur
#1 : value2
Reset when USIC0 memory parity error occur
End of enumeration elements list.
MRSTEN : Enable Master Reset
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Triggered Master reset
End of enumeration elements list.
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