Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
Global Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TM : Trigger Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Mode 0: BCCU trigger occurs if there is any channel trigger (OR logic)
#1 : value2
Mode 1: BCCU trigger occurs if there is a channel trigger event on the active channel. When this happens, the next trigger-enabled channel will be active following the round robin.
End of enumeration elements list.
TRDEL : Trigger Delay
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
No delay
#01 : value2
BCCU trigger occurs a quarter bit time after the channel trigger that caused it; only to be used if BCCU_GLOBCLK.BCS is 0
#10 : value3
BCCU trigger occurs half a bit time after the channel trigger that caused it; only to be used if BCCU_GLOBCLK.BCS is 0
#11 : value4
No delay
End of enumeration elements list.
SUSCFG : Suspend Mode Configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
Suspend request is ignored and the module cannot get suspended
#01 : value2
All channels stop running immediately and freeze in the last state without any safe stop
#10 : value3
All channels stop running immediately and freeze in the last state; all outputs go to passive state to achieve safe stop
End of enumeration elements list.
TRAPIS : Trap Input Pin Selector
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
#0000 : value1
BCCU.TRAPINA
#0001 : value2
BCCU.TRAPINB
#0010 : value3
BCCU.TRAPINC
#0011 : value4
BCCU.TRAPIND
#0100 : value5
BCCU.TRAPINE
#0101 : value6
BCCU.TRAPINF
#0110 : value7
BCCU.TRAPING
#0111 : value8
BCCU.TRAPINH
#1000 : value9
BCCU.TRAPINI
#1001 : value10
BCCU.TRAPING
#1010 : value11
BCCU.TRAPINK
#1011 : value12
BCCU.TRAPINL
#1100 : value13
BCCU.TRAPINM
#1101 : value14
BCCU.TRAPINN
#1110 : value15
BCCU.TRAPINO
#1111 : value16
BCCU.TRAPINP
End of enumeration elements list.
TRAPED : Trap Edge
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap occurs (trap flag is set) on rising edge of the BCCU.TRAPL signal
#1 : value2
Trap occurs (trap flag is set) on falling edge of the BCCU.TRAPL signal
End of enumeration elements list.
LTRS : Last Trigger Source
bits : 12 - 14 (3 bit)
access : read-only
Enumeration:
#0000 : value1
The last trigger occurred in channel turn 0
#0001 : value2
The last trigger occurred in channel turn 1
#0010 : value3
The last trigger occurred in channel turn 2
#0011 : value4
The last trigger occurred in channel turn 3
#0100 : value5
The last trigger occurred in channel turn 4
#0101 : value6
The last trigger occurred in channel turn 5
#0110 : value7
The last trigger occurred in channel turn 6
#0111 : value8
The last trigger occurred in channel turn 7
#1000 : value9
The last trigger occurred in channel turn 8
End of enumeration elements list.
WDMBN : Watchdog Maximum Bitnumber
bits : 16 - 26 (11 bit)
access : read-write
Channel Output Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OP : Channel 0 Output Passive Level
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH1OP : Channel 1 Output Passive Level
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH2OP : Channel 2 Output Passive Level
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH3OP : Channel 3 Output Passive Level
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH4OP : Channel 4 Output Passive Level
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH5OP : Channel 5 Output Passive Level
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH6OP : Channel 6 Output Passive Level
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH7OP : Channel 7 Output Passive Level
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH8OP : Channel 8 Output Passive Level
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
Active high
#1 : value2
Active low
End of enumeration elements list.
CH0TPE : Channel 0 Trap Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH1TPE : Channel 1 Trap Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH2TPE : Channel 2 Trap Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH3TPE : Channel 3 Trap Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH4TPE : Channel 4 Trap Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH5TPE : Channel 5 Trap Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH6TPE : Channel 6 Trap Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH7TPE : Channel 7 Trap Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
CH8TPE : Channel 8 Trap Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function on channel is disabled
#1 : value2
Trap function on channel is enabled, the output goes to passive level when trap occurs
End of enumeration elements list.
Channel Trigger
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ET0 : Channel 0 Trigger Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET1 : Channel 1 Trigger Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET2 : Channel 2 Trigger Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET3 : Channel 3 Trigger Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET4 : Channel 4 Trigger Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET5 : Channel 5 Trigger Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET6 : Channel 6 Trigger Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET7 : Channel 7 Trigger Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
ET8 : Channel 8 Trigger Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel trigger is disabled
#1 : value2
Channel trigger is enabled
End of enumeration elements list.
TOS0 : Channel 0 Trigger Output Select
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS1 : Channel 1 Trigger Output Select
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS2 : Channel 2 Trigger Output Select
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS3 : Channel 3 Trigger Output Select
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS4 : Channel 4 Trigger Output Select
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS5 : Channel 5 Trigger Output Select
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS6 : Channel 6 Trigger Output Select
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS7 : Channel 7 Trigger Output Select
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
TOS8 : Channel 8 Trigger Output Select
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
The channel trigger pulse will appear on BCCU_TRIGOUT0
#1 : value2
The channel trigger pulse will appear on BCCU_TRIGOUT1
End of enumeration elements list.
Channel Shadow Transfer
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0S : Channel 0 Shadow Transfer
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH1S : Channel 1 Shadow Transfer
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH2S : Channel 2 Shadow Transfer
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH3S : Channel 3 Shadow Transfer
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH4S : Channel 4 Shadow Transfer
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH5S : Channel 5 Shadow Transfer
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH6S : Channel 6 Shadow Transfer
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH7S : Channel 7 Shadow Transfer
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH8S : Channel 8 Shadow Transfer
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate channel y target intensity shadow transfer. The linear walk will start and channel y intensity will start to change towards the target. Cleared by hardware when the linear walk is complete and the target has been reached.
End of enumeration elements list.
CH0A : Channel 0 Linear Walk Abort
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH1A : Channel 1 Linear Walk Abort
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH2A : Channel 2 Linear Walk Abort
bits : 18 - 17 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH3A : Channel 3 Linear Walk Abort
bits : 19 - 18 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH4A : Channel 4 Linear Walk Abort
bits : 20 - 19 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH5A : Channel 5 Linear Walk Abort
bits : 21 - 20 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH6A : Channel 6 Linear Walk Abort
bits : 22 - 21 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH7A : Channel 7 Linear Walk Abort
bits : 23 - 22 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
CH8A : Channel 8 Linear Walk Abort
bits : 24 - 23 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort linear walk; CHyS is cleared, channel y intensity stops changing
End of enumeration elements list.
Last Trigger Channel Output Level
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTOL0 : Last Trigger Channel Output
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL1 : Last Trigger Channel Output
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL2 : Last Trigger Channel Output
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL3 : Last Trigger Channel Output
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL4 : Last Trigger Channel Output
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL5 : Last Trigger Channel Output
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL6 : Last Trigger Channel Output
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL7 : Last Trigger Channel Output
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
LTOL8 : Last Trigger Channel Output
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Passive
#1 : value2
Active
End of enumeration elements list.
Dimming Engine Enable
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDE0 : Dimming Engine 0 Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Dimming Engine is disabled; the output dimming level (DLz.DLEV) is reset to 0 when the dimming engine gets disabled
#1 : value2
Dimming Engine is enabled
End of enumeration elements list.
EDE1 : Dimming Engine 1 Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Dimming Engine is disabled; the output dimming level (DLz.DLEV) is reset to 0 when the dimming engine gets disabled
#1 : value2
Dimming Engine is enabled
End of enumeration elements list.
EDE2 : Dimming Engine 2 Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Dimming Engine is disabled; the output dimming level (DLz.DLEV) is reset to 0 when the dimming engine gets disabled
#1 : value2
Dimming Engine is enabled
End of enumeration elements list.
Dimming Shadow Transfer
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DE0S : Dimming Engine 0 Shadow Transfer
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate target dimming level shadow transfer. The dimming process will start and the dimming level will change towards the target. Cleared by hardware when the dimming process is complete and the target has been reached.
End of enumeration elements list.
DE1S : Dimming Engine 1 Shadow Transfer
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate target dimming level shadow transfer. The dimming process will start and the dimming level will change towards the target. Cleared by hardware when the dimming process is complete and the target has been reached.
End of enumeration elements list.
DE2S : Dimming Engine 2 Shadow Transfer
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No action
#1 : value2
Initiate target dimming level shadow transfer. The dimming process will start and the dimming level will change towards the target. Cleared by hardware when the dimming process is complete and the target has been reached.
End of enumeration elements list.
DE0A : Dimming Engine 0 Dimming Abort
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort dimming; DEzS is cleared, BCCU_DLz.DLEV stops changing
End of enumeration elements list.
DE1A : Dimming Engine 1 Dimming Abort
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort dimming; DEzS is cleared, BCCU_DLz.DLEV stops changing
End of enumeration elements list.
DE2A : Dimming Engine 2 Dimming Abort
bits : 18 - 17 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Abort dimming; DEzS is cleared, BCCU_DLz.DLEV stops changing
End of enumeration elements list.
Global Dimming Level
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GLOBDIM : Global Dimming Level
bits : 0 - 10 (11 bit)
access : read-write
Event Interrupt Enable
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T0IEN : Trigger 0 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trigger 0 interrupt generation is disabled
#1 : value2
BCCU trigger 0 (BCCU_TRIGOUT0) generates an interrupt on SR0
End of enumeration elements list.
T1IEN : Trigger 1 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trigger 1 interrupt generation is disabled
#1 : value2
BCCU trigger 1 (BCCU_TRIGOUT1) generates an interrupt on SR0
End of enumeration elements list.
FIEN : FIFO Full Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
FIFO-full interrupt generation is disabled
#1 : value2
An interrupt is generated on SR0 if any of the packer FIFOs is full when there is a write attempt by the on-time or off-time counter
End of enumeration elements list.
EIEN : FIFO Empty Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
FIFO-full interrupt generation is disabled
#1 : value2
An interrupt is generated on SR0 if any of the packer FIFOs is empty when there is a read attempt by the output generator
End of enumeration elements list.
TPIEN : Trap Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap interrupt generation is disabled
#1 : value2
An interrupt is generated on SR0 if a trap occurs
End of enumeration elements list.
Event Flag
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T0F : Trigger 0 Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
No trigger event has been detected on BCCU trigger line 0 (BCCU_TRIGOUT0)
#1 : value2
A trigger event has been detected on BCCU trigger line 0 (BCCU_TRIGOUT0)
End of enumeration elements list.
T1F : Trigger 1 Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
No trigger event has been detected on BCCU trigger line 1 (BCCU_TRIGOUT1)
#1 : value2
A trigger event has been detected on BCCU trigger line 1 (BCCU_TRIGOUT1)
End of enumeration elements list.
FF : FIFO Full Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
No FIFO full event has been detected
#1 : value2
A FIFO full event has been detected because one of the packer FIFOs is full and there has been a write attempt by the on-time or off-time counter
End of enumeration elements list.
EF : FIFO Empty Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
No FIFO full event has been detected
#1 : value2
A FIFO full event has been detected because one of the packer FIFOs is empty and there has been a read attempt by the output generator
End of enumeration elements list.
TPF : Trap Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
No trap event has been detected
#1 : value2
A trap event has been detected
End of enumeration elements list.
TPSF : Trap State Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
BCCU is not in a trap state
#1 : value2
BCCU is in a trap state, the affected channel outputs are at their passive levels
End of enumeration elements list.
TPINL : Trap Input Level
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current level of BCCU.TRAPL is low
#1 : value2
The current level of BCCU.TRAPL is high
End of enumeration elements list.
Event Flag Set
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T0FS : Trigger 0 Flag Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Sets the Trigger 0 Flag in EVFR and an interrupt will be generated if enabled in EVIER
End of enumeration elements list.
T1FS : Trigger 1 Flag Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Sets the Trigger 1 Flag in EVFR and an interrupt will be generated if enabled in EVIER
End of enumeration elements list.
FFS : FIFO Full Flag Set
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Sets the FIFO Full Flag in EVFR and an interrupt will be generated if enabled in EVIER
End of enumeration elements list.
EFS : FIFO Empty Flag Set
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Sets the FIFO Empty Flag in EVFR and an interrupt will be generated if enabled in EVIER
End of enumeration elements list.
TPFS : Trap Flag Set
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Sets the Trap Flag in EVFR and an interrupt will be generated if enabled in EVIER, no trap will occur
End of enumeration elements list.
TPS : Trap Set
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Sets the Trap State Flag and Trap Flag in EVFR, a trap will be generated and an interrupt will be generated if enabled in EVIER
End of enumeration elements list.
Event Flag Clear
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T0FC : Trigger 0 Flag Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clears the Trigger 0 Flag in EVFR
End of enumeration elements list.
T1FC : Trigger 1 Flag Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clears the Trigger 1 Flag in EVFR
End of enumeration elements list.
FFC : FIFO Full Flag Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clears the FIFO Full Flag in EVFR
End of enumeration elements list.
EFC : FIFO Empty Flag Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clears the FIFO Empty Flag in EVFR
End of enumeration elements list.
TPFC : Trap Flag Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clears the Trap Flag in EVFR
End of enumeration elements list.
TPC : Trap Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clears the Trap State Flag in EVFR; trap state is exited, the affected channels will return to their normal output levels
End of enumeration elements list.
Global Clock
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCLK_PS : Fast Clock Prescaler Factor
bits : 0 - 10 (11 bit)
access : read-write
Enumeration:
0 : value1
No clock
1 : value2
Divide by 1
4095 : value3
Divide by 4095
End of enumeration elements list.
BCS : Bit-Clock Selector
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Normal Mode: BCCU_bclk is generated from BCCU_fclk by a division of 4
#1 : value2
Fast Mode: BCCU_bclk is the same as BCCU_fclk
End of enumeration elements list.
DCLK_PS : Dimmer Clock Prescaler Factor
bits : 16 - 26 (11 bit)
access : read-write
Enumeration:
0 : value1
No clock
1 : value2
Divide by 1
4095 : value3
Divide by 4095
End of enumeration elements list.
Module Identification
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE0 : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number Value
bits : 16 - 30 (15 bit)
access : read-only
Channel Enable
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECH0 : Channel 0 Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH1 : Channel 1 Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH2 : Channel 2 Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH3 : Channel 3 Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH4 : Channel 4 Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH5 : Channel 5 Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH6 : Channel 6 Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH7 : Channel 7 Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
ECH8 : Channel 8 Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
Channel is disabled, the output level is passive; the Linear Walker and the Sigma-Delta Modulator are reset, the Packer FIFO is flushed; all internal logic and INTy are reset when the channel gets disabled
#1 : value2
Channel is enabled
End of enumeration elements list.
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