\n

BCCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

DLS

DL

DTT


DLS

Dimming Level Shadow
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLS DLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDLEV

TDLEV : Target Dimming Level
bits : 0 - 10 (11 bit)
access : read-write


DL

Dimming Level
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DL DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLEV

DLEV : Dimming Level
bits : 0 - 10 (11 bit)
access : read-only


DTT

Dimming Transition Time
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTT DTT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIMDIV DTEN CSEL

DIMDIV : Dimming Clock Divider
bits : 0 - 8 (9 bit)
access : read-write

DTEN : Dither Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

No dithering

#1 : value2

Dithering is added to every dimming step if the dimming level is below 128; the coarse curve is used for the entire dimming range

End of enumeration elements list.

CSEL : Curve Select
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

Coarse curve

#1 : value2

Fine curve

End of enumeration elements list.



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