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HRPWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DCI

DSV1

DSV2

SDSV1

SPC

CC

PLC

BLV

SRE

SRS

SWS

SWC

ISTAT

IES

SC

PC


DCI

External input selection
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCI DCI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SVIS STRIS STPIS TRGIS STIS SCS

SVIS : Value Selector input selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

HRPWMx.SyIA

#0001 : value2

HRPWMx.SyIB

#0010 : value3

HRPWMx.SyIC

#0011 : value4

HRPWMx.SyID

#0100 : value5

HRPWMx.SyIE

#0101 : value6

HRPWMx.SyIF

#0110 : value7

HRPWMx.SyIG

#0111 : value8

HRPWMx.SyIH

#1000 : value9

HRPWMx.SyII

#1001 : value10

HRPWMx.SyIJ

#1010 : value11

HRPWMx.SyIK

#1011 : value12

HRPWMx.SyIL

#1100 : value13

HRPWMx.SyIM

#1101 : value14

HRPWMx.SyIN

#1110 : value15

HRPWMx.SyIO

#1111 : value16

HRPWMx.SyIP

End of enumeration elements list.

STRIS : Slope generation start control input selection
bits : 4 - 6 (3 bit)
access : read-write

STPIS : Slope generation stop control input selection
bits : 8 - 10 (3 bit)
access : read-write

TRGIS : External conversion trigger input selection
bits : 12 - 14 (3 bit)
access : read-write

STIS : External shadow request enable input selection
bits : 16 - 18 (3 bit)
access : read-write

SCS : Slope generation clock selection
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

HRPWMx.MCLK (Module clock is used)

#01 : value2

HRPWMx.ECLKA (External clock is used)

#10 : value3

HRPWMx.ECLKB (External clock is used)

#11 : value4

HRPWMx.ECLKC (External clock is used)

End of enumeration elements list.


DSV1

DAC reference value 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSV1 DSV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSV1

DSV1 : DAC reference value 1
bits : 0 - 8 (9 bit)
access : read-only


DSV2

DAC reference value 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSV2 DSV2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSV2

DSV2 : DAC reference value 2
bits : 0 - 8 (9 bit)
access : read-write


SDSV1

Shadow reference value 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDSV1 SDSV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDSV1

SDSV1 : Shadow DAC reference value 1
bits : 0 - 8 (9 bit)
access : read-write


SPC

Shadow Pulse swallow value
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPC SPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPSWV

SPSWV : Shadow pulse swallow value
bits : 0 - 4 (5 bit)
access : read-write


CC

Comparator configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IBS IMCS IMCC ESE OIE OSE BLMC EBE COFE COFM COFC

IBS : External blanking trigger selector
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

HRPWMx.BLyA

#0001 : value2

HRPWMx.BLyB

#0010 : value3

HRPWMx.BLyC

#0011 : value4

HRPWMx.BLyD

#0100 : value5

HRPWMx.BLyE

#0101 : value6

HRPWMx.BLyF

#0110 : value7

HRPWMx.BLyG

#0111 : value8

HRPWMx.BLyH

#1000 : value9

HRPWMx.BLyI

#1001 : value10

HRPWMx.BLyJ

#1010 : value11

HRPWMx.BLyK

#1011 : value12

HRPWMx.BLyL

#1100 : value13

HRPWMx.BLyM

#1101 : value14

HRPWMx.BLyN

#1110 : value15

HRPWMx.BLyO

#1111 : value16

HRPWMx.BLyP

End of enumeration elements list.

IMCS : Inverting comparator input selector
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

HRPWMx.CyINA

#1 : value2

HRPWMx.CyINB

End of enumeration elements list.

IMCC : Comparator input switching configuration
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#00 : value1

Dynamic switch disabled

#01 : value2

Comparator input is connected to HRPWMx.CyINB when the control signal is HIGH

#10 : value3

Comparator input is connected to HRPWMx.CyINA when the control signal is HIGH

End of enumeration elements list.

ESE : External triggered switch enable
bits : 11 - 10 (0 bit)
access : read-write

OIE : Comparator output inversion enable
bits : 12 - 11 (0 bit)
access : read-write

OSE : Comparator output synchronization enable
bits : 13 - 12 (0 bit)
access : read-write

BLMC : Blanking mode
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

Blanking disabled

#01 : value2

Blanking on a LOW to HIGH transition

#10 : value3

Blanking on a HIGH to LOW transition

#11 : value4

Blanking on both transitions

End of enumeration elements list.

EBE : External blanking trigger enabled
bits : 16 - 15 (0 bit)
access : read-write

COFE : Comparator output filter enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

Filtering stage disabled

#1 : value2

Filtering stage enabled

End of enumeration elements list.

COFM : Comparator output filter window
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Comparator Output needs to be stable for 2 clock cycles

#0001 : value2

Comparator Output needs to be stable for 3 clock cycles

#0010 : value3

Comparator Output needs to be stable for 4 clock cycles

#0011 : value4

Comparator Output needs to be stable for 5 clock cycles

#1100 : value5

Comparator Output needs to be stable for 14 clock cycles

#1101 : value6

Comparator Output needs to be stable for 15 clock cycles

#1110 : value7

Comparator Output needs to be stable for 16 clock cycles

#1111 : value8

Comparator Output needs to be stable for 32 clock cycles

End of enumeration elements list.

COFC : Comparator output filter control
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#00 : value1

Filtering is always done if enabled

#01 : value2

Filtering is only done when CSGyDSV1 value is currently fed to the DAC

#10 : value3

Filtering is only done when the CSGyDSV2 value is currently fed to the DAC

End of enumeration elements list.


PLC

Passive level configuration
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLC PLC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPLS PLCL PSL PLSW PLEC PLXC

IPLS : Clamping control signal selector
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

HRPWMx.BLyA

#0001 : value2

HRPWMx.BLyB

#0010 : value3

HRPWMx.BLyC

#0011 : value4

HRPWMx.BLyD

#0100 : value5

HRPWMx.BLyE

#0101 : value6

HRPWMx.BLyF

#0110 : value7

HRPWMx.BLyG

#0111 : value8

HRPWMx.BLyH

#1000 : value9

HRPWMx.BLyI

#1001 : value10

HRPWMx.BLyJ

#1010 : value11

HRPWMx.BLyK

#1011 : value12

HRPWMx.BLyL

#1100 : value13

HRPWMx.BLyM

#1101 : value14

HRPWMx.BLyN

#1110 : value15

HRPWMx.BLyO

#1111 : value16

HRPWMx.BLyP

End of enumeration elements list.

PLCL : Clamping control signal level selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Clamping control disabled

#01 : value2

Output is set to clamped level when the control signal is HIGH

#10 : value3

Output is set to clamped level when the control signal is LOW

End of enumeration elements list.

PSL : Output passive level value
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Output clamped level is LOW

#1 : value2

Output clamped level is HIGH

End of enumeration elements list.

PLSW : Clamped state exit SW configuration
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

External signal and SW can remove the output from the clamped state

#1 : value2

Only SW can remove the output from the clamped state

End of enumeration elements list.

PLEC : Passive level enter configuration
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : value1

Passive level is entered immediately

#01 : value2

Passive level is entered only after the comparator output passes to LOW (output from the blanking stage)

#10 : value3

Passive level is entered only after the comparator output passes to HIGH (output from the blanking stage)

End of enumeration elements list.

PLXC : Passive level exit configuration
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

Passive level is exit immediately

#01 : value2

Passive level is exit only after the comparator output passes to LOW (output from the blanking stage)

#10 : value3

Passive level is exit only after the comparator output passes to HIGH (output from the blanking stage)

End of enumeration elements list.


BLV

Comparator blanking value
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLV BLV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLV

BLV : Blanking value
bits : 0 - 6 (7 bit)
access : read-write


SRE

Service request enable
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRE SRE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLS1E VLS2E TRGSE STRSE STPSE STDE CRSE CFSE CSEE

VLS1E : Value switch from CSGyDSV1 to CSGyDSV2 interrupt enable
bits : 0 - -1 (0 bit)
access : read-write

VLS2E : Value switch from CSGyDSV2 to CSGyDSV1 interrupt enable
bits : 1 - 0 (0 bit)
access : read-write

TRGSE : Conversion trigger interrupt enable
bits : 2 - 1 (0 bit)
access : read-write

STRSE : Start trigger interrupt enable
bits : 3 - 2 (0 bit)
access : read-write

STPSE : Stop trigger interrupt enable
bits : 4 - 3 (0 bit)
access : read-write

STDE : Shadow transfer done interrupt enable
bits : 5 - 4 (0 bit)
access : read-write

CRSE : Comparator rise interrupt enable
bits : 6 - 5 (0 bit)
access : read-write

CFSE : Comparator fall interrupt enable
bits : 7 - 6 (0 bit)
access : read-write

CSEE : Clamped state interrupt enable
bits : 8 - 7 (0 bit)
access : read-write


SRS

Service request line selector
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRS SRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLS1S VLS2S TRLS SSLS STLS CRFLS CSLS

VLS1S : Value switch from CSGyDSV1 to CSGyDSV2 interrupt line selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.

VLS2S : Value switch from CSGyDSV2 to CSGyDSV1 interrupt line selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.

TRLS : Conversion trigger interrupt line selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.

SSLS : Start/Stop trigger interrupt line selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.

STLS : Shadow transfer done interrupt line selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.

CRFLS : Comparator rise/fall interrupt line selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.

CSLS : Comparator clamped state interrupt line selection
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGySR0

#01 : value2

CSGySR1

#10 : value3

CSGySR2

#11 : value4

CSGySR3

End of enumeration elements list.


SWS

Service request SW set
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWS SWS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SVLS1 SVLS2 STRGS SSTRS SSTPS SSTD SCRS SCFS SCSS

SVLS1 : Value switch from CSGyDSV1 to CSGyDSV2 status set
bits : 0 - -1 (0 bit)
access : write-only

SVLS2 : Value switch from CSGyDSV2 to CSGyDSV1 status set
bits : 1 - 0 (0 bit)
access : write-only

STRGS : Conversion trigger status set
bits : 2 - 1 (0 bit)
access : write-only

SSTRS : Start trigger status set
bits : 3 - 2 (0 bit)
access : write-only

SSTPS : Stop trigger status set
bits : 4 - 3 (0 bit)
access : write-only

SSTD : Shadow transfer status set
bits : 5 - 4 (0 bit)
access : write-only

SCRS : Comparator rise status set
bits : 6 - 5 (0 bit)
access : write-only

SCFS : Comparator fall status set
bits : 7 - 6 (0 bit)
access : write-only

SCSS : Comparator clamped state status set
bits : 8 - 7 (0 bit)
access : write-only


SWC

Service request SW clear
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWC SWC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CVLS1 CVLS2 CTRGS CSTRS CSTPS CSTD CCRS CCFS CCSS

CVLS1 : Value switch from CSGyDSV1 to CSGyDSV2 status clear
bits : 0 - -1 (0 bit)
access : write-only

CVLS2 : Value switch from CSGyDSV2 to CSGyDSV1 status clear
bits : 1 - 0 (0 bit)
access : write-only

CTRGS : Conversion trigger status clear
bits : 2 - 1 (0 bit)
access : write-only

CSTRS : Start trigger status clear
bits : 3 - 2 (0 bit)
access : write-only

CSTPS : Stop trigger status clear
bits : 4 - 3 (0 bit)
access : write-only

CSTD : Shadow transfer status clear
bits : 5 - 4 (0 bit)
access : write-only

CCRS : Comparator rise status clear
bits : 6 - 5 (0 bit)
access : write-only

CCFS : Comparator fall status clear
bits : 7 - 6 (0 bit)
access : write-only

CCSS : Comparator clamped status clear
bits : 8 - 7 (0 bit)
access : write-only


ISTAT

Service request status
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISTAT ISTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VLS1S VLS2S TRGSS STRSS STPSS STDS CRSS CFSS CSES

VLS1S : Value switch from CSGyDSV1 to CSGyDSV2 interrupt status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Value switch not detected

#1 : value2

Value switch detected

End of enumeration elements list.

VLS2S : Value switch from CSGyDSV2 to CSGyDSV1 interrupt status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Value switch not detected

#1 : value2

Value switch detected

End of enumeration elements list.

TRGSS : Conversion trigger status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Conversion trigger was not generated

#1 : value2

Conversion trigger was generated

End of enumeration elements list.

STRSS : Start trigger interrupt status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Start trigger not detected

#1 : value2

Start trigger detected

End of enumeration elements list.

STPSS : Stop trigger interrupt status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Stop trigger not detected

#1 : value2

Stop trigger detected

End of enumeration elements list.

STDS : Shadow transfer interrupt status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Shadow transfer was not performed

#1 : value2

Shadow transfer was performed

End of enumeration elements list.

CRSS : Comparator rise interrupt status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

Comparator output LOW to HIGH transition not detected

#1 : value2

Comparator output LOW to HIGH transition detected

End of enumeration elements list.

CFSS : Comparator fall interrupt status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

Comparator output HIGH to LOW transition not detected

#1 : value2

Comparator output HIGH to LOW transition detected

End of enumeration elements list.

CSES : Comparator clamped interrupt status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Comparator output has been set to the clamped state

#1 : value2

Comparator output has not been set to the clamped state

End of enumeration elements list.


IES

External input selection
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IES IES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SVLS STRES STPES TRGES STES

SVLS : External value switch function level selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Function disabled

#01 : value2

Active when input is HIGH

#10 : value3

Active when input is LOW

End of enumeration elements list.

STRES : External start function edge selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

Function disabled

#01 : value2

Active on rising edge

#10 : value3

Active on falling edge

#11 : value4

Active on both edges

End of enumeration elements list.

STPES : External stop function edge selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Function disabled

#01 : value2

Active on rising edge

#10 : value3

Active on falling edge

#11 : value4

Active on both edges

End of enumeration elements list.

TRGES : External trigger function edge selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Function disabled

#01 : value2

Active on rising edge

#10 : value3

Active on falling edge

#11 : value4

Active on both edges

End of enumeration elements list.

STES : External shadow transfer enable edge selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Function disabled

#01 : value2

Active on rising edge

#10 : value3

Active on falling edge

#11 : value4

Active on both edges

End of enumeration elements list.


SC

Slope generation control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC SC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSRM PSTM FPD PSV SCM SSRM SSTM SVSC SWSM GCFG IST PSE PSWM

PSRM : Prescaler external start configuration
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

External start trigger is ignored

#01 : value2

Start prescaler

#10 : value3

Clear prescaler

#11 : value4

Clear & Start prescaler

End of enumeration elements list.

PSTM : Prescaler external stop configuration
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

External stop trigger is ignored

#01 : value2

Stop prescaler

#10 : value3

Clear prescaler

#11 : value4

Clear & Stop prescaler

End of enumeration elements list.

FPD : Fixed division disable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Division by 4 enabled

#1 : value2

Division by 4 disabled

End of enumeration elements list.

PSV : Prescaler division factor
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#00 : value1

division by 1

#01 : value2

division by 2

#10 : value3

division by 4

#11 : value4

division by 8

End of enumeration elements list.

SCM : Slope control mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Slope generation disabled. Used when the switch between the two reference values, CSGyDSV1This register contains the actual value used for the DSV1 reference. and CSGyDSV2This register contains the actual value used for the DSV2 reference. is done via external signal.

#01 : value2

Decrementing slope generation.

#10 : value3

Incrementing slope generation.

#11 : value4

Triangular slope generation.

End of enumeration elements list.

SSRM : Slope external start configuration
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : value1

External start trigger is ignored

#01 : value2

Start/restart slope generation

#10 : value3

Resumes slope

End of enumeration elements list.

SSTM : Slope external stop configuration
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : value1

External stop trigger is ignored

#01 : value2

Stops/Halts the slope generation

#10 : value3

Used in hybrid mode. It freezes the slope generation and feeds constantly the value programmed in CSGyDSV2This register contains the actual value used for the DSV2 reference. to the DAC.

End of enumeration elements list.

SVSC : Slope reference value mode
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

Only CSGyDSV1This register contains the actual value used for the DSV1 reference. value is used for the slope generation: if slope is incrementing, CSGyDSV1This register contains the actual value used for the DSV1 reference. is the bottom reference value from where the ramp starts; if decrementing, then CSGyDSV1This register contains the actual value used for the DSV1 reference. is the upper reference value from where the ramp starts.

#01 : value2

The two reference values are being used: CSGyDSV1This register contains the actual value used for the DSV1 reference. is the low or high reference value from where the ramp starts (incrementing or decrementing respectively); CSGyDSV2This register contains the actual value used for the DSV2 reference. is used as a static value (this value is constantly fed to the DAC after a stop trigger as been detected).

#10 : value3

The two reference values are used: CSGyDSV1This register contains the actual value used for the DSV1 reference. is the low or high reference value from where the slope starts (incrementing or decrementing respectively); CSGyDSV2This register contains the actual value used for the DSV2 reference. is used as an internal re start condition for the slope.

End of enumeration elements list.

SWSM : Initial DAC start mode
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#00 : value1

CSGyDSV2This register contains the actual value used for the DSV2 reference. is fed to the DAC and initial conversion trigger is generated.

#01 : value2

CSGyDSV1This register contains the actual value used for the DSV1 reference. is fed to the DAC and initial conversion trigger is generated.

#10 : value3

CSGyDSV2This register contains the actual value used for the DSV2 reference. is fed to the DAC but initial conversion trigger is not generated.

#11 : value4

CSGyDSV1This register contains the actual value used for the DSV1 reference. is fed to the DAC but initial conversion trigger is not generated.

End of enumeration elements list.

GCFG : Slope step gain configuration
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#00 : value1

Each slope step has an increment/decrement of 1

#01 : value2

Each slope step has an increment/decrement of 2

#10 : value3

Each slope step has an increment/decrement of 4

#11 : value4

Each slope step has an increment/decrement of 8

End of enumeration elements list.

IST : Immediate shadow transfer
bits : 20 - 19 (0 bit)
access : read-write

PSE : Pulse swallow enable
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Pulse swallow disabled

#1 : value2

Pulse swallow enabled

End of enumeration elements list.

PSWM : Pulse swallow window mode
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#00 : value1

16 clock cycle window

#01 : value2

32 clock cycle window

#10 : value3

64 clock cycle window

End of enumeration elements list.


PC

Pulse swallow configuration
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSWV

PSWV : Pulse swallow configuration
bits : 0 - 4 (5 bit)
access : read-only



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