\n

SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLKSTAT

CPUCLKCR

PBCLKCR

USBCLKCR

CCUCLKCR

WDTCLKCR

EXTCLKCR

MLINKCLKCR

SLEEPCR

DSLEEPCR

ECATCLKCR

CLKSET

CGATSTAT0

CGATSET0

CGATCLR0

CGATSTAT1

CGATSET1

CGATCLR1

CGATSTAT2

CGATSET2

CGATCLR2

CLKCLR

SYSCLKCR


CLKSTAT

Clock Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSTAT CLKSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCST MMCCST ETH0CST CCUCST WDTCST

USBCST : USB Clock Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Clock disabled

#1 : Const_1

Clock enabled

End of enumeration elements list.

MMCCST : MMC Clock Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Clock disabled

#1 : Const_1

Clock enabled

End of enumeration elements list.

ETH0CST : Ethernet Clock Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Clock disabled

#1 : Const_1

Clock enabled

End of enumeration elements list.

CCUCST : CCU Clock Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Clock disabled

#1 : Const_1

Clock enabled

End of enumeration elements list.

WDTCST : WDT Clock Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Clock disabled

#1 : Const_1

Clock enabled

End of enumeration elements list.


CPUCLKCR

CPU Clock Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUCLKCR CPUCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPUDIV

CPUDIV : CPU Clock Divider Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fCPU = fSYS

#1 : Const_1

fCPU = fSYS / 2

End of enumeration elements list.


PBCLKCR

Peripheral Bus Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PBCLKCR PBCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PBDIV

PBDIV : PB Clock Divider Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fPERIPH = fCPU

#1 : Const_1

fPERIPH = fCPU / 2

End of enumeration elements list.


USBCLKCR

USB Clock Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCLKCR USBCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBDIV USBSEL

USBDIV : USB Clock Divider Value
bits : 0 - 1 (2 bit)
access : read-write

USBSEL : USB Clock Selection Value
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

USB PLL Clock

#1 : Const_1

PLL Clock

End of enumeration elements list.


CCUCLKCR

CCU Clock Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCUCLKCR CCUCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCUDIV

CCUDIV : CCU Clock Divider Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fCCU = fSYS

#1 : Const_1

fCCU = fSYS / 2

End of enumeration elements list.


WDTCLKCR

WDT Clock Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDTCLKCR WDTCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTDIV WDTSEL

WDTDIV : WDT Clock Divider Value
bits : 0 - 6 (7 bit)
access : read-write

WDTSEL : WDT Clock Selection Value
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#00 : Const_00

fOFI clock

#01 : Const_01

fSTDBY clock

#10 : Const_10

fPLL clock

End of enumeration elements list.


EXTCLKCR

External Clock Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTCLKCR EXTCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECKSEL ECKDIV

ECKSEL : External Clock Selection Value
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : Const_00

fSYS clock

#10 : Const_10

fUSB clock divided according to ECKDIV bit field configuration

#11 : Const_11

fPLL clock divided according to ECKDIV bit field configuration

End of enumeration elements list.

ECKDIV : External Clock Divider Value
bits : 16 - 23 (8 bit)
access : read-write


MLINKCLKCR

Multi-Link Clock Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MLINKCLKCR MLINKCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSDIV SYSSEL CPUDIV PBDIV CCUDIV WDTDIV WDTSEL

SYSDIV : System Clock Division Value
bits : 0 - 6 (7 bit)
access : read-write

SYSSEL : System Clock Selection Value
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fOFI clock

#1 : Const_1

fPLL clock

End of enumeration elements list.

CPUDIV : CPU Clock Divider Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fCPU = fSYS

#1 : Const_1

fCPU = fSYS / 2

End of enumeration elements list.

PBDIV : PB Clock Divider Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fPERIPH = fCPU

#1 : Const_1

fPERIPH = fCPU / 2

End of enumeration elements list.

CCUDIV : CCU Clock Divider Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fCCU = fSYS

#1 : Const_1

fCCU = fSYS / 2

End of enumeration elements list.

WDTDIV : WDT Clock Divider Value
bits : 16 - 22 (7 bit)
access : read-write

WDTSEL : WDT Clock Selection Value
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#00 : Const_00

fOFI clock

#01 : Const_01

fSTDBY clock

#10 : Const_10

fPLL clock

End of enumeration elements list.


SLEEPCR

Sleep Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEPCR SLEEPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSSEL USBCR MMCCR ETH0CR CCUCR WDTCR

SYSSEL : System Clock Selection Value
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fOFI clock

#1 : Const_1

fPLL clock

End of enumeration elements list.

USBCR : USB Clock Control in Sleep Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

MMCCR : MMC Clock Control in Sleep Mode
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

ETH0CR : Ethernet Clock Control in Sleep Mode
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

CCUCR : CCU Clock Control in Sleep Mode
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

WDTCR : WDT Clock Control in Sleep Mode
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.


DSLEEPCR

Deep Sleep Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSLEEPCR DSLEEPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSSEL FPDN PLLPDN VCOPDN USBCR MMCCR ETH0CR CCUCR WDTCR

SYSSEL : System Clock Selection Value
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fOFI clock

#1 : Const_1

fPLL clock

End of enumeration elements list.

FPDN : Flash Power Down
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#1 : Const_1

Flash power down module

#0 : Const_0

No effect

End of enumeration elements list.

PLLPDN : PLL Power Down
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#1 : Const_1

Switch off main PLL

#0 : Const_0

No effect

End of enumeration elements list.

VCOPDN : VCO Power Down
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#1 : Const_1

Switch off VCO of main PLL

#0 : Const_0

No effect

End of enumeration elements list.

USBCR : USB Clock Control in Deep Sleep Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

MMCCR : MMC Clock Control in Deep Sleep Mode
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

ETH0CR : Ethernet Clock Control in Deep Sleep Mode
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

CCUCR : CCU Clock Control in Deep Sleep Mode
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

WDTCR : WDT Clock Control in Deep Sleep Mode
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.


ECATCLKCR

EtherCAT Clock Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECATCLKCR ECATCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECADIV ECATSEL

ECADIV : EtherCAT Clock Divider Value
bits : 0 - 0 (1 bit)
access : read-write

ECATSEL : EtherCAT Clock Selection Value
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fPLLUSB clock

#1 : Const_1

fPLL clock

End of enumeration elements list.


CLKSET

CLK Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSET CLKSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCEN MMCCEN ETH0CEN CCUCEN WDTCEN

USBCEN : USB Clock Enable
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable

End of enumeration elements list.

MMCCEN : MMC Clock Enable
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable

End of enumeration elements list.

ETH0CEN : Ethernet Clock Enable
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable

End of enumeration elements list.

CCUCEN : CCU Clock Enable
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable

End of enumeration elements list.

WDTCEN : WDT Clock Enable
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable

End of enumeration elements list.


CGATSTAT0

Peripheral 0 Clock Gating Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATSTAT0 CGATSTAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADC CCU40 CCU41 CCU80 POSIF0 USIC0 ERU1

VADC : VADC Gating Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

CCU40 : CCU40 Gating Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

CCU41 : CCU41 Gating Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

CCU80 : CCU80 Gating Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

POSIF0 : POSIF0 Gating Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

USIC0 : USIC0 Gating Status
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

ERU1 : ERU1 Gating Status
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.


CGATSET0

Peripheral 0 Clock Gating Set
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATSET0 CGATSET0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADC CCU40 CCU41 CCU80 POSIF0 USIC0 ERU1

VADC : VADC Gating Set
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

CCU40 : CCU40 Gating Set
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

CCU41 : CCU41 Gating Set
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

CCU80 : CCU80 Gating Set
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

POSIF0 : POSIF0 Gating Set
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

USIC0 : USIC0 Gating Set
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

ERU1 : ERU1 Gating Set
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.


CGATCLR0

Peripheral 0 Clock Gating Clear
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATCLR0 CGATCLR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADC CCU40 CCU41 CCU80 POSIF0 USIC0 ERU1

VADC : VADC Gating Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

CCU40 : CCU40 Gating Clear
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

CCU41 : CCU41 Gating Clear
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

CCU80 : CCU80 Gating Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

POSIF0 : POSIF0 Gating Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

USIC0 : USIC0 Gating Clear
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

ERU1 : ERU1 Gating Clear
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.


CGATSTAT1

Peripheral 1 Clock Gating Status
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATSTAT1 CGATSTAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEDTSCU0 MCAN0 DAC MMCI USIC1 PPORTS

LEDTSCU0 : LEDTS Gating Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Gating de-asserted

#1 : value2

Gating asserted

End of enumeration elements list.

MCAN0 : MultiCAN Gating Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Gating de-asserted

#1 : value2

Gating asserted

End of enumeration elements list.

DAC : DAC Gating Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Gating de-asserted

#1 : value2

Gating asserted

End of enumeration elements list.

MMCI : MMC Interface Gating Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

Gating de-asserted

#1 : value2

Gating asserted

End of enumeration elements list.

USIC1 : USIC1 Gating Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

Gating de-asserted

#1 : value2

Gating asserted

End of enumeration elements list.

PPORTS : PORTS Gating Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

Gating de-asserted

#1 : value2

Gating asserted

End of enumeration elements list.


CGATSET1

Peripheral 1 Clock Gating Set
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATSET1 CGATSET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEDTSCU0 MCAN0 DAC MMCI USIC1 PPORTS

LEDTSCU0 : LEDTS Gating Set
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

MCAN0 : MultiCAN Gating Set
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

DAC : DAC Gating Set
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

MMCI : MMC Interface Gating Set
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

USIC1 : USIC1 Gating Set
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

PPORTS : PORTS Gating Set
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.


CGATCLR1

Peripheral 1 Clock Gating Clear
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATCLR1 CGATCLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEDTSCU0 MCAN0 DAC MMCI USIC1 PPORTS

LEDTSCU0 : LEDTS Gating Clear
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

MCAN0 : MultiCAN Gating Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

DAC : DAC Gating Clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

MMCI : MMC Interface Gating Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

USIC1 : USIC1 Gating Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

PPORTS : PORTS Gating Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.


CGATSTAT2

Peripheral 2 Clock Gating Status
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATSTAT2 CGATSTAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT ETH0 DMA0 FCE USB ECAT0

WDT : WDT Gating Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

ETH0 : ETH0 Gating Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

DMA0 : DMA0 Gating Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

FCE : FCE Gating Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

USB : USB Gating Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.

ECAT0 : ECAT0 Gating Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Gating de-asserted

#1 : Const_1

Gating asserted

End of enumeration elements list.


CGATSET2

Peripheral 2 Clock Gating Set
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATSET2 CGATSET2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT ETH0 DMA0 FCE USB ECAT0

WDT : WDT Gating Set
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

ETH0 : ETH0 Gating Set
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

DMA0 : DMA0 Gating Set
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

FCE : FCE Gating Set
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

USB : USB Gating Set
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.

ECAT0 : ECAT0 Gating Set
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Enable gating

End of enumeration elements list.


CGATCLR2

Peripheral 2 Clock Gating Clear
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGATCLR2 CGATCLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT ETH0 DMA0 FCE USB ECAT0

WDT : WDT Gating Clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

ETH0 : ETH0 Gating Clear
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

DMA0 : DMA0 Gating Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

FCE : FCE Gating Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

USB : USB Gating Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.

ECAT0 : ECAT0 Gating Clear
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable gating

End of enumeration elements list.


CLKCLR

CLK Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCLR CLKCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCDI MMCCDI ETH0CDI CCUCDI WDTCDI

USBCDI : USB Clock Disable
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable clock

End of enumeration elements list.

MMCCDI : MMC Clock Disable
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable clock

End of enumeration elements list.

ETH0CDI : Ethernet Clock Disable
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable clock

End of enumeration elements list.

CCUCDI : CCU Clock Disable
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable clock

End of enumeration elements list.

WDTCDI : WDT Clock Disable
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No effect

#1 : Const_1

Disable clock

End of enumeration elements list.


SYSCLKCR

System Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSCLKCR SYSCLKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSDIV SYSSEL

SYSDIV : System Clock Division Value
bits : 0 - 6 (7 bit)
access : read-write

SYSSEL : System Clock Selection Value
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

fOFI clock

#1 : Const_1

fPLL clock

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.