Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Parity Error Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEENPS : Parity Error Enable for PSRAM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENDS1 : Parity Error Enable for DSRAM1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENU0 : Parity Error Enable for USIC0 Memory
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENU1 : Parity Error Enable for USIC1 Memory
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENMC : Parity Error Enable for MultiCAN Memory
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENPPRF : Parity Error Enable for PMU Prefetch Memory
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENUSB : Parity Error Enable for USB Memory
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENETH0TX : Parity Error Enable for ETH TX Memory
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENETH0RX : Parity Error Enable for ETH RX Memory
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENSD0 : Parity Error Enable for SDMMC Memory 0
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENSD1 : Parity Error Enable for SDMMC Memory 1
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PEENECAT0 : Parity Error Enable for ECAT0 Memory
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
Parity Error Flag Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEFPS : Parity Error Flag for PSRAM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEFDS1 : Parity Error Flag for DSRAM1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEFU0 : Parity Error Flag for USIC0 Memory
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEFU1 : Parity Error Flag for USIC1 Memory
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEFMC : Parity Error Flag for MultiCAN Memory
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEFPPRF : Parity Error Flag for PMU Prefetch Memory
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEUSB : Parity Error Flag for USB Memory
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEETH0TX : Parity Error Flag for ETH TX Memory
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEETH0RX : Parity Error Flag for ETH RX Memory
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PESD0 : Parity Error Flag for SDMMC Memory 0
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PESD1 : Parity Error Flag for SDMMC Memory 1
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
PEECAT0 : Parity Error Flag for ECAT0 Memory
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
No parity error detected
#1 : Const_1
Parity error detected
End of enumeration elements list.
Parity Memory Test Pattern Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWR : Parity Write Values for Memory Test
bits : 0 - 6 (7 bit)
access : read-write
PRD : Parity Read Values for Memory Test
bits : 8 - 14 (7 bit)
access : read-only
Parity Memory Test Select Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTENPS : Test Enable Control for PSRAM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTENDS1 : Test Enable Control for DSRAM1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTEU0 : Test Enable Control for USIC0 Memory
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTEU1 : Test Enable Control for USIC1 Memory
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTEMC : Test Enable Control for MultiCAN Memory
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTEPPRF : Test Enable Control for PMU Prefetch Memory
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTUSB : Test Enable Control for USB Memory
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTETH0TX : Test Enable Control for ETH TX Memory
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTETH0RX : Test Enable Control for ETH RX Memory
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTSD0 : Test Enable Control for SDMMC Memory 0
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTSD1 : Test Enable Control for SDMMC Memory 1
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
MTECAT0 : Test Enable Control for ECAT0 Memory
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Standard operation
#1 : Const_1
Parity bits under test
End of enumeration elements list.
Memory Checking Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELPS : Select Memory Check for PSRAM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELDS1 : Select Memory Check for DSRAM1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
USIC0DRA : Select Memory Check for USIC0
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
USIC1DRA : Select Memory Check for USIC1
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
MCANDRA : Select Memory Check for MultiCAN
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
PPRFDRA : Select Memory Check for PMU
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELUSB : Select Memory Check for USB SRAM
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELETH0TX : Select Memory Check for ETH0 TX SRAM
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELETH0RX : Select Memory Check for ETH0 RX SRAM
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELSD0 : Select Memory Check for SDMMC SRAM 0
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELSD1 : Select Memory Check for SDMMC SRAM 1
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
SELECAT0 : Select Memory Check for ECAT0 SRAM 1
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Not selected
#1 : Const_1
Selected
End of enumeration elements list.
Parity Error Trap Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PETEPS : Parity Error Trap Enable for PSRAM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEDS1 : Parity Error Trap Enable for DSRAM1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEU0 : Parity Error Trap Enable for USIC0 Memory
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEU1 : Parity Error Trap Enable for USIC1 Memory
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEMC : Parity Error Trap Enable for MultiCAN Memory
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEPPRF : Parity Error Trap Enable for PMU Prefetch Memory
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEUSB : Parity Error Trap Enable for USB Memory
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEETH0TX : Parity Error Trap Enable for ETH 0TX Memory
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEETH0RX : Parity Error Trap Enable for ETH0 RX Memory
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETESD0 : Parity Error Trap Enable for SDMMC SRAM 0 Memory
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETESD1 : Parity Error Trap Enable for SDMMC SRAM 1 Memory
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
PETEECAT0 : Parity Error Trap Enable for ECAT0 SRAM Memory
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Disabled
#1 : Const_1
Enabled
End of enumeration elements list.
Parity Error Reset Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSEN : System Reset Enable upon Parity Error Trap
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Reset request disabled
#1 : Const_1
Reset request enabled
End of enumeration elements list.
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