\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Hibernate Domain Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEV : Wake-up Pin Event Positive Edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Wake-up on positive edge pin event inactive
#1 : Const_1
Wake-up on positive edge pin event active
End of enumeration elements list.
ENEV : Wake-up Pin Event Negative Edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Wake-up on negative edge pin event inactive
#1 : Const_1
Wake-up on negative edge pin event active
End of enumeration elements list.
RTCEV : RTC Event
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Wake-up on RTC event inactive
#1 : Const_1
Wake-up on RTC event active
End of enumeration elements list.
ULPWDG : ULP WDG Alarm Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Watchdog alarm did not occur
#1 : Const_1
Watchdog alarm occurred
End of enumeration elements list.
HIBNOUT : Hibernate Control Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Hibernate not driven active to pads
#1 : Const_1
Hibernate driven active to pads
End of enumeration elements list.
fOSI Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWD : Turn OFF the fOSI Clock Source
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Enabled
#1 : Const_1
Disabled
End of enumeration elements list.
OSC_ULP Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X1D : XTAL1 Data Value
bits : 0 - -1 (0 bit)
access : read-only
OSC_ULP Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X1DEN : XTAL1 Data General Purpose Input Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Data input inactivated, power down
#1 : Const_1
Data input active
End of enumeration elements list.
MODE : Oscillator Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : Const_00
Oscillator is enabled, in operation
#01 : Const_01
Oscillator is enabled, in bypass mode
#10 : Const_10
Oscillator in power down
#11 : Const_11
Oscillator in power down, can be used as GPI
End of enumeration elements list.
Hibernate Domain Status Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEV : Wake-up Pin Event Positive Edge Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Clear wake-up event
End of enumeration elements list.
ENEV : Wake-up Pin Event Negative Edge Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Clear wake-up event
End of enumeration elements list.
RTCEV : RTC Event Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Clear wake-up event
End of enumeration elements list.
ULPWDG : ULP WDG Alarm Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Clear watchdog alarm
End of enumeration elements list.
Hibernate Domain Status Set Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEV : Wake-up Pin Event Positive Edge Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Set wake-up event
End of enumeration elements list.
ENEV : Wake-up Pin Event Negative Edge Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Set wake-up event
End of enumeration elements list.
RTCEV : RTC Event Set
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Set wake-up event
End of enumeration elements list.
ULPWDG : ULP WDG Alarm Set
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Set watchdog alarm
End of enumeration elements list.
Hibernate Domain Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKPEP : Wake-Up on Pin Event Positive Edge Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Wake-up event disabled
#1 : Const_1
Wake-up event enabled
End of enumeration elements list.
WKPEN : Wake-up on Pin Event Negative Edge Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Wake-up event disabled
#1 : Const_1
Wake-up event enabled
End of enumeration elements list.
RTCE : Wake-up on RTC Event Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Wake-up event disabled
#1 : Const_1
Wake-up event enabled
End of enumeration elements list.
ULPWDGEN : ULP WDG Alarm Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Wake-up event disabled
#1 : Const_1
Wake-up event enabled
End of enumeration elements list.
HIB : Hibernate Request Value Set
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
External hibernate request inactive
#1 : Const_1
External hibernate request active
End of enumeration elements list.
RCS : fRTC Clock Selection
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
fOSI selected
#1 : Const_1
fULP selected
End of enumeration elements list.
STDBYSEL : fSTDBY Clock Selection
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
fOSI selected
#1 : Const_1
fULP selected
End of enumeration elements list.
WKUPSEL : Wake-Up from Hibernate Trigger Input Selection
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
HIB_IO_1 pin selected
#1 : Const_1
HIB_IO_0 pin selected
End of enumeration elements list.
GPI0SEL : General Purpose Input 0 Selection
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
#0
#1 : Const_1
HIB_IO_0 pin selected
End of enumeration elements list.
HIBIO0POL : HIBIO0 Polarity Set
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Direct value
#1 : Const_1
Inverted value
End of enumeration elements list.
HIBIO1POL : HIBIO1 Polarity Set
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : Const_0
Direct value
#1 : Const_1
Inverted value
End of enumeration elements list.
HIBIO0SEL : HIB_IO_0 Pin I/O Control (default HIBOUT)
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#0000 : Const_0000
Direct input, No input pull device connected
#0001 : Const_0001
Direct input, Input pull-down device connected
#0010 : Const_0010
Direct input, Input pull-up device connected
#1000 : Const_1000
Push-pull HIB Control output
#1001 : Const_1001
Push-pull WDT service output
#1010 : Const_1010
Push-pull GPIO output
#1100 : Const_1100
Open-drain HIB Control output
#1101 : Const_1101
Open-drain WDT service output
#1110 : Const_1110
Open-drain GPIO output
#1111 : Const_1111
#1111
End of enumeration elements list.
HIBIO1SEL : HIB_IO_1 Pin I/O Control (Default WKUP)
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : Const_0000
Direct input, No input pull device connected
#0001 : Const_0001
Direct input, Input pull-down device connected
#0010 : Const_0010
Direct input, Input pull-up device connected
#1000 : Const_1000
Push-pull HIB Control output
#1001 : Const_1001
Push-pull WDT service output
#1010 : Const_1010
Push-pull GPIO output
#1100 : Const_1100
Open-drain HIB Control output
#1101 : Const_1101
Open-drain WDT service output
#1110 : Const_1110
Open-drain GPIO output
#1111 : Const_1111
#1111
End of enumeration elements list.
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