\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
RCU Reset Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTSTAT : Reset Status Information
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
#00000001 : Const_00000001
PORST reset
#00000010 : Const_00000010
SWD reset
#00000100 : Const_00000100
PV reset
#00001000 : Const_00001000
CPU system reset
#00010000 : Const_00010000
CPU lockup reset
#00100000 : Const_00100000
WDT reset
#10000000 : Const_10000000
Parity Error reset
End of enumeration elements list.
HIBWK : Hibernate Wake-up Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
No Wake-up
#1 : Const_1
Wake-up event
End of enumeration elements list.
HIBRS : Hibernate Reset Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
LCKEN : Enable Lockup Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset by Lockup disabled
#1 : Const_1
Reset by Lockup enabled
End of enumeration elements list.
ECAT0RS : ECAT0 Reset Status Information
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset did not occur
#1 : Const_1
Reset occurred
End of enumeration elements list.
RCU Peripheral 0 Reset Set
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VADCRS : VADC Reset Assert
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
CCU40RS : CCU40 Reset Assert
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
CCU41RS : CCU41 Reset Assert
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
CCU80RS : CCU80 Reset Assert
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
USIC0RS : USIC0 Reset Assert
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
ERU1RS : ERU1 Reset Assert
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
RCU Peripheral 0 Reset Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VADCRS : VADC Reset Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
CCU40RS : CCU40 Reset Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
CCU41RS : CCU41 Reset Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
CCU80RS : CCU80 Reset Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
USIC0RS : USIC0 Reset Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
ERU1RS : ERU1 Reset Clear
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
RCU Peripheral 1 Reset Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEDTSCU0RS : LEDTS Reset Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
MCAN0RS : MultiCAN Reset Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
DACRS : DAC Reset Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
MMCIRS : MMC Interface Reset Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
USIC1RS : USIC1 Reset Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
PPORTSRS : PORTS Reset Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
RCU Peripheral 1 Reset Set
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEDTSCU0RS : LEDTS Reset Assert
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
MCAN0RS : MultiCAN Reset Assert
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
DACRS : DAC Reset Assert
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
MMCIRS : MMC Interface Reset Assert
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
USIC1RS : USIC1 Reset Assert
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
PPORTSRS : PORTS Reset Assert
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
RCU Peripheral 1 Reset Clear
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEDTSCU0RS : LEDTS Reset Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
MCAN0RS : MultiCAN Reset Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
DACRS : DAC Reset Clear
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
MMCIRS : MMC Interface Reset Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
USIC1RS : USIC1 Reset Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
PPORTSRS : PORTS Reset Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
RCU Peripheral 2 Reset Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTRS : WDT Reset Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
ETH0RS : ETH0 Reset Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
DMA0RS : DMA0 Reset Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
FCERS : FCE Reset Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
USBRS : USB Reset Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
ECAT0RS : ECAT0 Reset Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
RCU Peripheral 2 Reset Set
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTRS : WDT Reset Assert
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
ETH0RS : ETH0 Reset Assert
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
DMA0RS : DMA0 Reset Assert
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
FCERS : FCE Reset Assert
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
USBRS : USB Reset Assert
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
ECAT0RS : ECAT0 Reset Assert
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
RCU Peripheral 2 Reset Clear
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTRS : WDT Reset Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
ETH0RS : ETH0 Reset Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
DMA0RS : DMA0 Reset Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
FCERS : FCE Reset Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
USBRS : USB Reset Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
ECAT0RS : ECAT0 Reset Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
RCU Reset Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIBWK : Set Hibernate Wake-up Reset Status
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset status bit
End of enumeration elements list.
HIBRS : Set Hibernate Reset
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset
End of enumeration elements list.
LCKEN : Enable Lockup Reset
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Enable reset when Lockup gets asserted
End of enumeration elements list.
ECAT0RS : ECAT0 Reset Status Information
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Assert reset status bit
End of enumeration elements list.
RCU Reset Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSCLR : Clear Reset Status
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Clears field RSTSTAT.RSTSTAT
End of enumeration elements list.
HIBWK : Clear Hibernate Wake-up Reset Status
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset status bit
End of enumeration elements list.
HIBRS : Clear Hibernate Reset
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset
End of enumeration elements list.
LCKEN : Enable Lockup Reset
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
Disable reset when Lockup gets asserted
End of enumeration elements list.
ECAT0RS : ECAT0 Reset Status Information
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : Const_0
No effect
#1 : Const_1
De-assert reset status
End of enumeration elements list.
RCU Peripheral 0 Reset Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VADCRS : VADC Reset Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
CCU40RS : CCU40 Reset Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
CCU41RS : CCU41 Reset Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
CCU80RS : CCU80 Reset Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
USIC0RS : USIC0 Reset Status
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
ERU1RS : ERU1 Reset Status
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : Const_0
Reset de-asserted
#1 : Const_1
Reset asserted
End of enumeration elements list.
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